drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38 };
  39
  40 static void band_gap_reset(struct drm_i915_private *dev_priv)
  41 {
  42         mutex_lock(&dev_priv->dpio_lock);
  43
  44         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  45         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  46         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  47         udelay(150);
  48         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  49         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  50
  51         mutex_unlock(&dev_priv->dpio_lock);
  52 }
  53
  54 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  55 {
  56         return container_of(intel_attached_encoder(connector),
  57                             struct intel_dsi, base);
  58 }
  59
  60 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  61 {
  62         return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
  63 }
  64
  65 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  66 {
  67         return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
  68 }
  69
  70 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  71 {
  72         DRM_DEBUG_KMS("\n");
  73 }
  74
  75 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  76                                      struct intel_crtc_config *config)
  77 {
  78         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  79                                                    base);
  80         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  81         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  82         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  83         struct drm_display_mode *mode = &config->requested_mode;
  84
  85         DRM_DEBUG_KMS("\n");
  86
  87         if (fixed_mode)
  88                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  89
  90         if (intel_dsi->dev.dev_ops->mode_fixup)
  91                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
  92                                                           mode, adjusted_mode);
  93
  94         return true;
  95 }
  96
  97 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
  98 {
  99         DRM_DEBUG_KMS("\n");
 100
 101         vlv_enable_dsi_pll(encoder);
 102 }
 103
 104 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 105 {
 106         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 107         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 108         int pipe = intel_crtc->pipe;
 109         u32 val;
 110
 111         DRM_DEBUG_KMS("\n");
 112
 113         mutex_lock(&dev_priv->dpio_lock);
 114         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 115          * needed everytime after power gate */
 116         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 117         mutex_unlock(&dev_priv->dpio_lock);
 118
 119         /* bandgap reset is needed after everytime we do power gate */
 120         band_gap_reset(dev_priv);
 121
 122         val = I915_READ(MIPI_PORT_CTRL(pipe));
 123         I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
 124         usleep_range(1000, 1500);
 125         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
 126         usleep_range(2000, 2500);
 127         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 128         usleep_range(2000, 2500);
 129         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 130         usleep_range(2000, 2500);
 131         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 132         usleep_range(2000, 2500);
 133 }
 134
 135 static void intel_dsi_enable(struct intel_encoder *encoder)
 136 {
 137         struct drm_device *dev = encoder->base.dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 140         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 141         int pipe = intel_crtc->pipe;
 142         u32 temp;
 143
 144         DRM_DEBUG_KMS("\n");
 145
 146         if (is_cmd_mode(intel_dsi))
 147                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 148         else {
 149                 msleep(20); /* XXX */
 150                 dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
 151                 msleep(100);
 152
 153                 if (intel_dsi->dev.dev_ops->enable)
 154                         intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 155
 156                 /* assert ip_tg_enable signal */
 157                 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
 158                 temp = temp | intel_dsi->port_bits;
 159                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 160                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 161         }
 162 }
 163
 164 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 165 {
 166         struct drm_device *dev = encoder->base.dev;
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 169         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 170         enum pipe pipe = intel_crtc->pipe;
 171         u32 tmp;
 172
 173         DRM_DEBUG_KMS("\n");
 174
 175         /* Disable DPOunit clock gating, can stall pipe
 176          * and we need DPLL REFA always enabled */
 177         tmp = I915_READ(DPLL(pipe));
 178         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 179         I915_WRITE(DPLL(pipe), tmp);
 180
 181         tmp = I915_READ(DSPCLK_GATE_D);
 182         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 183         I915_WRITE(DSPCLK_GATE_D, tmp);
 184
 185         /* put device in ready state */
 186         intel_dsi_device_ready(encoder);
 187
 188         if (intel_dsi->dev.dev_ops->panel_reset)
 189                 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
 190
 191         if (intel_dsi->dev.dev_ops->send_otp_cmds)
 192                 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 193
 194         /* Enable port in pre-enable phase itself because as per hw team
 195          * recommendation, port should be enabled befor plane & pipe */
 196         intel_dsi_enable(encoder);
 197 }
 198
 199 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 200 {
 201         DRM_DEBUG_KMS("\n");
 202
 203         /* for DSI port enable has to be done before pipe
 204          * and plane enable, so port enable is done in
 205          * pre_enable phase itself unlike other encoders
 206          */
 207 }
 208
 209 static void intel_dsi_disable(struct intel_encoder *encoder)
 210 {
 211         struct drm_device *dev = encoder->base.dev;
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 214         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 215         int pipe = intel_crtc->pipe;
 216         u32 temp;
 217
 218         DRM_DEBUG_KMS("\n");
 219
 220         if (is_vid_mode(intel_dsi)) {
 221                 /* Send Shutdown command to the panel in LP mode */
 222                 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
 223                 msleep(10);
 224
 225                 /* de-assert ip_tg_enable signal */
 226                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 227                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
 228                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 229
 230                 msleep(2);
 231         }
 232
 233         /* Panel commands can be sent when clock is in LP11 */
 234         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0);
 235
 236         temp = I915_READ(MIPI_CTRL(pipe));
 237         temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 238         I915_WRITE(MIPI_CTRL(pipe), temp |
 239                         intel_dsi->escape_clk_div <<
 240                         ESCAPE_CLOCK_DIVIDER_SHIFT);
 241
 242         I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
 243
 244         temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe));
 245         temp &= ~VID_MODE_FORMAT_MASK;
 246         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp);
 247
 248         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1);
 249
 250         /* if disable packets are sent before sending shutdown packet then in
 251          * some next enable sequence send turn on packet error is observed */
 252         if (intel_dsi->dev.dev_ops->disable)
 253                 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 254 }
 255
 256 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 257 {
 258         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 259         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 260         int pipe = intel_crtc->pipe;
 261         u32 val;
 262
 263         DRM_DEBUG_KMS("\n");
 264
 265         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 266         usleep_range(2000, 2500);
 267
 268         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
 269         usleep_range(2000, 2500);
 270
 271         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 272         usleep_range(2000, 2500);
 273
 274         val = I915_READ(MIPI_PORT_CTRL(pipe));
 275         I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
 276         usleep_range(1000, 1500);
 277
 278         if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
 279                                         == 0x00000), 30))
 280                 DRM_ERROR("DSI LP not going Low\n");
 281
 282         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 283         usleep_range(2000, 2500);
 284
 285         vlv_disable_dsi_pll(encoder);
 286 }
 287
 288 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 289 {
 290         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 291         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 292         u32 val;
 293
 294         DRM_DEBUG_KMS("\n");
 295
 296         intel_dsi_clear_device_ready(encoder);
 297
 298         val = I915_READ(DSPCLK_GATE_D);
 299         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 300         I915_WRITE(DSPCLK_GATE_D, val);
 301
 302         if (intel_dsi->dev.dev_ops->disable_panel_power)
 303                 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
 304 }
 305
 306 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 307                                    enum pipe *pipe)
 308 {
 309         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 310         enum intel_display_power_domain power_domain;
 311         u32 port, func;
 312         enum pipe p;
 313
 314         DRM_DEBUG_KMS("\n");
 315
 316         power_domain = intel_display_port_power_domain(encoder);
 317         if (!intel_display_power_enabled(dev_priv, power_domain))
 318                 return false;
 319
 320         /* XXX: this only works for one DSI output */
 321         for (p = PIPE_A; p <= PIPE_B; p++) {
 322                 port = I915_READ(MIPI_PORT_CTRL(p));
 323                 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
 324
 325                 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 326                         if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
 327                                 *pipe = p;
 328                                 return true;
 329                         }
 330                 }
 331         }
 332
 333         return false;
 334 }
 335
 336 static void intel_dsi_get_config(struct intel_encoder *encoder,
 337                                  struct intel_crtc_config *pipe_config)
 338 {
 339         DRM_DEBUG_KMS("\n");
 340
 341         /* XXX: read flags, set to adjusted_mode */
 342 }
 343
 344 static enum drm_mode_status
 345 intel_dsi_mode_valid(struct drm_connector *connector,
 346                      struct drm_display_mode *mode)
 347 {
 348         struct intel_connector *intel_connector = to_intel_connector(connector);
 349         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 350         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 351
 352         DRM_DEBUG_KMS("\n");
 353
 354         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 355                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 356                 return MODE_NO_DBLESCAN;
 357         }
 358
 359         if (fixed_mode) {
 360                 if (mode->hdisplay > fixed_mode->hdisplay)
 361                         return MODE_PANEL;
 362                 if (mode->vdisplay > fixed_mode->vdisplay)
 363                         return MODE_PANEL;
 364         }
 365
 366         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 367 }
 368
 369 /* return txclkesc cycles in terms of divider and duration in us */
 370 static u16 txclkesc(u32 divider, unsigned int us)
 371 {
 372         switch (divider) {
 373         case ESCAPE_CLOCK_DIVIDER_1:
 374         default:
 375                 return 20 * us;
 376         case ESCAPE_CLOCK_DIVIDER_2:
 377                 return 10 * us;
 378         case ESCAPE_CLOCK_DIVIDER_4:
 379                 return 5 * us;
 380         }
 381 }
 382
 383 /* return pixels in terms of txbyteclkhs */
 384 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
 385 {
 386         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
 387 }
 388
 389 static void set_dsi_timings(struct drm_encoder *encoder,
 390                             const struct drm_display_mode *mode)
 391 {
 392         struct drm_device *dev = encoder->dev;
 393         struct drm_i915_private *dev_priv = dev->dev_private;
 394         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 395         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 396         int pipe = intel_crtc->pipe;
 397         unsigned int bpp = intel_crtc->config.pipe_bpp;
 398         unsigned int lane_count = intel_dsi->lane_count;
 399
 400         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 401
 402         hactive = mode->hdisplay;
 403         hfp = mode->hsync_start - mode->hdisplay;
 404         hsync = mode->hsync_end - mode->hsync_start;
 405         hbp = mode->htotal - mode->hsync_end;
 406
 407         vfp = mode->vsync_start - mode->vdisplay;
 408         vsync = mode->vsync_end - mode->vsync_start;
 409         vbp = mode->vtotal - mode->vsync_end;
 410
 411         /* horizontal values are in terms of high speed byte clock */
 412         hactive = txbyteclkhs(hactive, bpp, lane_count);
 413         hfp = txbyteclkhs(hfp, bpp, lane_count);
 414         hsync = txbyteclkhs(hsync, bpp, lane_count);
 415         hbp = txbyteclkhs(hbp, bpp, lane_count);
 416
 417         I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
 418         I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
 419
 420         /* meaningful for video mode non-burst sync pulse mode only, can be zero
 421          * for non-burst sync events and burst modes */
 422         I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
 423         I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
 424
 425         /* vertical values are in terms of lines */
 426         I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
 427         I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
 428         I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 429 }
 430
 431 static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 432 {
 433         struct drm_encoder *encoder = &intel_encoder->base;
 434         struct drm_device *dev = encoder->dev;
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 437         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 438         struct drm_display_mode *adjusted_mode =
 439                 &intel_crtc->config.adjusted_mode;
 440         int pipe = intel_crtc->pipe;
 441         unsigned int bpp = intel_crtc->config.pipe_bpp;
 442         u32 val, tmp;
 443
 444         DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 445
 446         /* escape clock divider, 20MHz, shared for A and C. device ready must be
 447          * off when doing this! txclkesc? */
 448         tmp = I915_READ(MIPI_CTRL(0));
 449         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 450         I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
 451
 452         /* read request priority is per pipe */
 453         tmp = I915_READ(MIPI_CTRL(pipe));
 454         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 455         I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
 456
 457         /* XXX: why here, why like this? handling in irq handler?! */
 458         I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
 459         I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
 460
 461         I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
 462
 463         I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
 464                    adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 465                    adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 466
 467         set_dsi_timings(encoder, adjusted_mode);
 468
 469         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 470         if (is_cmd_mode(intel_dsi)) {
 471                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 472                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 473         } else {
 474                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 475
 476                 /* XXX: cross-check bpp vs. pixel format? */
 477                 val |= intel_dsi->pixel_format;
 478         }
 479         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
 480
 481         /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
 482          * stop state. */
 483
 484         /*
 485          * In burst mode, value greater than one DPI line Time in byte clock
 486          * (txbyteclkhs) To timeout this timer 1+ of the above said value is
 487          * recommended.
 488          *
 489          * In non-burst mode, Value greater than one DPI frame time in byte
 490          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 491          * is recommended.
 492          *
 493          * In DBI only mode, value greater than one DBI frame time in byte
 494          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 495          * is recommended.
 496          */
 497
 498         if (is_vid_mode(intel_dsi) &&
 499             intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 500                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 501                            txbyteclkhs(adjusted_mode->htotal, bpp,
 502                                        intel_dsi->lane_count) + 1);
 503         } else {
 504                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 505                            txbyteclkhs(adjusted_mode->vtotal *
 506                                        adjusted_mode->htotal,
 507                                        bpp, intel_dsi->lane_count) + 1);
 508         }
 509         I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
 510         I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
 511         I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
 512
 513         /* dphy stuff */
 514
 515         /* in terms of low power clock */
 516         I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
 517
 518         val = 0;
 519         if (intel_dsi->eotp_pkt == 0)
 520                 val |= EOT_DISABLE;
 521
 522         if (intel_dsi->clock_stop)
 523                 val |= CLOCKSTOP;
 524
 525         /* recovery disables */
 526         I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
 527
 528         /* in terms of txbyteclkhs. actual high to low switch +
 529          * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 530          *
 531          * XXX: write MIPI_STOP_STATE_STALL?
 532          */
 533         I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
 534                                                 intel_dsi->hs_to_lp_count);
 535
 536         /* XXX: low power clock equivalence in terms of byte clock. the number
 537          * of byte clocks occupied in one low power clock. based on txbyteclkhs
 538          * and txclkesc. txclkesc time / txbyteclk time * (105 +
 539          * MIPI_STOP_STATE_STALL) / 105.???
 540          */
 541         I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
 542
 543         /* the bw essential for transmitting 16 long packets containing 252
 544          * bytes meant for dcs write memory command is programmed in this
 545          * register in terms of byte clocks. based on dsi transfer rate and the
 546          * number of lanes configured the time taken to transmit 16 long packets
 547          * in a dsi stream varies. */
 548         I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
 549
 550         I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
 551                    intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 552                    intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 553
 554         if (is_vid_mode(intel_dsi))
 555                 /* Some panels might have resolution which is not a multiple of
 556                  * 64 like 1366 x 768. Enable RANDOM resolution support for such
 557                  * panels by default */
 558                 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 559                                 intel_dsi->video_frmt_cfg_bits |
 560                                 intel_dsi->video_mode_format |
 561                                 IP_TG_CONFIG |
 562                                 RANDOM_DPI_DISPLAY_RESOLUTION);
 563 }
 564
 565 static enum drm_connector_status
 566 intel_dsi_detect(struct drm_connector *connector, bool force)
 567 {
 568         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 569         struct intel_encoder *intel_encoder = &intel_dsi->base;
 570         enum intel_display_power_domain power_domain;
 571         enum drm_connector_status connector_status;
 572         struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
 573
 574         DRM_DEBUG_KMS("\n");
 575         power_domain = intel_display_port_power_domain(intel_encoder);
 576
 577         intel_display_power_get(dev_priv, power_domain);
 578         connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 579         intel_display_power_put(dev_priv, power_domain);
 580
 581         return connector_status;
 582 }
 583
 584 static int intel_dsi_get_modes(struct drm_connector *connector)
 585 {
 586         struct intel_connector *intel_connector = to_intel_connector(connector);
 587         struct drm_display_mode *mode;
 588
 589         DRM_DEBUG_KMS("\n");
 590
 591         if (!intel_connector->panel.fixed_mode) {
 592                 DRM_DEBUG_KMS("no fixed mode\n");
 593                 return 0;
 594         }
 595
 596         mode = drm_mode_duplicate(connector->dev,
 597                                   intel_connector->panel.fixed_mode);
 598         if (!mode) {
 599                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 600                 return 0;
 601         }
 602
 603         drm_mode_probed_add(connector, mode);
 604         return 1;
 605 }
 606
 607 static void intel_dsi_destroy(struct drm_connector *connector)
 608 {
 609         struct intel_connector *intel_connector = to_intel_connector(connector);
 610
 611         DRM_DEBUG_KMS("\n");
 612         intel_panel_fini(&intel_connector->panel);
 613         drm_connector_cleanup(connector);
 614         kfree(connector);
 615 }
 616
 617 static const struct drm_encoder_funcs intel_dsi_funcs = {
 618         .destroy = intel_encoder_destroy,
 619 };
 620
 621 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 622         .get_modes = intel_dsi_get_modes,
 623         .mode_valid = intel_dsi_mode_valid,
 624         .best_encoder = intel_best_encoder,
 625 };
 626
 627 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 628         .dpms = intel_connector_dpms,
 629         .detect = intel_dsi_detect,
 630         .destroy = intel_dsi_destroy,
 631         .fill_modes = drm_helper_probe_single_connector_modes,
 632 };
 633
 634 bool intel_dsi_init(struct drm_device *dev)
 635 {
 636         struct intel_dsi *intel_dsi;
 637         struct intel_encoder *intel_encoder;
 638         struct drm_encoder *encoder;
 639         struct intel_connector *intel_connector;
 640         struct drm_connector *connector;
 641         struct drm_display_mode *fixed_mode = NULL;
 642         const struct intel_dsi_device *dsi;
 643         unsigned int i;
 644
 645         DRM_DEBUG_KMS("\n");
 646
 647         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 648         if (!intel_dsi)
 649                 return false;
 650
 651         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 652         if (!intel_connector) {
 653                 kfree(intel_dsi);
 654                 return false;
 655         }
 656
 657         intel_encoder = &intel_dsi->base;
 658         encoder = &intel_encoder->base;
 659         intel_dsi->attached_connector = intel_connector;
 660
 661         connector = &intel_connector->base;
 662
 663         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 664
 665         /* XXX: very likely not all of these are needed */
 666         intel_encoder->hot_plug = intel_dsi_hot_plug;
 667         intel_encoder->compute_config = intel_dsi_compute_config;
 668         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 669         intel_encoder->pre_enable = intel_dsi_pre_enable;
 670         intel_encoder->enable = intel_dsi_enable_nop;
 671         intel_encoder->mode_set = intel_dsi_mode_set;
 672         intel_encoder->disable = intel_dsi_disable;
 673         intel_encoder->post_disable = intel_dsi_post_disable;
 674         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 675         intel_encoder->get_config = intel_dsi_get_config;
 676
 677         intel_connector->get_hw_state = intel_connector_get_hw_state;
 678         intel_connector->unregister = intel_connector_unregister;
 679
 680         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 681                 dsi = &intel_dsi_devices[i];
 682                 intel_dsi->dev = *dsi;
 683
 684                 if (dsi->dev_ops->init(&intel_dsi->dev))
 685                         break;
 686         }
 687
 688         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 689                 DRM_DEBUG_KMS("no device found\n");
 690                 goto err;
 691         }
 692
 693         intel_encoder->type = INTEL_OUTPUT_DSI;
 694         intel_encoder->crtc_mask = (1 << 0); /* XXX */
 695
 696         intel_encoder->cloneable = 0;
 697         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 698                            DRM_MODE_CONNECTOR_DSI);
 699
 700         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 701
 702         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 703         connector->interlace_allowed = false;
 704         connector->doublescan_allowed = false;
 705
 706         intel_connector_attach_encoder(intel_connector, intel_encoder);
 707
 708         drm_sysfs_connector_add(connector);
 709
 710         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 711         if (!fixed_mode) {
 712                 DRM_DEBUG_KMS("no fixed mode\n");
 713                 goto err;
 714         }
 715
 716         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 717         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 718
 719         return true;
 720
 721 err:
 722         drm_encoder_cleanup(&intel_encoder->base);
 723         kfree(intel_dsi);
 724         kfree(intel_connector);
 725
 726         return false;
 727 }