drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38         {
  39                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  40                 .name = "vbt-generic-dsi-vid-mode-display",
  41                 .dev_ops = &vbt_generic_dsi_display_ops,
  42         },
  43 };
  44
  45 static void band_gap_reset(struct drm_i915_private *dev_priv)
  46 {
  47         mutex_lock(&dev_priv->dpio_lock);
  48
  49         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  50         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  51         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  52         udelay(150);
  53         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  54         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  55
  56         mutex_unlock(&dev_priv->dpio_lock);
  57 }
  58
  59 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  60 {
  61         return container_of(intel_attached_encoder(connector),
  62                             struct intel_dsi, base);
  63 }
  64
  65 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  66 {
  67         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
  68 }
  69
  70 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  71 {
  72         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
  73 }
  74
  75 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  76 {
  77         DRM_DEBUG_KMS("\n");
  78 }
  79
  80 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  81                                      struct intel_crtc_config *config)
  82 {
  83         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  84                                                    base);
  85         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  86         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  87         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  88         struct drm_display_mode *mode = &config->requested_mode;
  89
  90         DRM_DEBUG_KMS("\n");
  91
  92         if (fixed_mode)
  93                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  94
  95         /* DSI uses short packets for sync events, so clear mode flags for DSI */
  96         adjusted_mode->flags = 0;
  97
  98         if (intel_dsi->dev.dev_ops->mode_fixup)
  99                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
 100                                                           mode, adjusted_mode);
 101
 102         return true;
 103 }
 104
 105 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 106 {
 107         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 108         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 109         int pipe = intel_crtc->pipe;
 110         u32 val;
 111
 112         DRM_DEBUG_KMS("\n");
 113
 114         mutex_lock(&dev_priv->dpio_lock);
 115         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 116          * needed everytime after power gate */
 117         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 118         mutex_unlock(&dev_priv->dpio_lock);
 119
 120         /* bandgap reset is needed after everytime we do power gate */
 121         band_gap_reset(dev_priv);
 122
 123         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 124         usleep_range(2500, 3000);
 125
 126         val = I915_READ(MIPI_PORT_CTRL(pipe));
 127         I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
 128         usleep_range(1000, 1500);
 129
 130         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
 131         usleep_range(2500, 3000);
 132
 133         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 134         usleep_range(2500, 3000);
 135 }
 136
 137 static void intel_dsi_enable(struct intel_encoder *encoder)
 138 {
 139         struct drm_device *dev = encoder->base.dev;
 140         struct drm_i915_private *dev_priv = dev->dev_private;
 141         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 142         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 143         int pipe = intel_crtc->pipe;
 144         u32 temp;
 145
 146         DRM_DEBUG_KMS("\n");
 147
 148         if (is_cmd_mode(intel_dsi))
 149                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 150         else {
 151                 msleep(20); /* XXX */
 152                 dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
 153                 msleep(100);
 154
 155                 if (intel_dsi->dev.dev_ops->enable)
 156                         intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 157
 158                 wait_for_dsi_fifo_empty(intel_dsi);
 159
 160                 /* assert ip_tg_enable signal */
 161                 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
 162                 temp = temp | intel_dsi->port_bits;
 163                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 164                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 165         }
 166 }
 167
 168 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 169 {
 170         struct drm_device *dev = encoder->base.dev;
 171         struct drm_i915_private *dev_priv = dev->dev_private;
 172         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 173         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 174         enum pipe pipe = intel_crtc->pipe;
 175         u32 tmp;
 176
 177         DRM_DEBUG_KMS("\n");
 178
 179         /* Disable DPOunit clock gating, can stall pipe
 180          * and we need DPLL REFA always enabled */
 181         tmp = I915_READ(DPLL(pipe));
 182         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 183         I915_WRITE(DPLL(pipe), tmp);
 184
 185         /* update the hw state for DPLL */
 186         intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
 187                 DPLL_REFA_CLK_ENABLE_VLV;
 188
 189         tmp = I915_READ(DSPCLK_GATE_D);
 190         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 191         I915_WRITE(DSPCLK_GATE_D, tmp);
 192
 193         /* put device in ready state */
 194         intel_dsi_device_ready(encoder);
 195
 196         msleep(intel_dsi->panel_on_delay);
 197
 198         if (intel_dsi->dev.dev_ops->panel_reset)
 199                 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
 200
 201         if (intel_dsi->dev.dev_ops->send_otp_cmds)
 202                 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 203
 204         wait_for_dsi_fifo_empty(intel_dsi);
 205
 206         /* Enable port in pre-enable phase itself because as per hw team
 207          * recommendation, port should be enabled befor plane & pipe */
 208         intel_dsi_enable(encoder);
 209 }
 210
 211 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 212 {
 213         DRM_DEBUG_KMS("\n");
 214
 215         /* for DSI port enable has to be done before pipe
 216          * and plane enable, so port enable is done in
 217          * pre_enable phase itself unlike other encoders
 218          */
 219 }
 220
 221 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 222 {
 223         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 224
 225         DRM_DEBUG_KMS("\n");
 226
 227         if (is_vid_mode(intel_dsi)) {
 228                 /* Send Shutdown command to the panel in LP mode */
 229                 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
 230                 msleep(10);
 231         }
 232 }
 233
 234 static void intel_dsi_disable(struct intel_encoder *encoder)
 235 {
 236         struct drm_device *dev = encoder->base.dev;
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 239         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 240         int pipe = intel_crtc->pipe;
 241         u32 temp;
 242
 243         DRM_DEBUG_KMS("\n");
 244
 245         if (is_vid_mode(intel_dsi)) {
 246                 wait_for_dsi_fifo_empty(intel_dsi);
 247
 248                 /* de-assert ip_tg_enable signal */
 249                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 250                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
 251                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 252
 253                 msleep(2);
 254         }
 255
 256         /* Panel commands can be sent when clock is in LP11 */
 257         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0);
 258
 259         temp = I915_READ(MIPI_CTRL(pipe));
 260         temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 261         I915_WRITE(MIPI_CTRL(pipe), temp |
 262                    intel_dsi->escape_clk_div <<
 263                    ESCAPE_CLOCK_DIVIDER_SHIFT);
 264
 265         I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
 266
 267         temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe));
 268         temp &= ~VID_MODE_FORMAT_MASK;
 269         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp);
 270
 271         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1);
 272
 273         /* if disable packets are sent before sending shutdown packet then in
 274          * some next enable sequence send turn on packet error is observed */
 275         if (intel_dsi->dev.dev_ops->disable)
 276                 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 277
 278         wait_for_dsi_fifo_empty(intel_dsi);
 279 }
 280
 281 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 282 {
 283         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 284         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 285         int pipe = intel_crtc->pipe;
 286         u32 val;
 287
 288         DRM_DEBUG_KMS("\n");
 289
 290         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
 291         usleep_range(2000, 2500);
 292
 293         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
 294         usleep_range(2000, 2500);
 295
 296         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
 297         usleep_range(2000, 2500);
 298
 299         if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
 300                       == 0x00000), 30))
 301                 DRM_ERROR("DSI LP not going Low\n");
 302
 303         val = I915_READ(MIPI_PORT_CTRL(pipe));
 304         I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
 305         usleep_range(1000, 1500);
 306
 307         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 308         usleep_range(2000, 2500);
 309
 310         vlv_disable_dsi_pll(encoder);
 311 }
 312
 313 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 314 {
 315         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 316         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 317         u32 val;
 318
 319         DRM_DEBUG_KMS("\n");
 320
 321         intel_dsi_disable(encoder);
 322
 323         intel_dsi_clear_device_ready(encoder);
 324
 325         val = I915_READ(DSPCLK_GATE_D);
 326         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 327         I915_WRITE(DSPCLK_GATE_D, val);
 328
 329         if (intel_dsi->dev.dev_ops->disable_panel_power)
 330                 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
 331
 332         msleep(intel_dsi->panel_off_delay);
 333         msleep(intel_dsi->panel_pwr_cycle_delay);
 334 }
 335
 336 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 337                                    enum pipe *pipe)
 338 {
 339         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 340         enum intel_display_power_domain power_domain;
 341         u32 port, func;
 342         enum pipe p;
 343
 344         DRM_DEBUG_KMS("\n");
 345
 346         power_domain = intel_display_port_power_domain(encoder);
 347         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 348                 return false;
 349
 350         /* XXX: this only works for one DSI output */
 351         for (p = PIPE_A; p <= PIPE_B; p++) {
 352                 port = I915_READ(MIPI_PORT_CTRL(p));
 353                 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
 354
 355                 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 356                         if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
 357                                 *pipe = p;
 358                                 return true;
 359                         }
 360                 }
 361         }
 362
 363         return false;
 364 }
 365
 366 static void intel_dsi_get_config(struct intel_encoder *encoder,
 367                                  struct intel_crtc_config *pipe_config)
 368 {
 369         u32 pclk;
 370         DRM_DEBUG_KMS("\n");
 371
 372         /*
 373          * DPLL_MD is not used in case of DSI, reading will get some default value
 374          * set dpll_md = 0
 375          */
 376         pipe_config->dpll_hw_state.dpll_md = 0;
 377
 378         pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 379         if (!pclk)
 380                 return;
 381
 382         pipe_config->adjusted_mode.crtc_clock = pclk;
 383         pipe_config->port_clock = pclk;
 384 }
 385
 386 static enum drm_mode_status
 387 intel_dsi_mode_valid(struct drm_connector *connector,
 388                      struct drm_display_mode *mode)
 389 {
 390         struct intel_connector *intel_connector = to_intel_connector(connector);
 391         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 392         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 393
 394         DRM_DEBUG_KMS("\n");
 395
 396         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 397                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 398                 return MODE_NO_DBLESCAN;
 399         }
 400
 401         if (fixed_mode) {
 402                 if (mode->hdisplay > fixed_mode->hdisplay)
 403                         return MODE_PANEL;
 404                 if (mode->vdisplay > fixed_mode->vdisplay)
 405                         return MODE_PANEL;
 406         }
 407
 408         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 409 }
 410
 411 /* return txclkesc cycles in terms of divider and duration in us */
 412 static u16 txclkesc(u32 divider, unsigned int us)
 413 {
 414         switch (divider) {
 415         case ESCAPE_CLOCK_DIVIDER_1:
 416         default:
 417                 return 20 * us;
 418         case ESCAPE_CLOCK_DIVIDER_2:
 419                 return 10 * us;
 420         case ESCAPE_CLOCK_DIVIDER_4:
 421                 return 5 * us;
 422         }
 423 }
 424
 425 /* return pixels in terms of txbyteclkhs */
 426 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
 427                        u16 burst_mode_ratio)
 428 {
 429         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
 430                                          8 * 100), lane_count);
 431 }
 432
 433 static void set_dsi_timings(struct drm_encoder *encoder,
 434                             const struct drm_display_mode *mode)
 435 {
 436         struct drm_device *dev = encoder->dev;
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 439         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 440         int pipe = intel_crtc->pipe;
 441         unsigned int bpp = intel_crtc->config.pipe_bpp;
 442         unsigned int lane_count = intel_dsi->lane_count;
 443
 444         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 445
 446         hactive = mode->hdisplay;
 447         hfp = mode->hsync_start - mode->hdisplay;
 448         hsync = mode->hsync_end - mode->hsync_start;
 449         hbp = mode->htotal - mode->hsync_end;
 450
 451         vfp = mode->vsync_start - mode->vdisplay;
 452         vsync = mode->vsync_end - mode->vsync_start;
 453         vbp = mode->vtotal - mode->vsync_end;
 454
 455         /* horizontal values are in terms of high speed byte clock */
 456         hactive = txbyteclkhs(hactive, bpp, lane_count,
 457                               intel_dsi->burst_mode_ratio);
 458         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 459         hsync = txbyteclkhs(hsync, bpp, lane_count,
 460                             intel_dsi->burst_mode_ratio);
 461         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 462
 463         I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
 464         I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
 465
 466         /* meaningful for video mode non-burst sync pulse mode only, can be zero
 467          * for non-burst sync events and burst modes */
 468         I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
 469         I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
 470
 471         /* vertical values are in terms of lines */
 472         I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
 473         I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
 474         I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 475 }
 476
 477 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 478 {
 479         struct drm_encoder *encoder = &intel_encoder->base;
 480         struct drm_device *dev = encoder->dev;
 481         struct drm_i915_private *dev_priv = dev->dev_private;
 482         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 483         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 484         struct drm_display_mode *adjusted_mode =
 485                 &intel_crtc->config.adjusted_mode;
 486         int pipe = intel_crtc->pipe;
 487         unsigned int bpp = intel_crtc->config.pipe_bpp;
 488         u32 val, tmp;
 489
 490         DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 491
 492         /* escape clock divider, 20MHz, shared for A and C. device ready must be
 493          * off when doing this! txclkesc? */
 494         tmp = I915_READ(MIPI_CTRL(0));
 495         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 496         I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
 497
 498         /* read request priority is per pipe */
 499         tmp = I915_READ(MIPI_CTRL(pipe));
 500         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 501         I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
 502
 503         /* XXX: why here, why like this? handling in irq handler?! */
 504         I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
 505         I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
 506
 507         I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
 508
 509         I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
 510                    adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 511                    adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 512
 513         set_dsi_timings(encoder, adjusted_mode);
 514
 515         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 516         if (is_cmd_mode(intel_dsi)) {
 517                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 518                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 519         } else {
 520                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 521
 522                 /* XXX: cross-check bpp vs. pixel format? */
 523                 val |= intel_dsi->pixel_format;
 524         }
 525         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
 526
 527         /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
 528          * stop state. */
 529
 530         /*
 531          * In burst mode, value greater than one DPI line Time in byte clock
 532          * (txbyteclkhs) To timeout this timer 1+ of the above said value is
 533          * recommended.
 534          *
 535          * In non-burst mode, Value greater than one DPI frame time in byte
 536          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 537          * is recommended.
 538          *
 539          * In DBI only mode, value greater than one DBI frame time in byte
 540          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 541          * is recommended.
 542          */
 543
 544         if (is_vid_mode(intel_dsi) &&
 545             intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 546                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 547                            txbyteclkhs(adjusted_mode->htotal, bpp,
 548                                        intel_dsi->lane_count,
 549                                        intel_dsi->burst_mode_ratio) + 1);
 550         } else {
 551                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 552                            txbyteclkhs(adjusted_mode->vtotal *
 553                                        adjusted_mode->htotal,
 554                                        bpp, intel_dsi->lane_count,
 555                                        intel_dsi->burst_mode_ratio) + 1);
 556         }
 557         I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
 558         I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
 559         I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
 560
 561         /* dphy stuff */
 562
 563         /* in terms of low power clock */
 564         I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
 565
 566         val = 0;
 567         if (intel_dsi->eotp_pkt == 0)
 568                 val |= EOT_DISABLE;
 569
 570         if (intel_dsi->clock_stop)
 571                 val |= CLOCKSTOP;
 572
 573         /* recovery disables */
 574         I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
 575
 576         /* in terms of low power clock */
 577         I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count);
 578
 579         /* in terms of txbyteclkhs. actual high to low switch +
 580          * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 581          *
 582          * XXX: write MIPI_STOP_STATE_STALL?
 583          */
 584         I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
 585                    intel_dsi->hs_to_lp_count);
 586
 587         /* XXX: low power clock equivalence in terms of byte clock. the number
 588          * of byte clocks occupied in one low power clock. based on txbyteclkhs
 589          * and txclkesc. txclkesc time / txbyteclk time * (105 +
 590          * MIPI_STOP_STATE_STALL) / 105.???
 591          */
 592         I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
 593
 594         /* the bw essential for transmitting 16 long packets containing 252
 595          * bytes meant for dcs write memory command is programmed in this
 596          * register in terms of byte clocks. based on dsi transfer rate and the
 597          * number of lanes configured the time taken to transmit 16 long packets
 598          * in a dsi stream varies. */
 599         I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
 600
 601         I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
 602                    intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 603                    intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 604
 605         if (is_vid_mode(intel_dsi))
 606                 /* Some panels might have resolution which is not a multiple of
 607                  * 64 like 1366 x 768. Enable RANDOM resolution support for such
 608                  * panels by default */
 609                 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 610                            intel_dsi->video_frmt_cfg_bits |
 611                            intel_dsi->video_mode_format |
 612                            IP_TG_CONFIG |
 613                            RANDOM_DPI_DISPLAY_RESOLUTION);
 614 }
 615
 616 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 617 {
 618         DRM_DEBUG_KMS("\n");
 619
 620         intel_dsi_prepare(encoder);
 621
 622         vlv_enable_dsi_pll(encoder);
 623 }
 624
 625 static enum drm_connector_status
 626 intel_dsi_detect(struct drm_connector *connector, bool force)
 627 {
 628         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 629         struct intel_encoder *intel_encoder = &intel_dsi->base;
 630         enum intel_display_power_domain power_domain;
 631         enum drm_connector_status connector_status;
 632         struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
 633
 634         DRM_DEBUG_KMS("\n");
 635         power_domain = intel_display_port_power_domain(intel_encoder);
 636
 637         intel_display_power_get(dev_priv, power_domain);
 638         connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 639         intel_display_power_put(dev_priv, power_domain);
 640
 641         return connector_status;
 642 }
 643
 644 static int intel_dsi_get_modes(struct drm_connector *connector)
 645 {
 646         struct intel_connector *intel_connector = to_intel_connector(connector);
 647         struct drm_display_mode *mode;
 648
 649         DRM_DEBUG_KMS("\n");
 650
 651         if (!intel_connector->panel.fixed_mode) {
 652                 DRM_DEBUG_KMS("no fixed mode\n");
 653                 return 0;
 654         }
 655
 656         mode = drm_mode_duplicate(connector->dev,
 657                                   intel_connector->panel.fixed_mode);
 658         if (!mode) {
 659                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 660                 return 0;
 661         }
 662
 663         drm_mode_probed_add(connector, mode);
 664         return 1;
 665 }
 666
 667 static void intel_dsi_destroy(struct drm_connector *connector)
 668 {
 669         struct intel_connector *intel_connector = to_intel_connector(connector);
 670
 671         DRM_DEBUG_KMS("\n");
 672         intel_panel_fini(&intel_connector->panel);
 673         drm_connector_cleanup(connector);
 674         kfree(connector);
 675 }
 676
 677 static const struct drm_encoder_funcs intel_dsi_funcs = {
 678         .destroy = intel_encoder_destroy,
 679 };
 680
 681 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 682         .get_modes = intel_dsi_get_modes,
 683         .mode_valid = intel_dsi_mode_valid,
 684         .best_encoder = intel_best_encoder,
 685 };
 686
 687 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 688         .dpms = intel_connector_dpms,
 689         .detect = intel_dsi_detect,
 690         .destroy = intel_dsi_destroy,
 691         .fill_modes = drm_helper_probe_single_connector_modes,
 692 };
 693
 694 void intel_dsi_init(struct drm_device *dev)
 695 {
 696         struct intel_dsi *intel_dsi;
 697         struct intel_encoder *intel_encoder;
 698         struct drm_encoder *encoder;
 699         struct intel_connector *intel_connector;
 700         struct drm_connector *connector;
 701         struct drm_display_mode *fixed_mode = NULL;
 702         struct drm_i915_private *dev_priv = dev->dev_private;
 703         const struct intel_dsi_device *dsi;
 704         unsigned int i;
 705
 706         DRM_DEBUG_KMS("\n");
 707
 708         /* There is no detection method for MIPI so rely on VBT */
 709         if (!dev_priv->vbt.has_mipi)
 710                 return;
 711
 712         if (IS_VALLEYVIEW(dev)) {
 713                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
 714         } else {
 715                 DRM_ERROR("Unsupported Mipi device to reg base");
 716                 return;
 717         }
 718
 719         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 720         if (!intel_dsi)
 721                 return;
 722
 723         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 724         if (!intel_connector) {
 725                 kfree(intel_dsi);
 726                 return;
 727         }
 728
 729         intel_encoder = &intel_dsi->base;
 730         encoder = &intel_encoder->base;
 731         intel_dsi->attached_connector = intel_connector;
 732
 733         connector = &intel_connector->base;
 734
 735         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 736
 737         /* XXX: very likely not all of these are needed */
 738         intel_encoder->hot_plug = intel_dsi_hot_plug;
 739         intel_encoder->compute_config = intel_dsi_compute_config;
 740         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 741         intel_encoder->pre_enable = intel_dsi_pre_enable;
 742         intel_encoder->enable = intel_dsi_enable_nop;
 743         intel_encoder->disable = intel_dsi_pre_disable;
 744         intel_encoder->post_disable = intel_dsi_post_disable;
 745         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 746         intel_encoder->get_config = intel_dsi_get_config;
 747
 748         intel_connector->get_hw_state = intel_connector_get_hw_state;
 749         intel_connector->unregister = intel_connector_unregister;
 750
 751         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 752                 dsi = &intel_dsi_devices[i];
 753                 intel_dsi->dev = *dsi;
 754
 755                 if (dsi->dev_ops->init(&intel_dsi->dev))
 756                         break;
 757         }
 758
 759         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 760                 DRM_DEBUG_KMS("no device found\n");
 761                 goto err;
 762         }
 763
 764         intel_encoder->type = INTEL_OUTPUT_DSI;
 765         intel_encoder->crtc_mask = (1 << 0); /* XXX */
 766
 767         intel_encoder->cloneable = 0;
 768         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 769                            DRM_MODE_CONNECTOR_DSI);
 770
 771         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 772
 773         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 774         connector->interlace_allowed = false;
 775         connector->doublescan_allowed = false;
 776
 777         intel_connector_attach_encoder(intel_connector, intel_encoder);
 778
 779         drm_connector_register(connector);
 780
 781         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 782         if (!fixed_mode) {
 783                 DRM_DEBUG_KMS("no fixed mode\n");
 784                 goto err;
 785         }
 786
 787         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 788         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 789
 790         return;
 791
 792 err:
 793         drm_encoder_cleanup(&intel_encoder->base);
 794         kfree(intel_dsi);
 795         kfree(intel_connector);
 796 }