drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38 };
  39
  40 static void band_gap_reset(struct drm_i915_private *dev_priv)
  41 {
  42         mutex_lock(&dev_priv->dpio_lock);
  43
  44         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  45         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  46         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  47         udelay(150);
  48         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  49         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  50
  51         mutex_unlock(&dev_priv->dpio_lock);
  52 }
  53
  54 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  55 {
  56         return container_of(intel_attached_encoder(connector),
  57                             struct intel_dsi, base);
  58 }
  59
  60 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  61 {
  62         return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
  63 }
  64
  65 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  66 {
  67         return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
  68 }
  69
  70 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  71 {
  72         DRM_DEBUG_KMS("\n");
  73 }
  74
  75 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  76                                      struct intel_crtc_config *config)
  77 {
  78         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  79                                                    base);
  80         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  81         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  82         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  83         struct drm_display_mode *mode = &config->requested_mode;
  84
  85         DRM_DEBUG_KMS("\n");
  86
  87         if (fixed_mode)
  88                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  89
  90         if (intel_dsi->dev.dev_ops->mode_fixup)
  91                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
  92                                                           mode, adjusted_mode);
  93
  94         return true;
  95 }
  96
  97 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
  98 {
  99         DRM_DEBUG_KMS("\n");
 100
 101         vlv_enable_dsi_pll(encoder);
 102 }
 103
 104 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 105 {
 106         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 107         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 108         int pipe = intel_crtc->pipe;
 109         u32 val;
 110
 111         DRM_DEBUG_KMS("\n");
 112
 113         mutex_lock(&dev_priv->dpio_lock);
 114         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 115          * needed everytime after power gate */
 116         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 117         mutex_unlock(&dev_priv->dpio_lock);
 118
 119         /* bandgap reset is needed after everytime we do power gate */
 120         band_gap_reset(dev_priv);
 121
 122         val = I915_READ(MIPI_PORT_CTRL(pipe));
 123         I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
 124         usleep_range(1000, 1500);
 125         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
 126         usleep_range(2000, 2500);
 127         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 128         usleep_range(2000, 2500);
 129         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 130         usleep_range(2000, 2500);
 131         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 132         usleep_range(2000, 2500);
 133 }
 134
 135 static void intel_dsi_enable(struct intel_encoder *encoder)
 136 {
 137         struct drm_device *dev = encoder->base.dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 140         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 141         int pipe = intel_crtc->pipe;
 142         u32 temp;
 143
 144         DRM_DEBUG_KMS("\n");
 145
 146         if (is_cmd_mode(intel_dsi))
 147                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 148         else {
 149                 msleep(20); /* XXX */
 150                 dpi_send_cmd(intel_dsi, TURN_ON);
 151                 msleep(100);
 152
 153                 if (intel_dsi->dev.dev_ops->enable)
 154                         intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 155
 156                 /* assert ip_tg_enable signal */
 157                 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
 158                 temp = temp | intel_dsi->port_bits;
 159                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 160                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 161         }
 162 }
 163
 164 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 165 {
 166         struct drm_device *dev = encoder->base.dev;
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 169         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 170         enum pipe pipe = intel_crtc->pipe;
 171         u32 tmp;
 172
 173         DRM_DEBUG_KMS("\n");
 174
 175         /* Disable DPOunit clock gating, can stall pipe
 176          * and we need DPLL REFA always enabled */
 177         tmp = I915_READ(DPLL(pipe));
 178         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 179         I915_WRITE(DPLL(pipe), tmp);
 180
 181         tmp = I915_READ(DSPCLK_GATE_D);
 182         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 183         I915_WRITE(DSPCLK_GATE_D, tmp);
 184
 185         /* put device in ready state */
 186         intel_dsi_device_ready(encoder);
 187
 188         if (intel_dsi->dev.dev_ops->panel_reset)
 189                 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
 190
 191         if (intel_dsi->dev.dev_ops->send_otp_cmds)
 192                 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 193
 194         /* Enable port in pre-enable phase itself because as per hw team
 195          * recommendation, port should be enabled befor plane & pipe */
 196         intel_dsi_enable(encoder);
 197 }
 198
 199 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 200 {
 201         DRM_DEBUG_KMS("\n");
 202
 203         /* for DSI port enable has to be done before pipe
 204          * and plane enable, so port enable is done in
 205          * pre_enable phase itself unlike other encoders
 206          */
 207 }
 208
 209 static void intel_dsi_disable(struct intel_encoder *encoder)
 210 {
 211         struct drm_device *dev = encoder->base.dev;
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 214         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 215         int pipe = intel_crtc->pipe;
 216         u32 temp;
 217
 218         DRM_DEBUG_KMS("\n");
 219
 220         if (is_vid_mode(intel_dsi)) {
 221                 dpi_send_cmd(intel_dsi, SHUTDOWN);
 222                 msleep(10);
 223
 224                 /* de-assert ip_tg_enable signal */
 225                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 226                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
 227                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 228
 229                 msleep(2);
 230         }
 231
 232         /* if disable packets are sent before sending shutdown packet then in
 233          * some next enable sequence send turn on packet error is observed */
 234         if (intel_dsi->dev.dev_ops->disable)
 235                 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 236 }
 237
 238 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 239 {
 240         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 241         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 242         int pipe = intel_crtc->pipe;
 243         u32 val;
 244
 245         DRM_DEBUG_KMS("\n");
 246
 247         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 248         usleep_range(2000, 2500);
 249
 250         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
 251         usleep_range(2000, 2500);
 252
 253         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 254         usleep_range(2000, 2500);
 255
 256         val = I915_READ(MIPI_PORT_CTRL(pipe));
 257         I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
 258         usleep_range(1000, 1500);
 259
 260         if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
 261                                         == 0x00000), 30))
 262                 DRM_ERROR("DSI LP not going Low\n");
 263
 264         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 265         usleep_range(2000, 2500);
 266
 267         vlv_disable_dsi_pll(encoder);
 268 }
 269
 270 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 271 {
 272         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 273         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 274         u32 val;
 275
 276         DRM_DEBUG_KMS("\n");
 277
 278         intel_dsi_clear_device_ready(encoder);
 279
 280         val = I915_READ(DSPCLK_GATE_D);
 281         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 282         I915_WRITE(DSPCLK_GATE_D, val);
 283
 284         if (intel_dsi->dev.dev_ops->disable_panel_power)
 285                 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
 286 }
 287
 288 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 289                                    enum pipe *pipe)
 290 {
 291         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 292         enum intel_display_power_domain power_domain;
 293         u32 port, func;
 294         enum pipe p;
 295
 296         DRM_DEBUG_KMS("\n");
 297
 298         power_domain = intel_display_port_power_domain(encoder);
 299         if (!intel_display_power_enabled(dev_priv, power_domain))
 300                 return false;
 301
 302         /* XXX: this only works for one DSI output */
 303         for (p = PIPE_A; p <= PIPE_B; p++) {
 304                 port = I915_READ(MIPI_PORT_CTRL(p));
 305                 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
 306
 307                 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 308                         if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
 309                                 *pipe = p;
 310                                 return true;
 311                         }
 312                 }
 313         }
 314
 315         return false;
 316 }
 317
 318 static void intel_dsi_get_config(struct intel_encoder *encoder,
 319                                  struct intel_crtc_config *pipe_config)
 320 {
 321         DRM_DEBUG_KMS("\n");
 322
 323         /* XXX: read flags, set to adjusted_mode */
 324 }
 325
 326 static enum drm_mode_status
 327 intel_dsi_mode_valid(struct drm_connector *connector,
 328                      struct drm_display_mode *mode)
 329 {
 330         struct intel_connector *intel_connector = to_intel_connector(connector);
 331         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 332         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 333
 334         DRM_DEBUG_KMS("\n");
 335
 336         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 337                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 338                 return MODE_NO_DBLESCAN;
 339         }
 340
 341         if (fixed_mode) {
 342                 if (mode->hdisplay > fixed_mode->hdisplay)
 343                         return MODE_PANEL;
 344                 if (mode->vdisplay > fixed_mode->vdisplay)
 345                         return MODE_PANEL;
 346         }
 347
 348         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 349 }
 350
 351 /* return txclkesc cycles in terms of divider and duration in us */
 352 static u16 txclkesc(u32 divider, unsigned int us)
 353 {
 354         switch (divider) {
 355         case ESCAPE_CLOCK_DIVIDER_1:
 356         default:
 357                 return 20 * us;
 358         case ESCAPE_CLOCK_DIVIDER_2:
 359                 return 10 * us;
 360         case ESCAPE_CLOCK_DIVIDER_4:
 361                 return 5 * us;
 362         }
 363 }
 364
 365 /* return pixels in terms of txbyteclkhs */
 366 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
 367 {
 368         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
 369 }
 370
 371 static void set_dsi_timings(struct drm_encoder *encoder,
 372                             const struct drm_display_mode *mode)
 373 {
 374         struct drm_device *dev = encoder->dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 377         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 378         int pipe = intel_crtc->pipe;
 379         unsigned int bpp = intel_crtc->config.pipe_bpp;
 380         unsigned int lane_count = intel_dsi->lane_count;
 381
 382         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 383
 384         hactive = mode->hdisplay;
 385         hfp = mode->hsync_start - mode->hdisplay;
 386         hsync = mode->hsync_end - mode->hsync_start;
 387         hbp = mode->htotal - mode->hsync_end;
 388
 389         vfp = mode->vsync_start - mode->vdisplay;
 390         vsync = mode->vsync_end - mode->vsync_start;
 391         vbp = mode->vtotal - mode->vsync_end;
 392
 393         /* horizontal values are in terms of high speed byte clock */
 394         hactive = txbyteclkhs(hactive, bpp, lane_count);
 395         hfp = txbyteclkhs(hfp, bpp, lane_count);
 396         hsync = txbyteclkhs(hsync, bpp, lane_count);
 397         hbp = txbyteclkhs(hbp, bpp, lane_count);
 398
 399         I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
 400         I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
 401
 402         /* meaningful for video mode non-burst sync pulse mode only, can be zero
 403          * for non-burst sync events and burst modes */
 404         I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
 405         I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
 406
 407         /* vertical values are in terms of lines */
 408         I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
 409         I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
 410         I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 411 }
 412
 413 static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 414 {
 415         struct drm_encoder *encoder = &intel_encoder->base;
 416         struct drm_device *dev = encoder->dev;
 417         struct drm_i915_private *dev_priv = dev->dev_private;
 418         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 419         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 420         struct drm_display_mode *adjusted_mode =
 421                 &intel_crtc->config.adjusted_mode;
 422         int pipe = intel_crtc->pipe;
 423         unsigned int bpp = intel_crtc->config.pipe_bpp;
 424         u32 val, tmp;
 425
 426         DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 427
 428         /* escape clock divider, 20MHz, shared for A and C. device ready must be
 429          * off when doing this! txclkesc? */
 430         tmp = I915_READ(MIPI_CTRL(0));
 431         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 432         I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
 433
 434         /* read request priority is per pipe */
 435         tmp = I915_READ(MIPI_CTRL(pipe));
 436         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 437         I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
 438
 439         /* XXX: why here, why like this? handling in irq handler?! */
 440         I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
 441         I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
 442
 443         I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
 444
 445         I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
 446                    adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 447                    adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 448
 449         set_dsi_timings(encoder, adjusted_mode);
 450
 451         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 452         if (is_cmd_mode(intel_dsi)) {
 453                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 454                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 455         } else {
 456                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 457
 458                 /* XXX: cross-check bpp vs. pixel format? */
 459                 val |= intel_dsi->pixel_format;
 460         }
 461         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
 462
 463         /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
 464          * stop state. */
 465
 466         /*
 467          * In burst mode, value greater than one DPI line Time in byte clock
 468          * (txbyteclkhs) To timeout this timer 1+ of the above said value is
 469          * recommended.
 470          *
 471          * In non-burst mode, Value greater than one DPI frame time in byte
 472          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 473          * is recommended.
 474          *
 475          * In DBI only mode, value greater than one DBI frame time in byte
 476          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 477          * is recommended.
 478          */
 479
 480         if (is_vid_mode(intel_dsi) &&
 481             intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 482                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 483                            txbyteclkhs(adjusted_mode->htotal, bpp,
 484                                        intel_dsi->lane_count) + 1);
 485         } else {
 486                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 487                            txbyteclkhs(adjusted_mode->vtotal *
 488                                        adjusted_mode->htotal,
 489                                        bpp, intel_dsi->lane_count) + 1);
 490         }
 491         I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
 492         I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
 493         I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
 494
 495         /* dphy stuff */
 496
 497         /* in terms of low power clock */
 498         I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
 499
 500         val = 0;
 501         if (intel_dsi->eotp_pkt == 0)
 502                 val |= EOT_DISABLE;
 503
 504         if (intel_dsi->clock_stop)
 505                 val |= CLOCKSTOP;
 506
 507         /* recovery disables */
 508         I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
 509
 510         /* in terms of txbyteclkhs. actual high to low switch +
 511          * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 512          *
 513          * XXX: write MIPI_STOP_STATE_STALL?
 514          */
 515         I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
 516                                                 intel_dsi->hs_to_lp_count);
 517
 518         /* XXX: low power clock equivalence in terms of byte clock. the number
 519          * of byte clocks occupied in one low power clock. based on txbyteclkhs
 520          * and txclkesc. txclkesc time / txbyteclk time * (105 +
 521          * MIPI_STOP_STATE_STALL) / 105.???
 522          */
 523         I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
 524
 525         /* the bw essential for transmitting 16 long packets containing 252
 526          * bytes meant for dcs write memory command is programmed in this
 527          * register in terms of byte clocks. based on dsi transfer rate and the
 528          * number of lanes configured the time taken to transmit 16 long packets
 529          * in a dsi stream varies. */
 530         I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
 531
 532         I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
 533                    intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 534                    intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 535
 536         if (is_vid_mode(intel_dsi))
 537                 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 538                                 intel_dsi->video_frmt_cfg_bits |
 539                                 intel_dsi->video_mode_format);
 540 }
 541
 542 static enum drm_connector_status
 543 intel_dsi_detect(struct drm_connector *connector, bool force)
 544 {
 545         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 546         struct intel_encoder *intel_encoder = &intel_dsi->base;
 547         enum intel_display_power_domain power_domain;
 548         enum drm_connector_status connector_status;
 549         struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
 550
 551         DRM_DEBUG_KMS("\n");
 552         power_domain = intel_display_port_power_domain(intel_encoder);
 553
 554         intel_display_power_get(dev_priv, power_domain);
 555         connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 556         intel_display_power_put(dev_priv, power_domain);
 557
 558         return connector_status;
 559 }
 560
 561 static int intel_dsi_get_modes(struct drm_connector *connector)
 562 {
 563         struct intel_connector *intel_connector = to_intel_connector(connector);
 564         struct drm_display_mode *mode;
 565
 566         DRM_DEBUG_KMS("\n");
 567
 568         if (!intel_connector->panel.fixed_mode) {
 569                 DRM_DEBUG_KMS("no fixed mode\n");
 570                 return 0;
 571         }
 572
 573         mode = drm_mode_duplicate(connector->dev,
 574                                   intel_connector->panel.fixed_mode);
 575         if (!mode) {
 576                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 577                 return 0;
 578         }
 579
 580         drm_mode_probed_add(connector, mode);
 581         return 1;
 582 }
 583
 584 static void intel_dsi_destroy(struct drm_connector *connector)
 585 {
 586         struct intel_connector *intel_connector = to_intel_connector(connector);
 587
 588         DRM_DEBUG_KMS("\n");
 589         intel_panel_fini(&intel_connector->panel);
 590         drm_connector_cleanup(connector);
 591         kfree(connector);
 592 }
 593
 594 static const struct drm_encoder_funcs intel_dsi_funcs = {
 595         .destroy = intel_encoder_destroy,
 596 };
 597
 598 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 599         .get_modes = intel_dsi_get_modes,
 600         .mode_valid = intel_dsi_mode_valid,
 601         .best_encoder = intel_best_encoder,
 602 };
 603
 604 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 605         .dpms = intel_connector_dpms,
 606         .detect = intel_dsi_detect,
 607         .destroy = intel_dsi_destroy,
 608         .fill_modes = drm_helper_probe_single_connector_modes,
 609 };
 610
 611 bool intel_dsi_init(struct drm_device *dev)
 612 {
 613         struct intel_dsi *intel_dsi;
 614         struct intel_encoder *intel_encoder;
 615         struct drm_encoder *encoder;
 616         struct intel_connector *intel_connector;
 617         struct drm_connector *connector;
 618         struct drm_display_mode *fixed_mode = NULL;
 619         const struct intel_dsi_device *dsi;
 620         unsigned int i;
 621
 622         DRM_DEBUG_KMS("\n");
 623
 624         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 625         if (!intel_dsi)
 626                 return false;
 627
 628         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 629         if (!intel_connector) {
 630                 kfree(intel_dsi);
 631                 return false;
 632         }
 633
 634         intel_encoder = &intel_dsi->base;
 635         encoder = &intel_encoder->base;
 636         intel_dsi->attached_connector = intel_connector;
 637
 638         connector = &intel_connector->base;
 639
 640         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 641
 642         /* XXX: very likely not all of these are needed */
 643         intel_encoder->hot_plug = intel_dsi_hot_plug;
 644         intel_encoder->compute_config = intel_dsi_compute_config;
 645         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 646         intel_encoder->pre_enable = intel_dsi_pre_enable;
 647         intel_encoder->enable = intel_dsi_enable_nop;
 648         intel_encoder->mode_set = intel_dsi_mode_set;
 649         intel_encoder->disable = intel_dsi_disable;
 650         intel_encoder->post_disable = intel_dsi_post_disable;
 651         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 652         intel_encoder->get_config = intel_dsi_get_config;
 653
 654         intel_connector->get_hw_state = intel_connector_get_hw_state;
 655         intel_connector->unregister = intel_connector_unregister;
 656
 657         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 658                 dsi = &intel_dsi_devices[i];
 659                 intel_dsi->dev = *dsi;
 660
 661                 if (dsi->dev_ops->init(&intel_dsi->dev))
 662                         break;
 663         }
 664
 665         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 666                 DRM_DEBUG_KMS("no device found\n");
 667                 goto err;
 668         }
 669
 670         intel_encoder->type = INTEL_OUTPUT_DSI;
 671         intel_encoder->crtc_mask = (1 << 0); /* XXX */
 672
 673         intel_encoder->cloneable = 0;
 674         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 675                            DRM_MODE_CONNECTOR_DSI);
 676
 677         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 678
 679         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 680         connector->interlace_allowed = false;
 681         connector->doublescan_allowed = false;
 682
 683         intel_connector_attach_encoder(intel_connector, intel_encoder);
 684
 685         drm_sysfs_connector_add(connector);
 686
 687         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 688         if (!fixed_mode) {
 689                 DRM_DEBUG_KMS("no fixed mode\n");
 690                 goto err;
 691         }
 692
 693         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 694         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 695
 696         return true;
 697
 698 err:
 699         drm_encoder_cleanup(&intel_encoder->base);
 700         kfree(intel_dsi);
 701         kfree(intel_connector);
 702
 703         return false;
 704 }