drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38         {
  39                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  40                 .name = "vbt-generic-dsi-vid-mode-display",
  41                 .dev_ops = &vbt_generic_dsi_display_ops,
  42         },
  43 };
  44
  45 static void band_gap_reset(struct drm_i915_private *dev_priv)
  46 {
  47         mutex_lock(&dev_priv->dpio_lock);
  48
  49         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  50         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  51         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  52         udelay(150);
  53         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  54         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  55
  56         mutex_unlock(&dev_priv->dpio_lock);
  57 }
  58
  59 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  60 {
  61         return container_of(intel_attached_encoder(connector),
  62                             struct intel_dsi, base);
  63 }
  64
  65 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  66 {
  67         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
  68 }
  69
  70 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  71 {
  72         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
  73 }
  74
  75 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  76 {
  77         DRM_DEBUG_KMS("\n");
  78 }
  79
  80 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  81                                      struct intel_crtc_config *config)
  82 {
  83         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  84                                                    base);
  85         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  86         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  87         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  88         struct drm_display_mode *mode = &config->requested_mode;
  89
  90         DRM_DEBUG_KMS("\n");
  91
  92         if (fixed_mode)
  93                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  94
  95         /* DSI uses short packets for sync events, so clear mode flags for DSI */
  96         adjusted_mode->flags = 0;
  97
  98         if (intel_dsi->dev.dev_ops->mode_fixup)
  99                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
 100                                                           mode, adjusted_mode);
 101
 102         return true;
 103 }
 104
 105 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 106 {
 107         struct drm_device *dev = encoder->base.dev;
 108         struct drm_i915_private *dev_priv = dev->dev_private;
 109         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 110         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 111         enum port port;
 112         u32 temp;
 113
 114         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 115                 temp = I915_READ(VLV_CHICKEN_3);
 116                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 117                                         intel_dsi->pixel_overlap <<
 118                                         PIXEL_OVERLAP_CNT_SHIFT;
 119                 I915_WRITE(VLV_CHICKEN_3, temp);
 120         }
 121
 122         for_each_dsi_port(port, intel_dsi->ports) {
 123                 temp = I915_READ(MIPI_PORT_CTRL(port));
 124                 temp &= ~LANE_CONFIGURATION_MASK;
 125                 temp &= ~DUAL_LINK_MODE_MASK;
 126
 127                 if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
 128                         temp |= (intel_dsi->dual_link - 1)
 129                                                 << DUAL_LINK_MODE_SHIFT;
 130                         temp |= intel_crtc->pipe ?
 131                                         LANE_CONFIGURATION_DUAL_LINK_B :
 132                                         LANE_CONFIGURATION_DUAL_LINK_A;
 133                 }
 134                 /* assert ip_tg_enable signal */
 135                 I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
 136                 POSTING_READ(MIPI_PORT_CTRL(port));
 137         }
 138 }
 139
 140 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 141 {
 142         struct drm_device *dev = encoder->base.dev;
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 145         enum port port;
 146         u32 temp;
 147
 148         for_each_dsi_port(port, intel_dsi->ports) {
 149                 /* de-assert ip_tg_enable signal */
 150                 temp = I915_READ(MIPI_PORT_CTRL(port));
 151                 I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
 152                 POSTING_READ(MIPI_PORT_CTRL(port));
 153         }
 154 }
 155
 156 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 157 {
 158         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 159         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 160         enum port port;
 161         u32 val;
 162
 163         DRM_DEBUG_KMS("\n");
 164
 165         mutex_lock(&dev_priv->dpio_lock);
 166         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 167          * needed everytime after power gate */
 168         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 169         mutex_unlock(&dev_priv->dpio_lock);
 170
 171         /* bandgap reset is needed after everytime we do power gate */
 172         band_gap_reset(dev_priv);
 173
 174         for_each_dsi_port(port, intel_dsi->ports) {
 175
 176                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 177                 usleep_range(2500, 3000);
 178
 179                 val = I915_READ(MIPI_PORT_CTRL(port));
 180
 181                 /* Enable MIPI PHY transparent latch
 182                  * Common bit for both MIPI Port A & MIPI Port C
 183                  * No similar bit in MIPI Port C reg
 184                  */
 185                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 186                 usleep_range(1000, 1500);
 187
 188                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 189                 usleep_range(2500, 3000);
 190
 191                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 192                 usleep_range(2500, 3000);
 193         }
 194 }
 195
 196 static void intel_dsi_enable(struct intel_encoder *encoder)
 197 {
 198         struct drm_device *dev = encoder->base.dev;
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 201         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 202         enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 203
 204         DRM_DEBUG_KMS("\n");
 205
 206         if (is_cmd_mode(intel_dsi))
 207                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 208         else {
 209                 msleep(20); /* XXX */
 210                 dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
 211                 msleep(100);
 212
 213                 if (intel_dsi->dev.dev_ops->enable)
 214                         intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 215
 216                 wait_for_dsi_fifo_empty(intel_dsi);
 217
 218                 intel_dsi_port_enable(encoder);
 219         }
 220 }
 221
 222 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 223 {
 224         struct drm_device *dev = encoder->base.dev;
 225         struct drm_i915_private *dev_priv = dev->dev_private;
 226         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 227         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 228         enum pipe pipe = intel_crtc->pipe;
 229         u32 tmp;
 230
 231         DRM_DEBUG_KMS("\n");
 232
 233         /* Disable DPOunit clock gating, can stall pipe
 234          * and we need DPLL REFA always enabled */
 235         tmp = I915_READ(DPLL(pipe));
 236         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 237         I915_WRITE(DPLL(pipe), tmp);
 238
 239         /* update the hw state for DPLL */
 240         intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
 241                 DPLL_REFA_CLK_ENABLE_VLV;
 242
 243         tmp = I915_READ(DSPCLK_GATE_D);
 244         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 245         I915_WRITE(DSPCLK_GATE_D, tmp);
 246
 247         /* put device in ready state */
 248         intel_dsi_device_ready(encoder);
 249
 250         msleep(intel_dsi->panel_on_delay);
 251
 252         if (intel_dsi->dev.dev_ops->panel_reset)
 253                 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
 254
 255         if (intel_dsi->dev.dev_ops->send_otp_cmds)
 256                 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 257
 258         wait_for_dsi_fifo_empty(intel_dsi);
 259
 260         /* Enable port in pre-enable phase itself because as per hw team
 261          * recommendation, port should be enabled befor plane & pipe */
 262         intel_dsi_enable(encoder);
 263 }
 264
 265 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 266 {
 267         DRM_DEBUG_KMS("\n");
 268
 269         /* for DSI port enable has to be done before pipe
 270          * and plane enable, so port enable is done in
 271          * pre_enable phase itself unlike other encoders
 272          */
 273 }
 274
 275 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 276 {
 277         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 278
 279         DRM_DEBUG_KMS("\n");
 280
 281         if (is_vid_mode(intel_dsi)) {
 282                 /* Send Shutdown command to the panel in LP mode */
 283                 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
 284                 msleep(10);
 285         }
 286 }
 287
 288 static void intel_dsi_disable(struct intel_encoder *encoder)
 289 {
 290         struct drm_device *dev = encoder->base.dev;
 291         struct drm_i915_private *dev_priv = dev->dev_private;
 292         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 293         enum port port;
 294         u32 temp;
 295
 296         DRM_DEBUG_KMS("\n");
 297
 298         if (is_vid_mode(intel_dsi)) {
 299                 wait_for_dsi_fifo_empty(intel_dsi);
 300
 301                 intel_dsi_port_disable(encoder);
 302                 msleep(2);
 303         }
 304
 305         for_each_dsi_port(port, intel_dsi->ports) {
 306                 /* Panel commands can be sent when clock is in LP11 */
 307                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 308
 309                 temp = I915_READ(MIPI_CTRL(port));
 310                 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 311                 I915_WRITE(MIPI_CTRL(port), temp |
 312                            intel_dsi->escape_clk_div <<
 313                            ESCAPE_CLOCK_DIVIDER_SHIFT);
 314
 315                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 316
 317                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 318                 temp &= ~VID_MODE_FORMAT_MASK;
 319                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 320
 321                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 322         }
 323         /* if disable packets are sent before sending shutdown packet then in
 324          * some next enable sequence send turn on packet error is observed */
 325         if (intel_dsi->dev.dev_ops->disable)
 326                 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 327
 328         wait_for_dsi_fifo_empty(intel_dsi);
 329 }
 330
 331 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 332 {
 333         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 334         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 335         enum port port;
 336         u32 val;
 337
 338         DRM_DEBUG_KMS("\n");
 339         for_each_dsi_port(port, intel_dsi->ports) {
 340
 341                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 342                                                         ULPS_STATE_ENTER);
 343                 usleep_range(2000, 2500);
 344
 345                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 346                                                         ULPS_STATE_EXIT);
 347                 usleep_range(2000, 2500);
 348
 349                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 350                                                         ULPS_STATE_ENTER);
 351                 usleep_range(2000, 2500);
 352
 353                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 354                  * only. MIPI Port C has no similar bit for checking
 355                  */
 356                 if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
 357                                                         == 0x00000), 30))
 358                         DRM_ERROR("DSI LP not going Low\n");
 359
 360                 val = I915_READ(MIPI_PORT_CTRL(port));
 361                 /* Disable MIPI PHY transparent latch
 362                  * Common bit for both MIPI Port A & MIPI Port C
 363                  */
 364                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
 365                 usleep_range(1000, 1500);
 366
 367                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 368                 usleep_range(2000, 2500);
 369         }
 370
 371         vlv_disable_dsi_pll(encoder);
 372 }
 373
 374 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 375 {
 376         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 377         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 378         u32 val;
 379
 380         DRM_DEBUG_KMS("\n");
 381
 382         intel_dsi_disable(encoder);
 383
 384         intel_dsi_clear_device_ready(encoder);
 385
 386         val = I915_READ(DSPCLK_GATE_D);
 387         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 388         I915_WRITE(DSPCLK_GATE_D, val);
 389
 390         if (intel_dsi->dev.dev_ops->disable_panel_power)
 391                 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
 392
 393         msleep(intel_dsi->panel_off_delay);
 394         msleep(intel_dsi->panel_pwr_cycle_delay);
 395 }
 396
 397 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 398                                    enum pipe *pipe)
 399 {
 400         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 401         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 402         struct drm_device *dev = encoder->base.dev;
 403         enum intel_display_power_domain power_domain;
 404         u32 dpi_enabled, func;
 405         enum port port;
 406
 407         DRM_DEBUG_KMS("\n");
 408
 409         power_domain = intel_display_port_power_domain(encoder);
 410         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 411                 return false;
 412
 413         /* XXX: this only works for one DSI output */
 414         for_each_dsi_port(port, intel_dsi->ports) {
 415                 func = I915_READ(MIPI_DSI_FUNC_PRG(port));
 416                 dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
 417                                                         DPI_ENABLE;
 418
 419                 /* Due to some hardware limitations on BYT, MIPI Port C DPI
 420                  * Enable bit does not get set. To check whether DSI Port C
 421                  * was enabled in BIOS, check the Pipe B enable bit
 422                  */
 423                 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 424                     (port == PORT_C))
 425                         dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 426                                                         PIPECONF_ENABLE;
 427
 428                 if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 429                         if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
 430                                 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 431                                 return true;
 432                         }
 433                 }
 434         }
 435
 436         return false;
 437 }
 438
 439 static void intel_dsi_get_config(struct intel_encoder *encoder,
 440                                  struct intel_crtc_config *pipe_config)
 441 {
 442         u32 pclk;
 443         DRM_DEBUG_KMS("\n");
 444
 445         /*
 446          * DPLL_MD is not used in case of DSI, reading will get some default value
 447          * set dpll_md = 0
 448          */
 449         pipe_config->dpll_hw_state.dpll_md = 0;
 450
 451         pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 452         if (!pclk)
 453                 return;
 454
 455         pipe_config->adjusted_mode.crtc_clock = pclk;
 456         pipe_config->port_clock = pclk;
 457 }
 458
 459 static enum drm_mode_status
 460 intel_dsi_mode_valid(struct drm_connector *connector,
 461                      struct drm_display_mode *mode)
 462 {
 463         struct intel_connector *intel_connector = to_intel_connector(connector);
 464         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 465         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 466
 467         DRM_DEBUG_KMS("\n");
 468
 469         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 470                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 471                 return MODE_NO_DBLESCAN;
 472         }
 473
 474         if (fixed_mode) {
 475                 if (mode->hdisplay > fixed_mode->hdisplay)
 476                         return MODE_PANEL;
 477                 if (mode->vdisplay > fixed_mode->vdisplay)
 478                         return MODE_PANEL;
 479         }
 480
 481         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 482 }
 483
 484 /* return txclkesc cycles in terms of divider and duration in us */
 485 static u16 txclkesc(u32 divider, unsigned int us)
 486 {
 487         switch (divider) {
 488         case ESCAPE_CLOCK_DIVIDER_1:
 489         default:
 490                 return 20 * us;
 491         case ESCAPE_CLOCK_DIVIDER_2:
 492                 return 10 * us;
 493         case ESCAPE_CLOCK_DIVIDER_4:
 494                 return 5 * us;
 495         }
 496 }
 497
 498 /* return pixels in terms of txbyteclkhs */
 499 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
 500                        u16 burst_mode_ratio)
 501 {
 502         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
 503                                          8 * 100), lane_count);
 504 }
 505
 506 static void set_dsi_timings(struct drm_encoder *encoder,
 507                             const struct drm_display_mode *mode)
 508 {
 509         struct drm_device *dev = encoder->dev;
 510         struct drm_i915_private *dev_priv = dev->dev_private;
 511         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 512         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 513         enum port port;
 514         unsigned int bpp = intel_crtc->config.pipe_bpp;
 515         unsigned int lane_count = intel_dsi->lane_count;
 516
 517         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 518
 519         hactive = mode->hdisplay;
 520         hfp = mode->hsync_start - mode->hdisplay;
 521         hsync = mode->hsync_end - mode->hsync_start;
 522         hbp = mode->htotal - mode->hsync_end;
 523
 524         if (intel_dsi->dual_link) {
 525                 hactive /= 2;
 526                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 527                         hactive += intel_dsi->pixel_overlap;
 528                 hfp /= 2;
 529                 hsync /= 2;
 530                 hbp /= 2;
 531         }
 532
 533         vfp = mode->vsync_start - mode->vdisplay;
 534         vsync = mode->vsync_end - mode->vsync_start;
 535         vbp = mode->vtotal - mode->vsync_end;
 536
 537         /* horizontal values are in terms of high speed byte clock */
 538         hactive = txbyteclkhs(hactive, bpp, lane_count,
 539                               intel_dsi->burst_mode_ratio);
 540         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 541         hsync = txbyteclkhs(hsync, bpp, lane_count,
 542                             intel_dsi->burst_mode_ratio);
 543         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 544
 545         for_each_dsi_port(port, intel_dsi->ports) {
 546                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
 547                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
 548
 549                 /* meaningful for video mode non-burst sync pulse mode only,
 550                  * can be zero for non-burst sync events and burst modes */
 551                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
 552                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
 553
 554                 /* vertical values are in terms of lines */
 555                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
 556                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
 557                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
 558         }
 559 }
 560
 561 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 562 {
 563         struct drm_encoder *encoder = &intel_encoder->base;
 564         struct drm_device *dev = encoder->dev;
 565         struct drm_i915_private *dev_priv = dev->dev_private;
 566         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 567         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 568         struct drm_display_mode *adjusted_mode =
 569                 &intel_crtc->config.adjusted_mode;
 570         enum port port;
 571         unsigned int bpp = intel_crtc->config.pipe_bpp;
 572         u32 val, tmp;
 573         u16 mode_hdisplay;
 574
 575         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 576
 577         mode_hdisplay = adjusted_mode->hdisplay;
 578
 579         if (intel_dsi->dual_link) {
 580                 mode_hdisplay /= 2;
 581                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 582                         mode_hdisplay += intel_dsi->pixel_overlap;
 583         }
 584
 585         for_each_dsi_port(port, intel_dsi->ports) {
 586                 /* escape clock divider, 20MHz, shared for A and C.
 587                  * device ready must be off when doing this! txclkesc? */
 588                 tmp = I915_READ(MIPI_CTRL(PORT_A));
 589                 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 590                 I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
 591
 592                 /* read request priority is per pipe */
 593                 tmp = I915_READ(MIPI_CTRL(port));
 594                 tmp &= ~READ_REQUEST_PRIORITY_MASK;
 595                 I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
 596
 597                 /* XXX: why here, why like this? handling in irq handler?! */
 598                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
 599                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
 600
 601                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
 602
 603                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
 604                         adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 605                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 606         }
 607
 608         set_dsi_timings(encoder, adjusted_mode);
 609
 610         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 611         if (is_cmd_mode(intel_dsi)) {
 612                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 613                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 614         } else {
 615                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 616
 617                 /* XXX: cross-check bpp vs. pixel format? */
 618                 val |= intel_dsi->pixel_format;
 619         }
 620
 621         tmp = 0;
 622         if (intel_dsi->eotp_pkt == 0)
 623                 tmp |= EOT_DISABLE;
 624         if (intel_dsi->clock_stop)
 625                 tmp |= CLOCKSTOP;
 626
 627         for_each_dsi_port(port, intel_dsi->ports) {
 628                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 629
 630                 /* timeouts for recovery. one frame IIUC. if counter expires,
 631                  * EOT and stop state. */
 632
 633                 /*
 634                  * In burst mode, value greater than one DPI line Time in byte
 635                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
 636                  * said value is recommended.
 637                  *
 638                  * In non-burst mode, Value greater than one DPI frame time in
 639                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 640                  * said value is recommended.
 641                  *
 642                  * In DBI only mode, value greater than one DBI frame time in
 643                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 644                  * said value is recommended.
 645                  */
 646
 647                 if (is_vid_mode(intel_dsi) &&
 648                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 649                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 650                                 txbyteclkhs(adjusted_mode->htotal, bpp,
 651                                         intel_dsi->lane_count,
 652                                         intel_dsi->burst_mode_ratio) + 1);
 653                 } else {
 654                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 655                                 txbyteclkhs(adjusted_mode->vtotal *
 656                                         adjusted_mode->htotal,
 657                                         bpp, intel_dsi->lane_count,
 658                                         intel_dsi->burst_mode_ratio) + 1);
 659                 }
 660                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
 661                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
 662                                                 intel_dsi->turn_arnd_val);
 663                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
 664                                                 intel_dsi->rst_timer_val);
 665
 666                 /* dphy stuff */
 667
 668                 /* in terms of low power clock */
 669                 I915_WRITE(MIPI_INIT_COUNT(port),
 670                                 txclkesc(intel_dsi->escape_clk_div, 100));
 671
 672
 673                 /* recovery disables */
 674                 I915_WRITE(MIPI_EOT_DISABLE(port), val);
 675
 676                 /* in terms of low power clock */
 677                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
 678
 679                 /* in terms of txbyteclkhs. actual high to low switch +
 680                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 681                  *
 682                  * XXX: write MIPI_STOP_STATE_STALL?
 683                  */
 684                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
 685                                                 intel_dsi->hs_to_lp_count);
 686
 687                 /* XXX: low power clock equivalence in terms of byte clock.
 688                  * the number of byte clocks occupied in one low power clock.
 689                  * based on txbyteclkhs and txclkesc.
 690                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
 691                  * ) / 105.???
 692                  */
 693                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
 694
 695                 /* the bw essential for transmitting 16 long packets containing
 696                  * 252 bytes meant for dcs write memory command is programmed in
 697                  * this register in terms of byte clocks. based on dsi transfer
 698                  * rate and the number of lanes configured the time taken to
 699                  * transmit 16 long packets in a dsi stream varies. */
 700                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
 701
 702                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
 703                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 704                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 705
 706                 if (is_vid_mode(intel_dsi))
 707                         /* Some panels might have resolution which is not a
 708                          * multiple of 64 like 1366 x 768. Enable RANDOM
 709                          * resolution support for such panels by default */
 710                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
 711                                 intel_dsi->video_frmt_cfg_bits |
 712                                 intel_dsi->video_mode_format |
 713                                 IP_TG_CONFIG |
 714                                 RANDOM_DPI_DISPLAY_RESOLUTION);
 715         }
 716 }
 717
 718 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 719 {
 720         DRM_DEBUG_KMS("\n");
 721
 722         intel_dsi_prepare(encoder);
 723
 724         vlv_enable_dsi_pll(encoder);
 725 }
 726
 727 static enum drm_connector_status
 728 intel_dsi_detect(struct drm_connector *connector, bool force)
 729 {
 730         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 731         struct intel_encoder *intel_encoder = &intel_dsi->base;
 732         enum intel_display_power_domain power_domain;
 733         enum drm_connector_status connector_status;
 734         struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
 735
 736         DRM_DEBUG_KMS("\n");
 737         power_domain = intel_display_port_power_domain(intel_encoder);
 738
 739         intel_display_power_get(dev_priv, power_domain);
 740         connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 741         intel_display_power_put(dev_priv, power_domain);
 742
 743         return connector_status;
 744 }
 745
 746 static int intel_dsi_get_modes(struct drm_connector *connector)
 747 {
 748         struct intel_connector *intel_connector = to_intel_connector(connector);
 749         struct drm_display_mode *mode;
 750
 751         DRM_DEBUG_KMS("\n");
 752
 753         if (!intel_connector->panel.fixed_mode) {
 754                 DRM_DEBUG_KMS("no fixed mode\n");
 755                 return 0;
 756         }
 757
 758         mode = drm_mode_duplicate(connector->dev,
 759                                   intel_connector->panel.fixed_mode);
 760         if (!mode) {
 761                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 762                 return 0;
 763         }
 764
 765         drm_mode_probed_add(connector, mode);
 766         return 1;
 767 }
 768
 769 static void intel_dsi_destroy(struct drm_connector *connector)
 770 {
 771         struct intel_connector *intel_connector = to_intel_connector(connector);
 772
 773         DRM_DEBUG_KMS("\n");
 774         intel_panel_fini(&intel_connector->panel);
 775         drm_connector_cleanup(connector);
 776         kfree(connector);
 777 }
 778
 779 static const struct drm_encoder_funcs intel_dsi_funcs = {
 780         .destroy = intel_encoder_destroy,
 781 };
 782
 783 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 784         .get_modes = intel_dsi_get_modes,
 785         .mode_valid = intel_dsi_mode_valid,
 786         .best_encoder = intel_best_encoder,
 787 };
 788
 789 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 790         .dpms = intel_connector_dpms,
 791         .detect = intel_dsi_detect,
 792         .destroy = intel_dsi_destroy,
 793         .fill_modes = drm_helper_probe_single_connector_modes,
 794 };
 795
 796 void intel_dsi_init(struct drm_device *dev)
 797 {
 798         struct intel_dsi *intel_dsi;
 799         struct intel_encoder *intel_encoder;
 800         struct drm_encoder *encoder;
 801         struct intel_connector *intel_connector;
 802         struct drm_connector *connector;
 803         struct drm_display_mode *fixed_mode = NULL;
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         const struct intel_dsi_device *dsi;
 806         unsigned int i;
 807
 808         DRM_DEBUG_KMS("\n");
 809
 810         /* There is no detection method for MIPI so rely on VBT */
 811         if (!dev_priv->vbt.has_mipi)
 812                 return;
 813
 814         if (IS_VALLEYVIEW(dev)) {
 815                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
 816         } else {
 817                 DRM_ERROR("Unsupported Mipi device to reg base");
 818                 return;
 819         }
 820
 821         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 822         if (!intel_dsi)
 823                 return;
 824
 825         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 826         if (!intel_connector) {
 827                 kfree(intel_dsi);
 828                 return;
 829         }
 830
 831         intel_encoder = &intel_dsi->base;
 832         encoder = &intel_encoder->base;
 833         intel_dsi->attached_connector = intel_connector;
 834
 835         connector = &intel_connector->base;
 836
 837         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 838
 839         /* XXX: very likely not all of these are needed */
 840         intel_encoder->hot_plug = intel_dsi_hot_plug;
 841         intel_encoder->compute_config = intel_dsi_compute_config;
 842         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 843         intel_encoder->pre_enable = intel_dsi_pre_enable;
 844         intel_encoder->enable = intel_dsi_enable_nop;
 845         intel_encoder->disable = intel_dsi_pre_disable;
 846         intel_encoder->post_disable = intel_dsi_post_disable;
 847         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 848         intel_encoder->get_config = intel_dsi_get_config;
 849
 850         intel_connector->get_hw_state = intel_connector_get_hw_state;
 851         intel_connector->unregister = intel_connector_unregister;
 852
 853         /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
 854         if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
 855                 intel_encoder->crtc_mask = (1 << PIPE_A);
 856                 intel_dsi->ports = (1 << PORT_A);
 857         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
 858                 intel_encoder->crtc_mask = (1 << PIPE_B);
 859                 intel_dsi->ports = (1 << PORT_C);
 860         }
 861
 862         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 863                 dsi = &intel_dsi_devices[i];
 864                 intel_dsi->dev = *dsi;
 865
 866                 if (dsi->dev_ops->init(&intel_dsi->dev))
 867                         break;
 868         }
 869
 870         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 871                 DRM_DEBUG_KMS("no device found\n");
 872                 goto err;
 873         }
 874
 875         intel_encoder->type = INTEL_OUTPUT_DSI;
 876         intel_encoder->cloneable = 0;
 877         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 878                            DRM_MODE_CONNECTOR_DSI);
 879
 880         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 881
 882         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 883         connector->interlace_allowed = false;
 884         connector->doublescan_allowed = false;
 885
 886         intel_connector_attach_encoder(intel_connector, intel_encoder);
 887
 888         drm_connector_register(connector);
 889
 890         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 891         if (!fixed_mode) {
 892                 DRM_DEBUG_KMS("no fixed mode\n");
 893                 goto err;
 894         }
 895
 896         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 897         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 898
 899         return;
 900
 901 err:
 902         drm_encoder_cleanup(&intel_encoder->base);
 903         kfree(intel_dsi);
 904         kfree(intel_connector);
 905 }