drivers/gpu/drm/i915/intel_dsi_panel_vbt.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  24  *
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <linux/slab.h>
  33 #include <video/mipi_display.h>
  34 #include <asm/intel-mid.h>
  35 #include <video/mipi_display.h>
  36 #include "i915_drv.h"
  37 #include "intel_drv.h"
  38 #include "intel_dsi.h"
  39
  40 struct vbt_panel {
  41         struct drm_panel panel;
  42         struct intel_dsi *intel_dsi;
  43 };
  44
  45 static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
  46 {
  47         return container_of(panel, struct vbt_panel, panel);
  48 }
  49
  50 #define MIPI_TRANSFER_MODE_SHIFT        0
  51 #define MIPI_VIRTUAL_CHANNEL_SHIFT      1
  52 #define MIPI_PORT_SHIFT                 3
  53
  54 #define PREPARE_CNT_MAX         0x3F
  55 #define EXIT_ZERO_CNT_MAX       0x3F
  56 #define CLK_ZERO_CNT_MAX        0xFF
  57 #define TRAIL_CNT_MAX           0x1F
  58
  59 #define NS_KHZ_RATIO 1000000
  60
  61 #define GPI0_NC_0_HV_DDI0_HPD           0x4130
  62 #define GPIO_NC_0_HV_DDI0_PAD           0x4138
  63 #define GPIO_NC_1_HV_DDI0_DDC_SDA       0x4120
  64 #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
  65 #define GPIO_NC_2_HV_DDI0_DDC_SCL       0x4110
  66 #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
  67 #define GPIO_NC_3_PANEL0_VDDEN          0x4140
  68 #define GPIO_NC_3_PANEL0_VDDEN_PAD      0x4148
  69 #define GPIO_NC_4_PANEL0_BLKEN          0x4150
  70 #define GPIO_NC_4_PANEL0_BLKEN_PAD      0x4158
  71 #define GPIO_NC_5_PANEL0_BLKCTL         0x4160
  72 #define GPIO_NC_5_PANEL0_BLKCTL_PAD     0x4168
  73 #define GPIO_NC_6_PCONF0                0x4180
  74 #define GPIO_NC_6_PAD                   0x4188
  75 #define GPIO_NC_7_PCONF0                0x4190
  76 #define GPIO_NC_7_PAD                   0x4198
  77 #define GPIO_NC_8_PCONF0                0x4170
  78 #define GPIO_NC_8_PAD                   0x4178
  79 #define GPIO_NC_9_PCONF0                0x4100
  80 #define GPIO_NC_9_PAD                   0x4108
  81 #define GPIO_NC_10_PCONF0               0x40E0
  82 #define GPIO_NC_10_PAD                  0x40E8
  83 #define GPIO_NC_11_PCONF0               0x40F0
  84 #define GPIO_NC_11_PAD                  0x40F8
  85
  86 struct gpio_table {
  87         u16 function_reg;
  88         u16 pad_reg;
  89         u8 init;
  90 };
  91
  92 static struct gpio_table gtable[] = {
  93         { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
  94         { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
  95         { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
  96         { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
  97         { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
  98         { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
  99         { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
 100         { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
 101         { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
 102         { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
 103         { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
 104         { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
 105 };
 106
 107 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 108 {
 109         return port ? PORT_C : PORT_A;
 110 }
 111
 112 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 113                                        const u8 *data)
 114 {
 115         struct mipi_dsi_device *dsi_device;
 116         u8 type, flags, seq_port;
 117         u16 len;
 118         enum port port;
 119
 120         flags = *data++;
 121         type = *data++;
 122
 123         len = *((u16 *) data);
 124         data += 2;
 125
 126         seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
 127
 128         /* For DSI single link on Port A & C, the seq_port value which is
 129          * parsed from Sequence Block#53 of VBT has been set to 0
 130          * Now, read/write of packets for the DSI single link on Port A and
 131          * Port C will based on the DVO port from VBT block 2.
 132          */
 133         if (intel_dsi->ports == (1 << PORT_C))
 134                 port = PORT_C;
 135         else
 136                 port = intel_dsi_seq_port_to_port(seq_port);
 137
 138         dsi_device = intel_dsi->dsi_hosts[port]->device;
 139         if (!dsi_device) {
 140                 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
 141                 goto out;
 142         }
 143
 144         if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
 145                 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
 146         else
 147                 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
 148
 149         dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
 150
 151         switch (type) {
 152         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 153                 mipi_dsi_generic_write(dsi_device, NULL, 0);
 154                 break;
 155         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 156                 mipi_dsi_generic_write(dsi_device, data, 1);
 157                 break;
 158         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 159                 mipi_dsi_generic_write(dsi_device, data, 2);
 160                 break;
 161         case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 162         case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
 163         case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
 164                 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
 165                 break;
 166         case MIPI_DSI_GENERIC_LONG_WRITE:
 167                 mipi_dsi_generic_write(dsi_device, data, len);
 168                 break;
 169         case MIPI_DSI_DCS_SHORT_WRITE:
 170                 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
 171                 break;
 172         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 173                 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
 174                 break;
 175         case MIPI_DSI_DCS_READ:
 176                 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
 177                 break;
 178         case MIPI_DSI_DCS_LONG_WRITE:
 179                 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
 180                 break;
 181         }
 182
 183 out:
 184         data += len;
 185
 186         return data;
 187 }
 188
 189 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 190 {
 191         u32 delay = *((const u32 *) data);
 192
 193         usleep_range(delay, delay + 10);
 194         data += 4;
 195
 196         return data;
 197 }
 198
 199 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 200 {
 201         u8 gpio, action;
 202         u16 function, pad;
 203         u32 val;
 204         struct drm_device *dev = intel_dsi->base.base.dev;
 205         struct drm_i915_private *dev_priv = dev->dev_private;
 206
 207         gpio = *data++;
 208
 209         /* pull up/down */
 210         action = *data++;
 211
 212         function = gtable[gpio].function_reg;
 213         pad = gtable[gpio].pad_reg;
 214
 215         mutex_lock(&dev_priv->sb_lock);
 216         if (!gtable[gpio].init) {
 217                 /* program the function */
 218                 /* FIXME: remove constant below */
 219                 vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
 220                 gtable[gpio].init = 1;
 221         }
 222
 223         val = 0x4 | action;
 224
 225         /* pull up/down */
 226         vlv_gpio_nc_write(dev_priv, pad, val);
 227         mutex_unlock(&dev_priv->sb_lock);
 228
 229         return data;
 230 }
 231
 232 static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
 233 {
 234         return data + *(data + 6) + 7;
 235 }
 236
 237 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
 238                                         const u8 *data);
 239 static const fn_mipi_elem_exec exec_elem[] = {
 240         [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
 241         [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
 242         [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
 243         [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
 244 };
 245
 246 /*
 247  * MIPI Sequence from VBT #53 parsing logic
 248  * We have already separated each seqence during bios parsing
 249  * Following is generic execution function for any sequence
 250  */
 251
 252 static const char * const seq_name[] = {
 253         [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
 254         [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
 255         [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
 256         [MIPI_SEQ_DISPLAY_OFF]  = "MIPI_SEQ_DISPLAY_OFF",
 257         [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
 258         [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
 259         [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
 260         [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
 261         [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
 262         [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
 263         [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
 264 };
 265
 266 static const char *sequence_name(enum mipi_seq seq_id)
 267 {
 268         if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
 269                 return seq_name[seq_id];
 270         else
 271                 return "(unknown)";
 272 }
 273
 274 static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
 275 {
 276         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 277         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 278         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 279         const u8 *data;
 280         fn_mipi_elem_exec mipi_elem_exec;
 281
 282         if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
 283                 return;
 284
 285         data = dev_priv->vbt.dsi.sequence[seq_id];
 286         if (!data) {
 287                 DRM_DEBUG_KMS("MIPI sequence %d - %s not available\n",
 288                               seq_id, sequence_name(seq_id));
 289                 return;
 290         }
 291
 292         WARN_ON(*data != seq_id);
 293
 294         DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
 295                       seq_id, sequence_name(seq_id));
 296
 297         /* Skip Sequence Byte. */
 298         data++;
 299
 300         /* Skip Size of Sequence. */
 301         if (dev_priv->vbt.dsi.seq_version >= 3)
 302                 data += 4;
 303
 304         while (1) {
 305                 u8 operation_byte = *data++;
 306                 u8 operation_size = 0;
 307
 308                 if (operation_byte == MIPI_SEQ_ELEM_END)
 309                         break;
 310
 311                 if (operation_byte < ARRAY_SIZE(exec_elem))
 312                         mipi_elem_exec = exec_elem[operation_byte];
 313                 else
 314                         mipi_elem_exec = NULL;
 315
 316                 /* Size of Operation. */
 317                 if (dev_priv->vbt.dsi.seq_version >= 3)
 318                         operation_size = *data++;
 319
 320                 if (mipi_elem_exec) {
 321                         data = mipi_elem_exec(intel_dsi, data);
 322                 } else if (operation_size) {
 323                         /* We have size, skip. */
 324                         DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
 325                                       operation_byte);
 326                         data += operation_size;
 327                 } else {
 328                         /* No size, can't skip without parsing. */
 329                         DRM_ERROR("Unsupported MIPI operation byte %u\n",
 330                                   operation_byte);
 331                         return;
 332                 }
 333         }
 334 }
 335
 336 static int vbt_panel_prepare(struct drm_panel *panel)
 337 {
 338         generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
 339         generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
 340
 341         return 0;
 342 }
 343
 344 static int vbt_panel_unprepare(struct drm_panel *panel)
 345 {
 346         generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
 347
 348         return 0;
 349 }
 350
 351 static int vbt_panel_enable(struct drm_panel *panel)
 352 {
 353         generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON);
 354
 355         return 0;
 356 }
 357
 358 static int vbt_panel_disable(struct drm_panel *panel)
 359 {
 360         generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF);
 361
 362         return 0;
 363 }
 364
 365 static int vbt_panel_get_modes(struct drm_panel *panel)
 366 {
 367         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 368         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 369         struct drm_device *dev = intel_dsi->base.base.dev;
 370         struct drm_i915_private *dev_priv = dev->dev_private;
 371         struct drm_display_mode *mode;
 372
 373         if (!panel->connector)
 374                 return 0;
 375
 376         mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
 377         if (!mode)
 378                 return 0;
 379
 380         mode->type |= DRM_MODE_TYPE_PREFERRED;
 381
 382         drm_mode_probed_add(panel->connector, mode);
 383
 384         return 1;
 385 }
 386
 387 static const struct drm_panel_funcs vbt_panel_funcs = {
 388         .disable = vbt_panel_disable,
 389         .unprepare = vbt_panel_unprepare,
 390         .prepare = vbt_panel_prepare,
 391         .enable = vbt_panel_enable,
 392         .get_modes = vbt_panel_get_modes,
 393 };
 394
 395 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 396 {
 397         struct drm_device *dev = intel_dsi->base.base.dev;
 398         struct drm_i915_private *dev_priv = dev->dev_private;
 399         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 400         struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
 401         struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
 402         struct vbt_panel *vbt_panel;
 403         u32 bits_per_pixel = 24;
 404         u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
 405         u32 ui_num, ui_den;
 406         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
 407         u32 ths_prepare_ns, tclk_trail_ns;
 408         u32 tclk_prepare_clkzero, ths_prepare_hszero;
 409         u32 lp_to_hs_switch, hs_to_lp_switch;
 410         u32 pclk, computed_ddr;
 411         u16 burst_mode_ratio;
 412         enum port port;
 413
 414         DRM_DEBUG_KMS("\n");
 415
 416         intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
 417         intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 418         intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 419         intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
 420         intel_dsi->dual_link = mipi_config->dual_link;
 421         intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 422
 423         if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
 424                 bits_per_pixel = 18;
 425         else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
 426                 bits_per_pixel = 16;
 427
 428         intel_dsi->operation_mode = mipi_config->is_cmd_mode;
 429         intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
 430         intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
 431         intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
 432         intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
 433         intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
 434         intel_dsi->init_count = mipi_config->master_init_timer;
 435         intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 436         intel_dsi->video_frmt_cfg_bits =
 437                 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 438
 439         pclk = mode->clock;
 440
 441         /* In dual link mode each port needs half of pixel clock */
 442         if (intel_dsi->dual_link) {
 443                 pclk = pclk / 2;
 444
 445                 /* we can enable pixel_overlap if needed by panel. In this
 446                  * case we need to increase the pixelclock for extra pixels
 447                  */
 448                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 449                         pclk += DIV_ROUND_UP(mode->vtotal *
 450                                                 intel_dsi->pixel_overlap *
 451                                                 60, 1000);
 452                 }
 453         }
 454
 455         /* Burst Mode Ratio
 456          * Target ddr frequency from VBT / non burst ddr freq
 457          * multiply by 100 to preserve remainder
 458          */
 459         if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 460                 if (mipi_config->target_burst_mode_freq) {
 461                         computed_ddr =
 462                                 (pclk * bits_per_pixel) / intel_dsi->lane_count;
 463
 464                         if (mipi_config->target_burst_mode_freq <
 465                                                                 computed_ddr) {
 466                                 DRM_ERROR("Burst mode freq is less than computed\n");
 467                                 return NULL;
 468                         }
 469
 470                         burst_mode_ratio = DIV_ROUND_UP(
 471                                 mipi_config->target_burst_mode_freq * 100,
 472                                 computed_ddr);
 473
 474                         pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
 475                 } else {
 476                         DRM_ERROR("Burst mode target is not set\n");
 477                         return NULL;
 478                 }
 479         } else
 480                 burst_mode_ratio = 100;
 481
 482         intel_dsi->burst_mode_ratio = burst_mode_ratio;
 483         intel_dsi->pclk = pclk;
 484
 485         bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
 486
 487         switch (intel_dsi->escape_clk_div) {
 488         case 0:
 489                 tlpx_ns = 50;
 490                 break;
 491         case 1:
 492                 tlpx_ns = 100;
 493                 break;
 494
 495         case 2:
 496                 tlpx_ns = 200;
 497                 break;
 498         default:
 499                 tlpx_ns = 50;
 500                 break;
 501         }
 502
 503         switch (intel_dsi->lane_count) {
 504         case 1:
 505         case 2:
 506                 extra_byte_count = 2;
 507                 break;
 508         case 3:
 509                 extra_byte_count = 4;
 510                 break;
 511         case 4:
 512         default:
 513                 extra_byte_count = 3;
 514                 break;
 515         }
 516
 517         /*
 518          * ui(s) = 1/f [f in hz]
 519          * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
 520          */
 521
 522         /* in Kbps */
 523         ui_num = NS_KHZ_RATIO;
 524         ui_den = bitrate;
 525
 526         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 527         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
 528
 529         /*
 530          * B060
 531          * LP byte clock = TLPX/ (8UI)
 532          */
 533         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 534
 535         /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
 536          *
 537          * Since txddrclkhs_i is 2xUI, all the count values programmed in
 538          * DPHY param register are divided by 2
 539          *
 540          * prepare count
 541          */
 542         ths_prepare_ns = max(mipi_config->ths_prepare,
 543                              mipi_config->tclk_prepare);
 544         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
 545
 546         /* exit zero count */
 547         exit_zero_cnt = DIV_ROUND_UP(
 548                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
 549                                 ui_num * 2
 550                                 );
 551
 552         /*
 553          * Exit zero  is unified val ths_zero and ths_exit
 554          * minimum value for ths_exit = 110ns
 555          * min (exit_zero_cnt * 2) = 110/UI
 556          * exit_zero_cnt = 55/UI
 557          */
 558          if (exit_zero_cnt < (55 * ui_den / ui_num))
 559                 if ((55 * ui_den) % ui_num)
 560                         exit_zero_cnt += 1;
 561
 562         /* clk zero count */
 563         clk_zero_cnt = DIV_ROUND_UP(
 564                         (tclk_prepare_clkzero - ths_prepare_ns)
 565                         * ui_den, 2 * ui_num);
 566
 567         /* trail count */
 568         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
 569         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
 570
 571         if (prepare_cnt > PREPARE_CNT_MAX ||
 572                 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
 573                 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
 574                 trail_cnt > TRAIL_CNT_MAX)
 575                 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
 576
 577         if (prepare_cnt > PREPARE_CNT_MAX)
 578                 prepare_cnt = PREPARE_CNT_MAX;
 579
 580         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
 581                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
 582
 583         if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
 584                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
 585
 586         if (trail_cnt > TRAIL_CNT_MAX)
 587                 trail_cnt = TRAIL_CNT_MAX;
 588
 589         /* B080 */
 590         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 591                                                 clk_zero_cnt << 8 | prepare_cnt;
 592
 593         /*
 594          * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
 595          *                                      + 10UI + Extra Byte Count
 596          *
 597          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
 598          * Extra Byte Count is calculated according to number of lanes.
 599          * High Low Switch Count is the Max of LP to HS and
 600          * HS to LP switch count
 601          *
 602          */
 603         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
 604
 605         /* B044 */
 606         /* FIXME:
 607          * The comment above does not match with the code */
 608         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
 609                                                 exit_zero_cnt * 2 + 10, 8);
 610
 611         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
 612
 613         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
 614         intel_dsi->hs_to_lp_count += extra_byte_count;
 615
 616         /* B088 */
 617         /* LP -> HS for clock lanes
 618          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
 619          *                                              extra byte count
 620          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
 621          *                                      2(in UI) + extra byte count
 622          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
 623          *                                      8 + extra byte count
 624          */
 625         intel_dsi->clk_lp_to_hs_count =
 626                 DIV_ROUND_UP(
 627                         4 * tlpx_ui + prepare_cnt * 2 +
 628                         clk_zero_cnt * 2,
 629                         8);
 630
 631         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
 632
 633         /* HS->LP for Clock Lanes
 634          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
 635          *                                              Extra byte count
 636          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
 637          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
 638          *                                              Extra byte count
 639          */
 640         intel_dsi->clk_hs_to_lp_count =
 641                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
 642                         8);
 643         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
 644
 645         DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
 646         DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
 647                                                 "disabled" : "enabled");
 648         DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
 649         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 650                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
 651         else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
 652                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
 653         else
 654                 DRM_DEBUG_KMS("Dual link: NONE\n");
 655         DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 656         DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 657         DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
 658         DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
 659         DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
 660         DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
 661         DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
 662         DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
 663         DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
 664         DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
 665         DRM_DEBUG_KMS("BTA %s\n",
 666                         intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
 667                         "disabled" : "enabled");
 668
 669         /* delays in VBT are in unit of 100us, so need to convert
 670          * here in ms
 671          * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
 672         intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 673         intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 674         intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
 675         intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
 676         intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
 677
 678         /* This is cheating a bit with the cleanup. */
 679         vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
 680         if (!vbt_panel)
 681                 return NULL;
 682
 683         vbt_panel->intel_dsi = intel_dsi;
 684         drm_panel_init(&vbt_panel->panel);
 685         vbt_panel->panel.funcs = &vbt_panel_funcs;
 686         drm_panel_add(&vbt_panel->panel);
 687
 688         /* a regular driver would get the device in probe */
 689         for_each_dsi_port(port, intel_dsi->ports) {
 690                 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
 691         }
 692
 693         return &vbt_panel->panel;
 694 }