2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <linux/slab.h>
32 #include <video/mipi_display.h>
33 #include <asm/intel-mid.h>
34 #include <video/mipi_display.h>
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
38 #include "intel_dsi_cmd.h"
40 #define MIPI_TRANSFER_MODE_SHIFT 0
41 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
42 #define MIPI_PORT_SHIFT 3
44 #define PREPARE_CNT_MAX 0x3F
45 #define EXIT_ZERO_CNT_MAX 0x3F
46 #define CLK_ZERO_CNT_MAX 0xFF
47 #define TRAIL_CNT_MAX 0x1F
49 #define NS_KHZ_RATIO 1000000
51 #define GPI0_NC_0_HV_DDI0_HPD 0x4130
52 #define GPIO_NC_0_HV_DDI0_PAD 0x4138
53 #define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
54 #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
55 #define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
56 #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
57 #define GPIO_NC_3_PANEL0_VDDEN 0x4140
58 #define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
59 #define GPIO_NC_4_PANEL0_BLKEN 0x4150
60 #define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
61 #define GPIO_NC_5_PANEL0_BLKCTL 0x4160
62 #define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
63 #define GPIO_NC_6_PCONF0 0x4180
64 #define GPIO_NC_6_PAD 0x4188
65 #define GPIO_NC_7_PCONF0 0x4190
66 #define GPIO_NC_7_PAD 0x4198
67 #define GPIO_NC_8_PCONF0 0x4170
68 #define GPIO_NC_8_PAD 0x4178
69 #define GPIO_NC_9_PCONF0 0x4100
70 #define GPIO_NC_9_PAD 0x4108
71 #define GPIO_NC_10_PCONF0 0x40E0
72 #define GPIO_NC_10_PAD 0x40E8
73 #define GPIO_NC_11_PCONF0 0x40F0
74 #define GPIO_NC_11_PAD 0x40F8
82 static struct gpio_table gtable
[] = {
83 { GPI0_NC_0_HV_DDI0_HPD
, GPIO_NC_0_HV_DDI0_PAD
, 0 },
84 { GPIO_NC_1_HV_DDI0_DDC_SDA
, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD
, 0 },
85 { GPIO_NC_2_HV_DDI0_DDC_SCL
, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD
, 0 },
86 { GPIO_NC_3_PANEL0_VDDEN
, GPIO_NC_3_PANEL0_VDDEN_PAD
, 0 },
87 { GPIO_NC_4_PANEL0_BLKEN
, GPIO_NC_4_PANEL0_BLKEN_PAD
, 0 },
88 { GPIO_NC_5_PANEL0_BLKCTL
, GPIO_NC_5_PANEL0_BLKCTL_PAD
, 0 },
89 { GPIO_NC_6_PCONF0
, GPIO_NC_6_PAD
, 0 },
90 { GPIO_NC_7_PCONF0
, GPIO_NC_7_PAD
, 0 },
91 { GPIO_NC_8_PCONF0
, GPIO_NC_8_PAD
, 0 },
92 { GPIO_NC_9_PCONF0
, GPIO_NC_9_PAD
, 0 },
93 { GPIO_NC_10_PCONF0
, GPIO_NC_10_PAD
, 0},
94 { GPIO_NC_11_PCONF0
, GPIO_NC_11_PAD
, 0}
97 static u8
*mipi_exec_send_packet(struct intel_dsi
*intel_dsi
, u8
*data
)
99 u8 type
, byte
, mode
, vc
, port
;
103 mode
= (byte
>> MIPI_TRANSFER_MODE_SHIFT
) & 0x1;
104 vc
= (byte
>> MIPI_VIRTUAL_CHANNEL_SHIFT
) & 0x3;
105 port
= (byte
>> MIPI_PORT_SHIFT
) & 0x3;
108 intel_dsi
->hs
= mode
;
110 /* get packet type and increment the pointer */
113 len
= *((u16
*) data
);
117 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM
:
118 dsi_vc_generic_write_0(intel_dsi
, vc
);
120 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM
:
121 dsi_vc_generic_write_1(intel_dsi
, vc
, *data
);
123 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
124 dsi_vc_generic_write_2(intel_dsi
, vc
, *data
, *(data
+ 1));
126 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM
:
127 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM
:
128 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM
:
129 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
131 case MIPI_DSI_GENERIC_LONG_WRITE
:
132 dsi_vc_generic_write(intel_dsi
, vc
, data
, len
);
134 case MIPI_DSI_DCS_SHORT_WRITE
:
135 dsi_vc_dcs_write_0(intel_dsi
, vc
, *data
);
137 case MIPI_DSI_DCS_SHORT_WRITE_PARAM
:
138 dsi_vc_dcs_write_1(intel_dsi
, vc
, *data
, *(data
+ 1));
140 case MIPI_DSI_DCS_READ
:
141 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
143 case MIPI_DSI_DCS_LONG_WRITE
:
144 dsi_vc_dcs_write(intel_dsi
, vc
, data
, len
);
153 static u8
*mipi_exec_delay(struct intel_dsi
*intel_dsi
, u8
*data
)
155 u32 delay
= *((u32
*) data
);
157 usleep_range(delay
, delay
+ 10);
163 static u8
*mipi_exec_gpio(struct intel_dsi
*intel_dsi
, u8
*data
)
168 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 function
= gtable
[gpio
].function_reg
;
177 pad
= gtable
[gpio
].pad_reg
;
179 mutex_lock(&dev_priv
->dpio_lock
);
180 if (!gtable
[gpio
].init
) {
181 /* program the function */
182 /* FIXME: remove constant below */
183 vlv_gpio_nc_write(dev_priv
, function
, 0x2000CC00);
184 gtable
[gpio
].init
= 1;
190 vlv_gpio_nc_write(dev_priv
, pad
, val
);
191 mutex_unlock(&dev_priv
->dpio_lock
);
196 typedef u8
* (*fn_mipi_elem_exec
)(struct intel_dsi
*intel_dsi
, u8
*data
);
197 static const fn_mipi_elem_exec exec_elem
[] = {
199 mipi_exec_send_packet
,
202 NULL
, /* status read; later */
206 * MIPI Sequence from VBT #53 parsing logic
207 * We have already separated each seqence during bios parsing
208 * Following is generic execution function for any sequence
211 static const char * const seq_name
[] = {
213 "MIPI_SEQ_ASSERT_RESET",
215 "MIPI_SEQ_DISPLAY_ON",
216 "MIPI_SEQ_DISPLAY_OFF",
217 "MIPI_SEQ_DEASSERT_RESET"
220 static void generic_exec_sequence(struct intel_dsi
*intel_dsi
, char *sequence
)
223 fn_mipi_elem_exec mipi_elem_exec
;
229 DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name
[*data
]);
231 /* go to the first element of the sequence */
234 /* parse each byte till we reach end of sequence byte - 0x00 */
237 mipi_elem_exec
= exec_elem
[index
];
238 if (!mipi_elem_exec
) {
239 DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
243 /* goto element payload */
246 /* execute the element specific rotines */
247 data
= mipi_elem_exec(intel_dsi
, data
);
250 * After processing the element, data should point to
251 * next element or end of sequence
252 * check if have we reached end of sequence
259 static bool generic_init(struct intel_dsi_device
*dsi
)
261 struct intel_dsi
*intel_dsi
= container_of(dsi
, struct intel_dsi
, dev
);
262 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
264 struct mipi_config
*mipi_config
= dev_priv
->vbt
.dsi
.config
;
265 struct mipi_pps_data
*pps
= dev_priv
->vbt
.dsi
.pps
;
266 struct drm_display_mode
*mode
= dev_priv
->vbt
.lfp_lvds_vbt_mode
;
267 u32 bits_per_pixel
= 24;
268 u32 tlpx_ns
, extra_byte_count
, bitrate
, tlpx_ui
;
270 u32 prepare_cnt
, exit_zero_cnt
, clk_zero_cnt
, trail_cnt
;
271 u32 ths_prepare_ns
, tclk_trail_ns
;
272 u32 tclk_prepare_clkzero
, ths_prepare_hszero
;
273 u32 lp_to_hs_switch
, hs_to_lp_switch
;
277 intel_dsi
->eotp_pkt
= mipi_config
->eot_pkt_disabled
? 0 : 1;
278 intel_dsi
->clock_stop
= mipi_config
->enable_clk_stop
? 1 : 0;
279 intel_dsi
->lane_count
= mipi_config
->lane_cnt
+ 1;
280 intel_dsi
->pixel_format
= mipi_config
->videomode_color_format
<< 7;
282 if (intel_dsi
->pixel_format
== VID_MODE_FORMAT_RGB666
)
284 else if (intel_dsi
->pixel_format
== VID_MODE_FORMAT_RGB565
)
287 bitrate
= (mode
->clock
* bits_per_pixel
) / intel_dsi
->lane_count
;
289 intel_dsi
->operation_mode
= mipi_config
->is_cmd_mode
;
290 intel_dsi
->video_mode_format
= mipi_config
->video_transfer_mode
;
291 intel_dsi
->escape_clk_div
= mipi_config
->byte_clk_sel
;
292 intel_dsi
->lp_rx_timeout
= mipi_config
->lp_rx_timeout
;
293 intel_dsi
->turn_arnd_val
= mipi_config
->turn_around_timeout
;
294 intel_dsi
->rst_timer_val
= mipi_config
->device_reset_timer
;
295 intel_dsi
->init_count
= mipi_config
->master_init_timer
;
296 intel_dsi
->bw_timer
= mipi_config
->dbi_bw_timer
;
297 intel_dsi
->video_frmt_cfg_bits
= mipi_config
->bta_enabled
? DISABLE_VIDEO_BTA
: 0;
299 switch (intel_dsi
->escape_clk_div
) {
315 switch (intel_dsi
->lane_count
) {
318 extra_byte_count
= 2;
321 extra_byte_count
= 4;
325 extra_byte_count
= 3;
330 * ui(s) = 1/f [f in hz]
331 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
335 ui_num
= NS_KHZ_RATIO
;
338 tclk_prepare_clkzero
= mipi_config
->tclk_prepare_clkzero
;
339 ths_prepare_hszero
= mipi_config
->ths_prepare_hszero
;
343 * LP byte clock = TLPX/ (8UI)
345 intel_dsi
->lp_byte_clk
= DIV_ROUND_UP(tlpx_ns
* ui_den
, 8 * ui_num
);
347 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
349 * Since txddrclkhs_i is 2xUI, all the count values programmed in
350 * DPHY param register are divided by 2
354 ths_prepare_ns
= max(mipi_config
->ths_prepare
, mipi_config
->tclk_prepare
);
355 prepare_cnt
= DIV_ROUND_UP(ths_prepare_ns
* ui_den
, ui_num
* 2);
357 /* exit zero count */
358 exit_zero_cnt
= DIV_ROUND_UP(
359 (ths_prepare_hszero
- ths_prepare_ns
) * ui_den
,
364 * Exit zero is unified val ths_zero and ths_exit
365 * minimum value for ths_exit = 110ns
366 * min (exit_zero_cnt * 2) = 110/UI
367 * exit_zero_cnt = 55/UI
369 if (exit_zero_cnt
< (55 * ui_den
/ ui_num
))
370 if ((55 * ui_den
) % ui_num
)
374 clk_zero_cnt
= DIV_ROUND_UP(
375 (tclk_prepare_clkzero
- ths_prepare_ns
)
376 * ui_den
, 2 * ui_num
);
379 tclk_trail_ns
= max(mipi_config
->tclk_trail
, mipi_config
->ths_trail
);
380 trail_cnt
= DIV_ROUND_UP(tclk_trail_ns
* ui_den
, 2 * ui_num
);
382 if (prepare_cnt
> PREPARE_CNT_MAX
||
383 exit_zero_cnt
> EXIT_ZERO_CNT_MAX
||
384 clk_zero_cnt
> CLK_ZERO_CNT_MAX
||
385 trail_cnt
> TRAIL_CNT_MAX
)
386 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
388 if (prepare_cnt
> PREPARE_CNT_MAX
)
389 prepare_cnt
= PREPARE_CNT_MAX
;
391 if (exit_zero_cnt
> EXIT_ZERO_CNT_MAX
)
392 exit_zero_cnt
= EXIT_ZERO_CNT_MAX
;
394 if (clk_zero_cnt
> CLK_ZERO_CNT_MAX
)
395 clk_zero_cnt
= CLK_ZERO_CNT_MAX
;
397 if (trail_cnt
> TRAIL_CNT_MAX
)
398 trail_cnt
= TRAIL_CNT_MAX
;
401 intel_dsi
->dphy_reg
= exit_zero_cnt
<< 24 | trail_cnt
<< 16 |
402 clk_zero_cnt
<< 8 | prepare_cnt
;
405 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
406 * + 10UI + Extra Byte Count
408 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
409 * Extra Byte Count is calculated according to number of lanes.
410 * High Low Switch Count is the Max of LP to HS and
411 * HS to LP switch count
414 tlpx_ui
= DIV_ROUND_UP(tlpx_ns
* ui_den
, ui_num
);
418 * The comment above does not match with the code */
419 lp_to_hs_switch
= DIV_ROUND_UP(4 * tlpx_ui
+ prepare_cnt
* 2 +
420 exit_zero_cnt
* 2 + 10, 8);
422 hs_to_lp_switch
= DIV_ROUND_UP(mipi_config
->ths_trail
+ 2 * tlpx_ui
, 8);
424 intel_dsi
->hs_to_lp_count
= max(lp_to_hs_switch
, hs_to_lp_switch
);
425 intel_dsi
->hs_to_lp_count
+= extra_byte_count
;
428 /* LP -> HS for clock lanes
429 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
431 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
432 * 2(in UI) + extra byte count
433 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
434 * 8 + extra byte count
436 intel_dsi
->clk_lp_to_hs_count
=
438 4 * tlpx_ui
+ prepare_cnt
* 2 +
442 intel_dsi
->clk_lp_to_hs_count
+= extra_byte_count
;
444 /* HS->LP for Clock Lanes
445 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
447 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
448 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
451 intel_dsi
->clk_hs_to_lp_count
=
452 DIV_ROUND_UP(2 * tlpx_ui
+ trail_cnt
* 2 + 8,
454 intel_dsi
->clk_hs_to_lp_count
+= extra_byte_count
;
456 DRM_DEBUG_KMS("Eot %s\n", intel_dsi
->eotp_pkt
? "enabled" : "disabled");
457 DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi
->clock_stop
?
458 "disabled" : "enabled");
459 DRM_DEBUG_KMS("Mode %s\n", intel_dsi
->operation_mode
? "command" : "video");
460 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi
->pixel_format
);
461 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi
->escape_clk_div
);
462 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi
->lp_rx_timeout
);
463 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi
->turn_arnd_val
);
464 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi
->init_count
);
465 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi
->hs_to_lp_count
);
466 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi
->lp_byte_clk
);
467 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi
->bw_timer
);
468 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi
->clk_lp_to_hs_count
);
469 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi
->clk_hs_to_lp_count
);
470 DRM_DEBUG_KMS("BTA %s\n",
471 intel_dsi
->video_frmt_cfg_bits
& DISABLE_VIDEO_BTA
?
472 "disabled" : "enabled");
474 /* delays in VBT are in unit of 100us, so need to convert
476 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
477 intel_dsi
->backlight_off_delay
= pps
->bl_disable_delay
/ 10;
478 intel_dsi
->backlight_on_delay
= pps
->bl_enable_delay
/ 10;
479 intel_dsi
->panel_on_delay
= pps
->panel_on_delay
/ 10;
480 intel_dsi
->panel_off_delay
= pps
->panel_off_delay
/ 10;
481 intel_dsi
->panel_pwr_cycle_delay
= pps
->panel_power_cycle_delay
/ 10;
486 static int generic_mode_valid(struct intel_dsi_device
*dsi
,
487 struct drm_display_mode
*mode
)
492 static bool generic_mode_fixup(struct intel_dsi_device
*dsi
,
493 const struct drm_display_mode
*mode
,
494 struct drm_display_mode
*adjusted_mode
) {
498 static void generic_panel_reset(struct intel_dsi_device
*dsi
)
500 struct intel_dsi
*intel_dsi
= container_of(dsi
, struct intel_dsi
, dev
);
501 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
504 char *sequence
= dev_priv
->vbt
.dsi
.sequence
[MIPI_SEQ_ASSERT_RESET
];
506 generic_exec_sequence(intel_dsi
, sequence
);
509 static void generic_disable_panel_power(struct intel_dsi_device
*dsi
)
511 struct intel_dsi
*intel_dsi
= container_of(dsi
, struct intel_dsi
, dev
);
512 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
515 char *sequence
= dev_priv
->vbt
.dsi
.sequence
[MIPI_SEQ_DEASSERT_RESET
];
517 generic_exec_sequence(intel_dsi
, sequence
);
520 static void generic_send_otp_cmds(struct intel_dsi_device
*dsi
)
522 struct intel_dsi
*intel_dsi
= container_of(dsi
, struct intel_dsi
, dev
);
523 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
526 char *sequence
= dev_priv
->vbt
.dsi
.sequence
[MIPI_SEQ_INIT_OTP
];
528 generic_exec_sequence(intel_dsi
, sequence
);
531 static void generic_enable(struct intel_dsi_device
*dsi
)
533 struct intel_dsi
*intel_dsi
= container_of(dsi
, struct intel_dsi
, dev
);
534 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
537 char *sequence
= dev_priv
->vbt
.dsi
.sequence
[MIPI_SEQ_DISPLAY_ON
];
539 generic_exec_sequence(intel_dsi
, sequence
);
542 static void generic_disable(struct intel_dsi_device
*dsi
)
544 struct intel_dsi
*intel_dsi
= container_of(dsi
, struct intel_dsi
, dev
);
545 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
548 char *sequence
= dev_priv
->vbt
.dsi
.sequence
[MIPI_SEQ_DISPLAY_OFF
];
550 generic_exec_sequence(intel_dsi
, sequence
);
553 static enum drm_connector_status
generic_detect(struct intel_dsi_device
*dsi
)
555 return connector_status_connected
;
558 static bool generic_get_hw_state(struct intel_dsi_device
*dev
)
563 static struct drm_display_mode
*generic_get_modes(struct intel_dsi_device
*dsi
)
565 struct intel_dsi
*intel_dsi
= container_of(dsi
, struct intel_dsi
, dev
);
566 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
569 dev_priv
->vbt
.lfp_lvds_vbt_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
570 return dev_priv
->vbt
.lfp_lvds_vbt_mode
;
573 static void generic_destroy(struct intel_dsi_device
*dsi
) { }
575 /* Callbacks. We might not need them all. */
576 struct intel_dsi_dev_ops vbt_generic_dsi_display_ops
= {
577 .init
= generic_init
,
578 .mode_valid
= generic_mode_valid
,
579 .mode_fixup
= generic_mode_fixup
,
580 .panel_reset
= generic_panel_reset
,
581 .disable_panel_power
= generic_disable_panel_power
,
582 .send_otp_cmds
= generic_send_otp_cmds
,
583 .enable
= generic_enable
,
584 .disable
= generic_disable
,
585 .detect
= generic_detect
,
586 .get_hw_state
= generic_get_hw_state
,
587 .get_modes
= generic_get_modes
,
588 .destroy
= generic_destroy
,