2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <linux/slab.h>
33 #include <video/mipi_display.h>
34 #include <asm/intel-mid.h>
35 #include <video/mipi_display.h>
37 #include "intel_drv.h"
38 #include "intel_dsi.h"
41 struct drm_panel panel
;
42 struct intel_dsi
*intel_dsi
;
45 static inline struct vbt_panel
*to_vbt_panel(struct drm_panel
*panel
)
47 return container_of(panel
, struct vbt_panel
, panel
);
50 #define MIPI_TRANSFER_MODE_SHIFT 0
51 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
52 #define MIPI_PORT_SHIFT 3
54 #define PREPARE_CNT_MAX 0x3F
55 #define EXIT_ZERO_CNT_MAX 0x3F
56 #define CLK_ZERO_CNT_MAX 0xFF
57 #define TRAIL_CNT_MAX 0x1F
59 #define NS_KHZ_RATIO 1000000
61 /* base offsets for gpio pads */
62 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
63 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
64 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
65 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
66 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
67 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
68 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
69 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
70 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
71 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
72 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
73 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
75 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
76 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
83 static struct gpio_map vlv_gpio_table
[] = {
84 { VLV_GPIO_NC_0_HV_DDI0_HPD
},
85 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA
},
86 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL
},
87 { VLV_GPIO_NC_3_PANEL0_VDDEN
},
88 { VLV_GPIO_NC_4_PANEL0_BKLTEN
},
89 { VLV_GPIO_NC_5_PANEL0_BKLTCTL
},
90 { VLV_GPIO_NC_6_HV_DDI1_HPD
},
91 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA
},
92 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL
},
93 { VLV_GPIO_NC_9_PANEL1_VDDEN
},
94 { VLV_GPIO_NC_10_PANEL1_BKLTEN
},
95 { VLV_GPIO_NC_11_PANEL1_BKLTCTL
},
98 #define CHV_GPIO_IDX_START_N 0
99 #define CHV_GPIO_IDX_START_E 73
100 #define CHV_GPIO_IDX_START_SW 100
101 #define CHV_GPIO_IDX_START_SE 198
103 #define CHV_VBT_MAX_PINS_PER_FMLY 15
105 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
106 #define CHV_GPIO_GPIOEN (1 << 15)
107 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
108 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
109 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
110 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
111 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
113 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
114 #define CHV_GPIO_CFGLOCK (1 << 31)
116 static inline enum port
intel_dsi_seq_port_to_port(u8 port
)
118 return port
? PORT_C
: PORT_A
;
121 static const u8
*mipi_exec_send_packet(struct intel_dsi
*intel_dsi
,
124 struct mipi_dsi_device
*dsi_device
;
125 u8 type
, flags
, seq_port
;
132 len
= *((u16
*) data
);
135 seq_port
= (flags
>> MIPI_PORT_SHIFT
) & 3;
137 /* For DSI single link on Port A & C, the seq_port value which is
138 * parsed from Sequence Block#53 of VBT has been set to 0
139 * Now, read/write of packets for the DSI single link on Port A and
140 * Port C will based on the DVO port from VBT block 2.
142 if (intel_dsi
->ports
== (1 << PORT_C
))
145 port
= intel_dsi_seq_port_to_port(seq_port
);
147 dsi_device
= intel_dsi
->dsi_hosts
[port
]->device
;
149 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port
));
153 if ((flags
>> MIPI_TRANSFER_MODE_SHIFT
) & 1)
154 dsi_device
->mode_flags
&= ~MIPI_DSI_MODE_LPM
;
156 dsi_device
->mode_flags
|= MIPI_DSI_MODE_LPM
;
158 dsi_device
->channel
= (flags
>> MIPI_VIRTUAL_CHANNEL_SHIFT
) & 3;
161 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM
:
162 mipi_dsi_generic_write(dsi_device
, NULL
, 0);
164 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM
:
165 mipi_dsi_generic_write(dsi_device
, data
, 1);
167 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
168 mipi_dsi_generic_write(dsi_device
, data
, 2);
170 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM
:
171 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM
:
172 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM
:
173 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
175 case MIPI_DSI_GENERIC_LONG_WRITE
:
176 mipi_dsi_generic_write(dsi_device
, data
, len
);
178 case MIPI_DSI_DCS_SHORT_WRITE
:
179 mipi_dsi_dcs_write_buffer(dsi_device
, data
, 1);
181 case MIPI_DSI_DCS_SHORT_WRITE_PARAM
:
182 mipi_dsi_dcs_write_buffer(dsi_device
, data
, 2);
184 case MIPI_DSI_DCS_READ
:
185 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
187 case MIPI_DSI_DCS_LONG_WRITE
:
188 mipi_dsi_dcs_write_buffer(dsi_device
, data
, len
);
198 static const u8
*mipi_exec_delay(struct intel_dsi
*intel_dsi
, const u8
*data
)
200 u32 delay
= *((const u32
*) data
);
202 usleep_range(delay
, delay
+ 10);
208 static void vlv_exec_gpio(struct drm_i915_private
*dev_priv
,
209 u8 gpio_source
, u8 gpio_index
, bool value
)
211 struct gpio_map
*map
;
216 if (gpio_index
>= ARRAY_SIZE(vlv_gpio_table
)) {
217 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index
);
221 map
= &vlv_gpio_table
[gpio_index
];
223 if (dev_priv
->vbt
.dsi
.seq_version
>= 3) {
224 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
225 port
= IOSF_PORT_GPIO_NC
;
227 if (gpio_source
== 0) {
228 port
= IOSF_PORT_GPIO_NC
;
229 } else if (gpio_source
== 1) {
230 DRM_DEBUG_KMS("SC gpio not supported\n");
233 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source
);
238 pconf0
= VLV_GPIO_PCONF0(map
->base_offset
);
239 padval
= VLV_GPIO_PAD_VAL(map
->base_offset
);
241 mutex_lock(&dev_priv
->sb_lock
);
243 /* FIXME: remove constant below */
244 vlv_iosf_sb_write(dev_priv
, port
, pconf0
, 0x2000CC00);
249 vlv_iosf_sb_write(dev_priv
, port
, padval
, tmp
);
250 mutex_unlock(&dev_priv
->sb_lock
);
253 static void chv_exec_gpio(struct drm_i915_private
*dev_priv
,
254 u8 gpio_source
, u8 gpio_index
, bool value
)
260 if (dev_priv
->vbt
.dsi
.seq_version
>= 3) {
261 if (gpio_index
>= CHV_GPIO_IDX_START_SE
) {
262 /* XXX: it's unclear whether 255->57 is part of SE. */
263 gpio_index
-= CHV_GPIO_IDX_START_SE
;
264 port
= CHV_IOSF_PORT_GPIO_SE
;
265 } else if (gpio_index
>= CHV_GPIO_IDX_START_SW
) {
266 gpio_index
-= CHV_GPIO_IDX_START_SW
;
267 port
= CHV_IOSF_PORT_GPIO_SW
;
268 } else if (gpio_index
>= CHV_GPIO_IDX_START_E
) {
269 gpio_index
-= CHV_GPIO_IDX_START_E
;
270 port
= CHV_IOSF_PORT_GPIO_E
;
272 port
= CHV_IOSF_PORT_GPIO_N
;
275 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
276 if (gpio_source
!= 0) {
277 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source
);
281 if (gpio_index
>= CHV_GPIO_IDX_START_E
) {
282 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
287 port
= CHV_IOSF_PORT_GPIO_N
;
290 family_num
= gpio_index
/ CHV_VBT_MAX_PINS_PER_FMLY
;
291 gpio_index
= gpio_index
% CHV_VBT_MAX_PINS_PER_FMLY
;
293 cfg0
= CHV_GPIO_PAD_CFG0(family_num
, gpio_index
);
294 cfg1
= CHV_GPIO_PAD_CFG1(family_num
, gpio_index
);
296 mutex_lock(&dev_priv
->sb_lock
);
297 vlv_iosf_sb_write(dev_priv
, port
, cfg1
, 0);
298 vlv_iosf_sb_write(dev_priv
, port
, cfg0
,
299 CHV_GPIO_GPIOCFG_GPO
| CHV_GPIO_GPIOTXSTATE(value
));
300 mutex_unlock(&dev_priv
->sb_lock
);
303 static const u8
*mipi_exec_gpio(struct intel_dsi
*intel_dsi
, const u8
*data
)
305 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
306 struct drm_i915_private
*dev_priv
= to_i915(dev
);
307 u8 gpio_source
, gpio_index
;
310 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
313 gpio_index
= *data
++;
315 /* gpio source in sequence v2 only */
316 if (dev_priv
->vbt
.dsi
.seq_version
== 2)
317 gpio_source
= (*data
>> 1) & 3;
324 if (IS_VALLEYVIEW(dev_priv
))
325 vlv_exec_gpio(dev_priv
, gpio_source
, gpio_index
, value
);
326 else if (IS_CHERRYVIEW(dev_priv
))
327 chv_exec_gpio(dev_priv
, gpio_source
, gpio_index
, value
);
329 DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
334 static const u8
*mipi_exec_i2c_skip(struct intel_dsi
*intel_dsi
, const u8
*data
)
336 return data
+ *(data
+ 6) + 7;
339 typedef const u8
* (*fn_mipi_elem_exec
)(struct intel_dsi
*intel_dsi
,
341 static const fn_mipi_elem_exec exec_elem
[] = {
342 [MIPI_SEQ_ELEM_SEND_PKT
] = mipi_exec_send_packet
,
343 [MIPI_SEQ_ELEM_DELAY
] = mipi_exec_delay
,
344 [MIPI_SEQ_ELEM_GPIO
] = mipi_exec_gpio
,
345 [MIPI_SEQ_ELEM_I2C
] = mipi_exec_i2c_skip
,
349 * MIPI Sequence from VBT #53 parsing logic
350 * We have already separated each seqence during bios parsing
351 * Following is generic execution function for any sequence
354 static const char * const seq_name
[] = {
355 [MIPI_SEQ_ASSERT_RESET
] = "MIPI_SEQ_ASSERT_RESET",
356 [MIPI_SEQ_INIT_OTP
] = "MIPI_SEQ_INIT_OTP",
357 [MIPI_SEQ_DISPLAY_ON
] = "MIPI_SEQ_DISPLAY_ON",
358 [MIPI_SEQ_DISPLAY_OFF
] = "MIPI_SEQ_DISPLAY_OFF",
359 [MIPI_SEQ_DEASSERT_RESET
] = "MIPI_SEQ_DEASSERT_RESET",
360 [MIPI_SEQ_BACKLIGHT_ON
] = "MIPI_SEQ_BACKLIGHT_ON",
361 [MIPI_SEQ_BACKLIGHT_OFF
] = "MIPI_SEQ_BACKLIGHT_OFF",
362 [MIPI_SEQ_TEAR_ON
] = "MIPI_SEQ_TEAR_ON",
363 [MIPI_SEQ_TEAR_OFF
] = "MIPI_SEQ_TEAR_OFF",
364 [MIPI_SEQ_POWER_ON
] = "MIPI_SEQ_POWER_ON",
365 [MIPI_SEQ_POWER_OFF
] = "MIPI_SEQ_POWER_OFF",
368 static const char *sequence_name(enum mipi_seq seq_id
)
370 if (seq_id
< ARRAY_SIZE(seq_name
) && seq_name
[seq_id
])
371 return seq_name
[seq_id
];
376 static void generic_exec_sequence(struct drm_panel
*panel
, enum mipi_seq seq_id
)
378 struct vbt_panel
*vbt_panel
= to_vbt_panel(panel
);
379 struct intel_dsi
*intel_dsi
= vbt_panel
->intel_dsi
;
380 struct drm_i915_private
*dev_priv
= to_i915(intel_dsi
->base
.base
.dev
);
382 fn_mipi_elem_exec mipi_elem_exec
;
384 if (WARN_ON(seq_id
>= ARRAY_SIZE(dev_priv
->vbt
.dsi
.sequence
)))
387 data
= dev_priv
->vbt
.dsi
.sequence
[seq_id
];
389 DRM_DEBUG_KMS("MIPI sequence %d - %s not available\n",
390 seq_id
, sequence_name(seq_id
));
394 WARN_ON(*data
!= seq_id
);
396 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
397 seq_id
, sequence_name(seq_id
));
399 /* Skip Sequence Byte. */
402 /* Skip Size of Sequence. */
403 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
407 u8 operation_byte
= *data
++;
408 u8 operation_size
= 0;
410 if (operation_byte
== MIPI_SEQ_ELEM_END
)
413 if (operation_byte
< ARRAY_SIZE(exec_elem
))
414 mipi_elem_exec
= exec_elem
[operation_byte
];
416 mipi_elem_exec
= NULL
;
418 /* Size of Operation. */
419 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
420 operation_size
= *data
++;
422 if (mipi_elem_exec
) {
423 data
= mipi_elem_exec(intel_dsi
, data
);
424 } else if (operation_size
) {
425 /* We have size, skip. */
426 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
428 data
+= operation_size
;
430 /* No size, can't skip without parsing. */
431 DRM_ERROR("Unsupported MIPI operation byte %u\n",
438 static int vbt_panel_prepare(struct drm_panel
*panel
)
440 generic_exec_sequence(panel
, MIPI_SEQ_ASSERT_RESET
);
441 generic_exec_sequence(panel
, MIPI_SEQ_INIT_OTP
);
446 static int vbt_panel_unprepare(struct drm_panel
*panel
)
448 generic_exec_sequence(panel
, MIPI_SEQ_DEASSERT_RESET
);
453 static int vbt_panel_enable(struct drm_panel
*panel
)
455 generic_exec_sequence(panel
, MIPI_SEQ_DISPLAY_ON
);
460 static int vbt_panel_disable(struct drm_panel
*panel
)
462 generic_exec_sequence(panel
, MIPI_SEQ_DISPLAY_OFF
);
467 static int vbt_panel_get_modes(struct drm_panel
*panel
)
469 struct vbt_panel
*vbt_panel
= to_vbt_panel(panel
);
470 struct intel_dsi
*intel_dsi
= vbt_panel
->intel_dsi
;
471 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
472 struct drm_i915_private
*dev_priv
= to_i915(dev
);
473 struct drm_display_mode
*mode
;
475 if (!panel
->connector
)
478 mode
= drm_mode_duplicate(dev
, dev_priv
->vbt
.lfp_lvds_vbt_mode
);
482 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
484 drm_mode_probed_add(panel
->connector
, mode
);
489 static const struct drm_panel_funcs vbt_panel_funcs
= {
490 .disable
= vbt_panel_disable
,
491 .unprepare
= vbt_panel_unprepare
,
492 .prepare
= vbt_panel_prepare
,
493 .enable
= vbt_panel_enable
,
494 .get_modes
= vbt_panel_get_modes
,
497 struct drm_panel
*vbt_panel_init(struct intel_dsi
*intel_dsi
, u16 panel_id
)
499 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
500 struct drm_i915_private
*dev_priv
= to_i915(dev
);
501 struct mipi_config
*mipi_config
= dev_priv
->vbt
.dsi
.config
;
502 struct mipi_pps_data
*pps
= dev_priv
->vbt
.dsi
.pps
;
503 struct drm_display_mode
*mode
= dev_priv
->vbt
.lfp_lvds_vbt_mode
;
504 struct vbt_panel
*vbt_panel
;
506 u32 tlpx_ns
, extra_byte_count
, bitrate
, tlpx_ui
;
508 u32 prepare_cnt
, exit_zero_cnt
, clk_zero_cnt
, trail_cnt
;
509 u32 ths_prepare_ns
, tclk_trail_ns
;
510 u32 tclk_prepare_clkzero
, ths_prepare_hszero
;
511 u32 lp_to_hs_switch
, hs_to_lp_switch
;
512 u32 pclk
, computed_ddr
;
513 u16 burst_mode_ratio
;
518 intel_dsi
->eotp_pkt
= mipi_config
->eot_pkt_disabled
? 0 : 1;
519 intel_dsi
->clock_stop
= mipi_config
->enable_clk_stop
? 1 : 0;
520 intel_dsi
->lane_count
= mipi_config
->lane_cnt
+ 1;
521 intel_dsi
->pixel_format
=
522 pixel_format_from_register_bits(
523 mipi_config
->videomode_color_format
<< 7);
524 bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
526 intel_dsi
->dual_link
= mipi_config
->dual_link
;
527 intel_dsi
->pixel_overlap
= mipi_config
->pixel_overlap
;
528 intel_dsi
->operation_mode
= mipi_config
->is_cmd_mode
;
529 intel_dsi
->video_mode_format
= mipi_config
->video_transfer_mode
;
530 intel_dsi
->escape_clk_div
= mipi_config
->byte_clk_sel
;
531 intel_dsi
->lp_rx_timeout
= mipi_config
->lp_rx_timeout
;
532 intel_dsi
->turn_arnd_val
= mipi_config
->turn_around_timeout
;
533 intel_dsi
->rst_timer_val
= mipi_config
->device_reset_timer
;
534 intel_dsi
->init_count
= mipi_config
->master_init_timer
;
535 intel_dsi
->bw_timer
= mipi_config
->dbi_bw_timer
;
536 intel_dsi
->video_frmt_cfg_bits
=
537 mipi_config
->bta_enabled
? DISABLE_VIDEO_BTA
: 0;
541 /* In dual link mode each port needs half of pixel clock */
542 if (intel_dsi
->dual_link
) {
545 /* we can enable pixel_overlap if needed by panel. In this
546 * case we need to increase the pixelclock for extra pixels
548 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
549 pclk
+= DIV_ROUND_UP(mode
->vtotal
*
550 intel_dsi
->pixel_overlap
*
556 * Target ddr frequency from VBT / non burst ddr freq
557 * multiply by 100 to preserve remainder
559 if (intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
560 if (mipi_config
->target_burst_mode_freq
) {
561 computed_ddr
= (pclk
* bpp
) / intel_dsi
->lane_count
;
563 if (mipi_config
->target_burst_mode_freq
<
565 DRM_ERROR("Burst mode freq is less than computed\n");
569 burst_mode_ratio
= DIV_ROUND_UP(
570 mipi_config
->target_burst_mode_freq
* 100,
573 pclk
= DIV_ROUND_UP(pclk
* burst_mode_ratio
, 100);
575 DRM_ERROR("Burst mode target is not set\n");
579 burst_mode_ratio
= 100;
581 intel_dsi
->burst_mode_ratio
= burst_mode_ratio
;
582 intel_dsi
->pclk
= pclk
;
584 bitrate
= (pclk
* bpp
) / intel_dsi
->lane_count
;
586 switch (intel_dsi
->escape_clk_div
) {
602 switch (intel_dsi
->lane_count
) {
605 extra_byte_count
= 2;
608 extra_byte_count
= 4;
612 extra_byte_count
= 3;
617 * ui(s) = 1/f [f in hz]
618 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
622 ui_num
= NS_KHZ_RATIO
;
625 tclk_prepare_clkzero
= mipi_config
->tclk_prepare_clkzero
;
626 ths_prepare_hszero
= mipi_config
->ths_prepare_hszero
;
630 * LP byte clock = TLPX/ (8UI)
632 intel_dsi
->lp_byte_clk
= DIV_ROUND_UP(tlpx_ns
* ui_den
, 8 * ui_num
);
634 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
636 * Since txddrclkhs_i is 2xUI, all the count values programmed in
637 * DPHY param register are divided by 2
641 ths_prepare_ns
= max(mipi_config
->ths_prepare
,
642 mipi_config
->tclk_prepare
);
643 prepare_cnt
= DIV_ROUND_UP(ths_prepare_ns
* ui_den
, ui_num
* 2);
645 /* exit zero count */
646 exit_zero_cnt
= DIV_ROUND_UP(
647 (ths_prepare_hszero
- ths_prepare_ns
) * ui_den
,
652 * Exit zero is unified val ths_zero and ths_exit
653 * minimum value for ths_exit = 110ns
654 * min (exit_zero_cnt * 2) = 110/UI
655 * exit_zero_cnt = 55/UI
657 if (exit_zero_cnt
< (55 * ui_den
/ ui_num
) && (55 * ui_den
) % ui_num
)
661 clk_zero_cnt
= DIV_ROUND_UP(
662 (tclk_prepare_clkzero
- ths_prepare_ns
)
663 * ui_den
, 2 * ui_num
);
666 tclk_trail_ns
= max(mipi_config
->tclk_trail
, mipi_config
->ths_trail
);
667 trail_cnt
= DIV_ROUND_UP(tclk_trail_ns
* ui_den
, 2 * ui_num
);
669 if (prepare_cnt
> PREPARE_CNT_MAX
||
670 exit_zero_cnt
> EXIT_ZERO_CNT_MAX
||
671 clk_zero_cnt
> CLK_ZERO_CNT_MAX
||
672 trail_cnt
> TRAIL_CNT_MAX
)
673 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
675 if (prepare_cnt
> PREPARE_CNT_MAX
)
676 prepare_cnt
= PREPARE_CNT_MAX
;
678 if (exit_zero_cnt
> EXIT_ZERO_CNT_MAX
)
679 exit_zero_cnt
= EXIT_ZERO_CNT_MAX
;
681 if (clk_zero_cnt
> CLK_ZERO_CNT_MAX
)
682 clk_zero_cnt
= CLK_ZERO_CNT_MAX
;
684 if (trail_cnt
> TRAIL_CNT_MAX
)
685 trail_cnt
= TRAIL_CNT_MAX
;
688 intel_dsi
->dphy_reg
= exit_zero_cnt
<< 24 | trail_cnt
<< 16 |
689 clk_zero_cnt
<< 8 | prepare_cnt
;
692 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
693 * + 10UI + Extra Byte Count
695 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
696 * Extra Byte Count is calculated according to number of lanes.
697 * High Low Switch Count is the Max of LP to HS and
698 * HS to LP switch count
701 tlpx_ui
= DIV_ROUND_UP(tlpx_ns
* ui_den
, ui_num
);
705 * The comment above does not match with the code */
706 lp_to_hs_switch
= DIV_ROUND_UP(4 * tlpx_ui
+ prepare_cnt
* 2 +
707 exit_zero_cnt
* 2 + 10, 8);
709 hs_to_lp_switch
= DIV_ROUND_UP(mipi_config
->ths_trail
+ 2 * tlpx_ui
, 8);
711 intel_dsi
->hs_to_lp_count
= max(lp_to_hs_switch
, hs_to_lp_switch
);
712 intel_dsi
->hs_to_lp_count
+= extra_byte_count
;
715 /* LP -> HS for clock lanes
716 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
718 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
719 * 2(in UI) + extra byte count
720 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
721 * 8 + extra byte count
723 intel_dsi
->clk_lp_to_hs_count
=
725 4 * tlpx_ui
+ prepare_cnt
* 2 +
729 intel_dsi
->clk_lp_to_hs_count
+= extra_byte_count
;
731 /* HS->LP for Clock Lanes
732 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
734 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
735 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
738 intel_dsi
->clk_hs_to_lp_count
=
739 DIV_ROUND_UP(2 * tlpx_ui
+ trail_cnt
* 2 + 8,
741 intel_dsi
->clk_hs_to_lp_count
+= extra_byte_count
;
743 DRM_DEBUG_KMS("Eot %s\n", intel_dsi
->eotp_pkt
? "enabled" : "disabled");
744 DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi
->clock_stop
?
745 "disabled" : "enabled");
746 DRM_DEBUG_KMS("Mode %s\n", intel_dsi
->operation_mode
? "command" : "video");
747 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
748 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
749 else if (intel_dsi
->dual_link
== DSI_DUAL_LINK_PIXEL_ALT
)
750 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
752 DRM_DEBUG_KMS("Dual link: NONE\n");
753 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi
->pixel_format
);
754 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi
->escape_clk_div
);
755 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi
->lp_rx_timeout
);
756 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi
->turn_arnd_val
);
757 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi
->init_count
);
758 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi
->hs_to_lp_count
);
759 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi
->lp_byte_clk
);
760 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi
->bw_timer
);
761 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi
->clk_lp_to_hs_count
);
762 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi
->clk_hs_to_lp_count
);
763 DRM_DEBUG_KMS("BTA %s\n",
764 intel_dsi
->video_frmt_cfg_bits
& DISABLE_VIDEO_BTA
?
765 "disabled" : "enabled");
767 /* delays in VBT are in unit of 100us, so need to convert
769 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
770 intel_dsi
->backlight_off_delay
= pps
->bl_disable_delay
/ 10;
771 intel_dsi
->backlight_on_delay
= pps
->bl_enable_delay
/ 10;
772 intel_dsi
->panel_on_delay
= pps
->panel_on_delay
/ 10;
773 intel_dsi
->panel_off_delay
= pps
->panel_off_delay
/ 10;
774 intel_dsi
->panel_pwr_cycle_delay
= pps
->panel_power_cycle_delay
/ 10;
776 /* This is cheating a bit with the cleanup. */
777 vbt_panel
= devm_kzalloc(dev
->dev
, sizeof(*vbt_panel
), GFP_KERNEL
);
781 vbt_panel
->intel_dsi
= intel_dsi
;
782 drm_panel_init(&vbt_panel
->panel
);
783 vbt_panel
->panel
.funcs
= &vbt_panel_funcs
;
784 drm_panel_add(&vbt_panel
->panel
);
786 /* a regular driver would get the device in probe */
787 for_each_dsi_port(port
, intel_dsi
->ports
) {
788 mipi_dsi_attach(intel_dsi
->dsi_hosts
[port
]->device
);
791 return &vbt_panel
->panel
;