2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_ringbuffer.h"
27 #include "intel_lrc.h"
29 static const struct engine_info
{
35 int (*init_legacy
)(struct intel_engine_cs
*engine
);
36 int (*init_execlists
)(struct intel_engine_cs
*engine
);
39 .name
= "render ring",
40 .exec_id
= I915_EXEC_RENDER
,
41 .guc_id
= GUC_RENDER_ENGINE
,
42 .mmio_base
= RENDER_RING_BASE
,
43 .irq_shift
= GEN8_RCS_IRQ_SHIFT
,
44 .init_execlists
= logical_render_ring_init
,
45 .init_legacy
= intel_init_render_ring_buffer
,
48 .name
= "blitter ring",
49 .exec_id
= I915_EXEC_BLT
,
50 .guc_id
= GUC_BLITTER_ENGINE
,
51 .mmio_base
= BLT_RING_BASE
,
52 .irq_shift
= GEN8_BCS_IRQ_SHIFT
,
53 .init_execlists
= logical_xcs_ring_init
,
54 .init_legacy
= intel_init_blt_ring_buffer
,
58 .exec_id
= I915_EXEC_BSD
,
59 .guc_id
= GUC_VIDEO_ENGINE
,
60 .mmio_base
= GEN6_BSD_RING_BASE
,
61 .irq_shift
= GEN8_VCS1_IRQ_SHIFT
,
62 .init_execlists
= logical_xcs_ring_init
,
63 .init_legacy
= intel_init_bsd_ring_buffer
,
67 .exec_id
= I915_EXEC_BSD
,
68 .guc_id
= GUC_VIDEO_ENGINE2
,
69 .mmio_base
= GEN8_BSD2_RING_BASE
,
70 .irq_shift
= GEN8_VCS2_IRQ_SHIFT
,
71 .init_execlists
= logical_xcs_ring_init
,
72 .init_legacy
= intel_init_bsd2_ring_buffer
,
75 .name
= "video enhancement ring",
76 .exec_id
= I915_EXEC_VEBOX
,
77 .guc_id
= GUC_VIDEOENHANCE_ENGINE
,
78 .mmio_base
= VEBOX_RING_BASE
,
79 .irq_shift
= GEN8_VECS_IRQ_SHIFT
,
80 .init_execlists
= logical_xcs_ring_init
,
81 .init_legacy
= intel_init_vebox_ring_buffer
,
85 static struct intel_engine_cs
*
86 intel_engine_setup(struct drm_i915_private
*dev_priv
,
87 enum intel_engine_id id
)
89 const struct engine_info
*info
= &intel_engines
[id
];
90 struct intel_engine_cs
*engine
= &dev_priv
->engine
[id
];
93 engine
->i915
= dev_priv
;
94 engine
->name
= info
->name
;
95 engine
->exec_id
= info
->exec_id
;
96 engine
->hw_id
= engine
->guc_id
= info
->guc_id
;
97 engine
->mmio_base
= info
->mmio_base
;
98 engine
->irq_shift
= info
->irq_shift
;
104 * intel_engines_init() - allocate, populate and init the Engine Command Streamers
107 * Return: non-zero if the initialization failed.
109 int intel_engines_init(struct drm_device
*dev
)
111 struct drm_i915_private
*dev_priv
= to_i915(dev
);
112 unsigned int mask
= 0;
113 int (*init
)(struct intel_engine_cs
*engine
);
117 WARN_ON(INTEL_INFO(dev_priv
)->ring_mask
== 0);
118 WARN_ON(INTEL_INFO(dev_priv
)->ring_mask
&
119 GENMASK(sizeof(mask
) * BITS_PER_BYTE
- 1, I915_NUM_ENGINES
));
121 for (i
= 0; i
< ARRAY_SIZE(intel_engines
); i
++) {
122 if (!HAS_ENGINE(dev_priv
, i
))
125 if (i915
.enable_execlists
)
126 init
= intel_engines
[i
].init_execlists
;
128 init
= intel_engines
[i
].init_legacy
;
133 ret
= init(intel_engine_setup(dev_priv
, i
));
137 mask
|= ENGINE_MASK(i
);
141 * Catch failures to update intel_engines table when the new engines
142 * are added to the driver by a warning and disabling the forgotten
145 if (WARN_ON(mask
!= INTEL_INFO(dev_priv
)->ring_mask
)) {
146 struct intel_device_info
*info
=
147 (struct intel_device_info
*)&dev_priv
->info
;
148 info
->ring_mask
= mask
;
154 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
155 if (i915
.enable_execlists
)
156 intel_logical_ring_cleanup(&dev_priv
->engine
[i
]);
158 intel_cleanup_engine(&dev_priv
->engine
[i
]);
164 void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
)
166 memset(&engine
->hangcheck
, 0, sizeof(engine
->hangcheck
));
170 * intel_engines_setup_common - setup engine state not requiring hw access
171 * @engine: Engine to setup.
173 * Initializes @engine@ structure members shared between legacy and execlists
174 * submission modes which do not require hardware access.
176 * Typically done early in the submission mode specific engine setup stage.
178 void intel_engine_setup_common(struct intel_engine_cs
*engine
)
180 INIT_LIST_HEAD(&engine
->active_list
);
181 INIT_LIST_HEAD(&engine
->request_list
);
182 INIT_LIST_HEAD(&engine
->buffers
);
183 INIT_LIST_HEAD(&engine
->execlist_queue
);
184 spin_lock_init(&engine
->execlist_lock
);
186 engine
->fence_context
= fence_context_alloc(1);
188 intel_engine_init_hangcheck(engine
);
189 i915_gem_batch_pool_init(&engine
->i915
->drm
, &engine
->batch_pool
);
193 * intel_engines_init_common - initialize cengine state which might require hw access
194 * @engine: Engine to initialize.
196 * Initializes @engine@ structure members shared between legacy and execlists
197 * submission modes which do require hardware access.
199 * Typcally done at later stages of submission mode specific engine setup.
201 * Returns zero on success or an error code on failure.
203 int intel_engine_init_common(struct intel_engine_cs
*engine
)
207 ret
= intel_engine_init_breadcrumbs(engine
);
211 return intel_engine_init_cmd_parser(engine
);