drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return dev_priv->fbc.enable_fbc != NULL;
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;
  52 }
  53
  54 /*
  55  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  56  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  57  * origin so the x and y offsets can actually fit the registers. As a
  58  * consequence, the fence doesn't really start exactly at the display plane
  59  * address we program because it starts at the real start of the buffer, so we
  60  * have to take this into consideration here.
  61  */
  62 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
  63 {
  64         return crtc->base.y - crtc->adjusted_y;
  65 }
  66
  67 static void i8xx_fbc_disable(struct drm_i915_private *dev_priv)
  68 {
  69         u32 fbc_ctl;
  70
  71         dev_priv->fbc.enabled = false;
  72
  73         /* Disable compression */
  74         fbc_ctl = I915_READ(FBC_CONTROL);
  75         if ((fbc_ctl & FBC_CTL_EN) == 0)
  76                 return;
  77
  78         fbc_ctl &= ~FBC_CTL_EN;
  79         I915_WRITE(FBC_CONTROL, fbc_ctl);
  80
  81         /* Wait for compressing bit to clear */
  82         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  83                 DRM_DEBUG_KMS("FBC idle timed out\n");
  84                 return;
  85         }
  86
  87         DRM_DEBUG_KMS("disabled FBC\n");
  88 }
  89
  90 static void i8xx_fbc_enable(struct intel_crtc *crtc)
  91 {
  92         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  93         struct drm_framebuffer *fb = crtc->base.primary->fb;
  94         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  95         int cfb_pitch;
  96         int i;
  97         u32 fbc_ctl;
  98
  99         dev_priv->fbc.enabled = true;
 100
 101         /* Note: fbc.threshold == 1 for i8xx */
 102         cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE;
 103         if (fb->pitches[0] < cfb_pitch)
 104                 cfb_pitch = fb->pitches[0];
 105
 106         /* FBC_CTL wants 32B or 64B units */
 107         if (IS_GEN2(dev_priv))
 108                 cfb_pitch = (cfb_pitch / 32) - 1;
 109         else
 110                 cfb_pitch = (cfb_pitch / 64) - 1;
 111
 112         /* Clear old tags */
 113         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 114                 I915_WRITE(FBC_TAG(i), 0);
 115
 116         if (IS_GEN4(dev_priv)) {
 117                 u32 fbc_ctl2;
 118
 119                 /* Set it up... */
 120                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 121                 fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane);
 122                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 123                 I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc));
 124         }
 125
 126         /* enable it... */
 127         fbc_ctl = I915_READ(FBC_CONTROL);
 128         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 129         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 130         if (IS_I945GM(dev_priv))
 131                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 132         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 133         fbc_ctl |= obj->fence_reg;
 134         I915_WRITE(FBC_CONTROL, fbc_ctl);
 135
 136         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 137                       cfb_pitch, crtc->base.y, plane_name(crtc->plane));
 138 }
 139
 140 static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv)
 141 {
 142         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 143 }
 144
 145 static void g4x_fbc_enable(struct intel_crtc *crtc)
 146 {
 147         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 148         struct drm_framebuffer *fb = crtc->base.primary->fb;
 149         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 150         u32 dpfc_ctl;
 151
 152         dev_priv->fbc.enabled = true;
 153
 154         dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN;
 155         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 156                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 157         else
 158                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 159         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 160
 161         I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc));
 162
 163         /* enable it... */
 164         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 165
 166         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane));
 167 }
 168
 169 static void g4x_fbc_disable(struct drm_i915_private *dev_priv)
 170 {
 171         u32 dpfc_ctl;
 172
 173         dev_priv->fbc.enabled = false;
 174
 175         /* Disable compression */
 176         dpfc_ctl = I915_READ(DPFC_CONTROL);
 177         if (dpfc_ctl & DPFC_CTL_EN) {
 178                 dpfc_ctl &= ~DPFC_CTL_EN;
 179                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 180
 181                 DRM_DEBUG_KMS("disabled FBC\n");
 182         }
 183 }
 184
 185 static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv)
 186 {
 187         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 188 }
 189
 190 /* This function forces a CFB recompression through the nuke operation. */
 191 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 192 {
 193         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 194         POSTING_READ(MSG_FBC_REND_STATE);
 195 }
 196
 197 static void ilk_fbc_enable(struct intel_crtc *crtc)
 198 {
 199         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 200         struct drm_framebuffer *fb = crtc->base.primary->fb;
 201         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 202         u32 dpfc_ctl;
 203         int threshold = dev_priv->fbc.threshold;
 204         unsigned int y_offset;
 205
 206         dev_priv->fbc.enabled = true;
 207
 208         dpfc_ctl = DPFC_CTL_PLANE(crtc->plane);
 209         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 210                 threshold++;
 211
 212         switch (threshold) {
 213         case 4:
 214         case 3:
 215                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 216                 break;
 217         case 2:
 218                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 219                 break;
 220         case 1:
 221                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 222                 break;
 223         }
 224         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 225         if (IS_GEN5(dev_priv))
 226                 dpfc_ctl |= obj->fence_reg;
 227
 228         y_offset = get_crtc_fence_y_offset(crtc);
 229         I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset);
 230         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 231         /* enable it... */
 232         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 233
 234         if (IS_GEN6(dev_priv)) {
 235                 I915_WRITE(SNB_DPFC_CTL_SA,
 236                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 237                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset);
 238         }
 239
 240         intel_fbc_recompress(dev_priv);
 241
 242         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane));
 243 }
 244
 245 static void ilk_fbc_disable(struct drm_i915_private *dev_priv)
 246 {
 247         u32 dpfc_ctl;
 248
 249         dev_priv->fbc.enabled = false;
 250
 251         /* Disable compression */
 252         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 253         if (dpfc_ctl & DPFC_CTL_EN) {
 254                 dpfc_ctl &= ~DPFC_CTL_EN;
 255                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 256
 257                 DRM_DEBUG_KMS("disabled FBC\n");
 258         }
 259 }
 260
 261 static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv)
 262 {
 263         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 264 }
 265
 266 static void gen7_fbc_enable(struct intel_crtc *crtc)
 267 {
 268         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 269         struct drm_framebuffer *fb = crtc->base.primary->fb;
 270         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 271         u32 dpfc_ctl;
 272         int threshold = dev_priv->fbc.threshold;
 273
 274         dev_priv->fbc.enabled = true;
 275
 276         dpfc_ctl = 0;
 277         if (IS_IVYBRIDGE(dev_priv))
 278                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane);
 279
 280         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 281                 threshold++;
 282
 283         switch (threshold) {
 284         case 4:
 285         case 3:
 286                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 287                 break;
 288         case 2:
 289                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 290                 break;
 291         case 1:
 292                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 293                 break;
 294         }
 295
 296         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 297
 298         if (dev_priv->fbc.false_color)
 299                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 300
 301         if (IS_IVYBRIDGE(dev_priv)) {
 302                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 303                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 304                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 305                            ILK_FBCQ_DIS);
 306         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 307                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 308                 I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe),
 309                            I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) |
 310                            HSW_FBCQ_DIS);
 311         }
 312
 313         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 314
 315         I915_WRITE(SNB_DPFC_CTL_SA,
 316                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 317         I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc));
 318
 319         intel_fbc_recompress(dev_priv);
 320
 321         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane));
 322 }
 323
 324 /**
 325  * intel_fbc_enabled - Is FBC enabled?
 326  * @dev_priv: i915 device instance
 327  *
 328  * This function is used to verify the current state of FBC.
 329  * FIXME: This should be tracked in the plane config eventually
 330  *        instead of queried at runtime for most callers.
 331  */
 332 bool intel_fbc_enabled(struct drm_i915_private *dev_priv)
 333 {
 334         return dev_priv->fbc.enabled;
 335 }
 336
 337 static void intel_fbc_enable(struct intel_crtc *crtc,
 338                              const struct drm_framebuffer *fb)
 339 {
 340         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 341
 342         dev_priv->fbc.enable_fbc(crtc);
 343
 344         dev_priv->fbc.crtc = crtc;
 345         dev_priv->fbc.fb_id = fb->base.id;
 346         dev_priv->fbc.y = crtc->base.y;
 347 }
 348
 349 static void intel_fbc_work_fn(struct work_struct *__work)
 350 {
 351         struct intel_fbc_work *work =
 352                 container_of(to_delayed_work(__work),
 353                              struct intel_fbc_work, work);
 354         struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private;
 355         struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb;
 356
 357         mutex_lock(&dev_priv->fbc.lock);
 358         if (work == dev_priv->fbc.fbc_work) {
 359                 /* Double check that we haven't switched fb without cancelling
 360                  * the prior work.
 361                  */
 362                 if (crtc_fb == work->fb)
 363                         intel_fbc_enable(work->crtc, work->fb);
 364
 365                 dev_priv->fbc.fbc_work = NULL;
 366         }
 367         mutex_unlock(&dev_priv->fbc.lock);
 368
 369         kfree(work);
 370 }
 371
 372 static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv)
 373 {
 374         WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
 375
 376         if (dev_priv->fbc.fbc_work == NULL)
 377                 return;
 378
 379         /* Synchronisation is provided by struct_mutex and checking of
 380          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 381          * entirely asynchronously.
 382          */
 383         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 384                 /* tasklet was killed before being run, clean up */
 385                 kfree(dev_priv->fbc.fbc_work);
 386
 387         /* Mark the work as no longer wanted so that if it does
 388          * wake-up (because the work was already running and waiting
 389          * for our mutex), it will discover that is no longer
 390          * necessary to run.
 391          */
 392         dev_priv->fbc.fbc_work = NULL;
 393 }
 394
 395 static void intel_fbc_schedule_enable(struct intel_crtc *crtc)
 396 {
 397         struct intel_fbc_work *work;
 398         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 399
 400         WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
 401
 402         intel_fbc_cancel_work(dev_priv);
 403
 404         work = kzalloc(sizeof(*work), GFP_KERNEL);
 405         if (work == NULL) {
 406                 DRM_ERROR("Failed to allocate FBC work structure\n");
 407                 intel_fbc_enable(crtc, crtc->base.primary->fb);
 408                 return;
 409         }
 410
 411         work->crtc = crtc;
 412         work->fb = crtc->base.primary->fb;
 413         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 414
 415         dev_priv->fbc.fbc_work = work;
 416
 417         /* Delay the actual enabling to let pageflipping cease and the
 418          * display to settle before starting the compression. Note that
 419          * this delay also serves a second purpose: it allows for a
 420          * vblank to pass after disabling the FBC before we attempt
 421          * to modify the control registers.
 422          *
 423          * A more complicated solution would involve tracking vblanks
 424          * following the termination of the page-flipping sequence
 425          * and indeed performing the enable as a co-routine and not
 426          * waiting synchronously upon the vblank.
 427          *
 428          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 429          */
 430         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 431 }
 432
 433 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 434 {
 435         WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
 436
 437         intel_fbc_cancel_work(dev_priv);
 438
 439         if (dev_priv->fbc.enabled)
 440                 dev_priv->fbc.disable_fbc(dev_priv);
 441         dev_priv->fbc.crtc = NULL;
 442 }
 443
 444 /**
 445  * intel_fbc_disable - disable FBC
 446  * @dev_priv: i915 device instance
 447  *
 448  * This function disables FBC.
 449  */
 450 void intel_fbc_disable(struct drm_i915_private *dev_priv)
 451 {
 452         if (!fbc_supported(dev_priv))
 453                 return;
 454
 455         mutex_lock(&dev_priv->fbc.lock);
 456         __intel_fbc_disable(dev_priv);
 457         mutex_unlock(&dev_priv->fbc.lock);
 458 }
 459
 460 /*
 461  * intel_fbc_disable_crtc - disable FBC if it's associated with crtc
 462  * @crtc: the CRTC
 463  *
 464  * This function disables FBC if it's associated with the provided CRTC.
 465  */
 466 void intel_fbc_disable_crtc(struct intel_crtc *crtc)
 467 {
 468         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 469
 470         if (!fbc_supported(dev_priv))
 471                 return;
 472
 473         mutex_lock(&dev_priv->fbc.lock);
 474         if (dev_priv->fbc.crtc == crtc)
 475                 __intel_fbc_disable(dev_priv);
 476         mutex_unlock(&dev_priv->fbc.lock);
 477 }
 478
 479 static void set_no_fbc_reason(struct drm_i915_private *dev_priv,
 480                               const char *reason)
 481 {
 482         if (dev_priv->fbc.no_fbc_reason == reason)
 483                 return;
 484
 485         dev_priv->fbc.no_fbc_reason = reason;
 486         DRM_DEBUG_KMS("Disabling FBC: %s\n", reason);
 487 }
 488
 489 static bool crtc_is_valid(struct intel_crtc *crtc)
 490 {
 491         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 492
 493         if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
 494                 return false;
 495
 496         if (!intel_crtc_active(&crtc->base))
 497                 return false;
 498
 499         if (!to_intel_plane_state(crtc->base.primary->state)->visible)
 500                 return false;
 501
 502         return true;
 503 }
 504
 505 static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv)
 506 {
 507         struct drm_crtc *crtc = NULL, *tmp_crtc;
 508         enum pipe pipe;
 509
 510         for_each_pipe(dev_priv, pipe) {
 511                 tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 512
 513                 if (crtc_is_valid(to_intel_crtc(tmp_crtc)))
 514                         crtc = tmp_crtc;
 515         }
 516
 517         if (!crtc)
 518                 return NULL;
 519
 520         return crtc;
 521 }
 522
 523 static bool multiple_pipes_ok(struct drm_i915_private *dev_priv)
 524 {
 525         enum pipe pipe;
 526         int n_pipes = 0;
 527         struct drm_crtc *crtc;
 528
 529         if (INTEL_INFO(dev_priv)->gen > 4)
 530                 return true;
 531
 532         for_each_pipe(dev_priv, pipe) {
 533                 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 534
 535                 if (intel_crtc_active(crtc) &&
 536                     to_intel_plane_state(crtc->primary->state)->visible)
 537                         n_pipes++;
 538         }
 539
 540         return (n_pipes < 2);
 541 }
 542
 543 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 544                                       struct drm_mm_node *node,
 545                                       int size,
 546                                       int fb_cpp)
 547 {
 548         int compression_threshold = 1;
 549         int ret;
 550         u64 end;
 551
 552         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 553          * reserved range size, so it always assumes the maximum (8mb) is used.
 554          * If we enable FBC using a CFB on that memory range we'll get FIFO
 555          * underruns, even if that range is not reserved by the BIOS. */
 556         if (IS_BROADWELL(dev_priv) ||
 557             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 558                 end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024;
 559         else
 560                 end = dev_priv->gtt.stolen_usable_size;
 561
 562         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 563          * code changes, this code needs to change as well.
 564          *
 565          * The enable_fbc code will attempt to use one of our 2 compression
 566          * thresholds, therefore, in that case, we only have 1 resort.
 567          */
 568
 569         /* Try to over-allocate to reduce reallocations and fragmentation. */
 570         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 571                                                    4096, 0, end);
 572         if (ret == 0)
 573                 return compression_threshold;
 574
 575 again:
 576         /* HW's ability to limit the CFB is 1:4 */
 577         if (compression_threshold > 4 ||
 578             (fb_cpp == 2 && compression_threshold == 2))
 579                 return 0;
 580
 581         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 582                                                    4096, 0, end);
 583         if (ret && INTEL_INFO(dev_priv)->gen <= 4) {
 584                 return 0;
 585         } else if (ret) {
 586                 compression_threshold <<= 1;
 587                 goto again;
 588         } else {
 589                 return compression_threshold;
 590         }
 591 }
 592
 593 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size,
 594                                int fb_cpp)
 595 {
 596         struct drm_mm_node *uninitialized_var(compressed_llb);
 597         int ret;
 598
 599         ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb,
 600                                          size, fb_cpp);
 601         if (!ret)
 602                 goto err_llb;
 603         else if (ret > 1) {
 604                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 605
 606         }
 607
 608         dev_priv->fbc.threshold = ret;
 609
 610         if (INTEL_INFO(dev_priv)->gen >= 5)
 611                 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
 612         else if (IS_GM45(dev_priv)) {
 613                 I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
 614         } else {
 615                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 616                 if (!compressed_llb)
 617                         goto err_fb;
 618
 619                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 620                                                   4096, 4096);
 621                 if (ret)
 622                         goto err_fb;
 623
 624                 dev_priv->fbc.compressed_llb = compressed_llb;
 625
 626                 I915_WRITE(FBC_CFB_BASE,
 627                            dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start);
 628                 I915_WRITE(FBC_LL_BASE,
 629                            dev_priv->mm.stolen_base + compressed_llb->start);
 630         }
 631
 632         dev_priv->fbc.uncompressed_size = size;
 633
 634         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 635                       dev_priv->fbc.compressed_fb.size,
 636                       dev_priv->fbc.threshold);
 637
 638         return 0;
 639
 640 err_fb:
 641         kfree(compressed_llb);
 642         i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb);
 643 err_llb:
 644         pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 645         return -ENOSPC;
 646 }
 647
 648 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 649 {
 650         if (dev_priv->fbc.uncompressed_size == 0)
 651                 return;
 652
 653         i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb);
 654
 655         if (dev_priv->fbc.compressed_llb) {
 656                 i915_gem_stolen_remove_node(dev_priv,
 657                                             dev_priv->fbc.compressed_llb);
 658                 kfree(dev_priv->fbc.compressed_llb);
 659         }
 660
 661         dev_priv->fbc.uncompressed_size = 0;
 662 }
 663
 664 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 665 {
 666         if (!fbc_supported(dev_priv))
 667                 return;
 668
 669         mutex_lock(&dev_priv->fbc.lock);
 670         __intel_fbc_cleanup_cfb(dev_priv);
 671         mutex_unlock(&dev_priv->fbc.lock);
 672 }
 673
 674 /*
 675  * For SKL+, the plane source size used by the hardware is based on the value we
 676  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
 677  * we wrote to PIPESRC.
 678  */
 679 static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc,
 680                                             int *width, int *height)
 681 {
 682         struct intel_plane_state *plane_state =
 683                         to_intel_plane_state(crtc->base.primary->state);
 684         int w, h;
 685
 686         if (intel_rotation_90_or_270(plane_state->base.rotation)) {
 687                 w = drm_rect_height(&plane_state->src) >> 16;
 688                 h = drm_rect_width(&plane_state->src) >> 16;
 689         } else {
 690                 w = drm_rect_width(&plane_state->src) >> 16;
 691                 h = drm_rect_height(&plane_state->src) >> 16;
 692         }
 693
 694         if (width)
 695                 *width = w;
 696         if (height)
 697                 *height = h;
 698 }
 699
 700 static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc)
 701 {
 702         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 703         struct drm_framebuffer *fb = crtc->base.primary->fb;
 704         int lines;
 705
 706         intel_fbc_get_plane_source_size(crtc, NULL, &lines);
 707         if (INTEL_INFO(dev_priv)->gen >= 7)
 708                 lines = min(lines, 2048);
 709
 710         /* Hardware needs the full buffer stride, not just the active area. */
 711         return lines * fb->pitches[0];
 712 }
 713
 714 static int intel_fbc_setup_cfb(struct intel_crtc *crtc)
 715 {
 716         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 717         struct drm_framebuffer *fb = crtc->base.primary->fb;
 718         int size, cpp;
 719
 720         size = intel_fbc_calculate_cfb_size(crtc);
 721         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 722
 723         if (size <= dev_priv->fbc.uncompressed_size)
 724                 return 0;
 725
 726         /* Release any current block */
 727         __intel_fbc_cleanup_cfb(dev_priv);
 728
 729         return intel_fbc_alloc_cfb(dev_priv, size, cpp);
 730 }
 731
 732 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 733                             unsigned int stride)
 734 {
 735         /* These should have been caught earlier. */
 736         WARN_ON(stride < 512);
 737         WARN_ON((stride & (64 - 1)) != 0);
 738
 739         /* Below are the additional FBC restrictions. */
 740
 741         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 742                 return stride == 4096 || stride == 8192;
 743
 744         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 745                 return false;
 746
 747         if (stride > 16384)
 748                 return false;
 749
 750         return true;
 751 }
 752
 753 static bool pixel_format_is_valid(struct drm_framebuffer *fb)
 754 {
 755         struct drm_device *dev = fb->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757
 758         switch (fb->pixel_format) {
 759         case DRM_FORMAT_XRGB8888:
 760         case DRM_FORMAT_XBGR8888:
 761                 return true;
 762         case DRM_FORMAT_XRGB1555:
 763         case DRM_FORMAT_RGB565:
 764                 /* 16bpp not supported on gen2 */
 765                 if (IS_GEN2(dev))
 766                         return false;
 767                 /* WaFbcOnly1to1Ratio:ctg */
 768                 if (IS_G4X(dev_priv))
 769                         return false;
 770                 return true;
 771         default:
 772                 return false;
 773         }
 774 }
 775
 776 /*
 777  * For some reason, the hardware tracking starts looking at whatever we
 778  * programmed as the display plane base address register. It does not look at
 779  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 780  * variables instead of just looking at the pipe/plane size.
 781  */
 782 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 783 {
 784         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 785         unsigned int effective_w, effective_h, max_w, max_h;
 786
 787         if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) {
 788                 max_w = 4096;
 789                 max_h = 4096;
 790         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
 791                 max_w = 4096;
 792                 max_h = 2048;
 793         } else {
 794                 max_w = 2048;
 795                 max_h = 1536;
 796         }
 797
 798         intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h);
 799         effective_w += crtc->adjusted_x;
 800         effective_h += crtc->adjusted_y;
 801
 802         return effective_w <= max_w && effective_h <= max_h;
 803 }
 804
 805 /**
 806  * __intel_fbc_update - enable/disable FBC as needed, unlocked
 807  * @dev_priv: i915 device instance
 808  *
 809  * This function completely reevaluates the status of FBC, then enables,
 810  * disables or maintains it on the same state.
 811  */
 812 static void __intel_fbc_update(struct drm_i915_private *dev_priv)
 813 {
 814         struct drm_crtc *drm_crtc = NULL;
 815         struct intel_crtc *crtc;
 816         struct drm_framebuffer *fb;
 817         struct drm_i915_gem_object *obj;
 818         const struct drm_display_mode *adjusted_mode;
 819
 820         WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
 821
 822         if (intel_vgpu_active(dev_priv->dev))
 823                 i915.enable_fbc = 0;
 824
 825         if (i915.enable_fbc < 0) {
 826                 set_no_fbc_reason(dev_priv, "disabled per chip default");
 827                 goto out_disable;
 828         }
 829
 830         if (!i915.enable_fbc) {
 831                 set_no_fbc_reason(dev_priv, "disabled per module param");
 832                 goto out_disable;
 833         }
 834
 835         drm_crtc = intel_fbc_find_crtc(dev_priv);
 836         if (!drm_crtc) {
 837                 set_no_fbc_reason(dev_priv, "no output");
 838                 goto out_disable;
 839         }
 840
 841         if (!multiple_pipes_ok(dev_priv)) {
 842                 set_no_fbc_reason(dev_priv, "more than one pipe active");
 843                 goto out_disable;
 844         }
 845
 846         crtc = to_intel_crtc(drm_crtc);
 847         fb = crtc->base.primary->fb;
 848         obj = intel_fb_obj(fb);
 849         adjusted_mode = &crtc->config->base.adjusted_mode;
 850
 851         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 852             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 853                 set_no_fbc_reason(dev_priv, "incompatible mode");
 854                 goto out_disable;
 855         }
 856
 857         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 858                 set_no_fbc_reason(dev_priv, "mode too large for compression");
 859                 goto out_disable;
 860         }
 861
 862         if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) &&
 863             crtc->plane != PLANE_A) {
 864                 set_no_fbc_reason(dev_priv, "FBC unsupported on plane");
 865                 goto out_disable;
 866         }
 867
 868         /* The use of a CPU fence is mandatory in order to detect writes
 869          * by the CPU to the scanout and trigger updates to the FBC.
 870          */
 871         if (obj->tiling_mode != I915_TILING_X ||
 872             obj->fence_reg == I915_FENCE_REG_NONE) {
 873                 set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced");
 874                 goto out_disable;
 875         }
 876         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
 877             crtc->base.primary->state->rotation != BIT(DRM_ROTATE_0)) {
 878                 set_no_fbc_reason(dev_priv, "rotation unsupported");
 879                 goto out_disable;
 880         }
 881
 882         if (!stride_is_valid(dev_priv, fb->pitches[0])) {
 883                 set_no_fbc_reason(dev_priv, "framebuffer stride not supported");
 884                 goto out_disable;
 885         }
 886
 887         if (!pixel_format_is_valid(fb)) {
 888                 set_no_fbc_reason(dev_priv, "pixel format is invalid");
 889                 goto out_disable;
 890         }
 891
 892         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 893         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 894             ilk_pipe_pixel_rate(crtc->config) >=
 895             dev_priv->cdclk_freq * 95 / 100) {
 896                 set_no_fbc_reason(dev_priv, "pixel rate is too big");
 897                 goto out_disable;
 898         }
 899
 900         if (intel_fbc_setup_cfb(crtc)) {
 901                 set_no_fbc_reason(dev_priv, "not enough stolen memory");
 902                 goto out_disable;
 903         }
 904
 905         /* If the scanout has not changed, don't modify the FBC settings.
 906          * Note that we make the fundamental assumption that the fb->obj
 907          * cannot be unpinned (and have its GTT offset and fence revoked)
 908          * without first being decoupled from the scanout and FBC disabled.
 909          */
 910         if (dev_priv->fbc.crtc == crtc &&
 911             dev_priv->fbc.fb_id == fb->base.id &&
 912             dev_priv->fbc.y == crtc->base.y)
 913                 return;
 914
 915         if (intel_fbc_enabled(dev_priv)) {
 916                 /* We update FBC along two paths, after changing fb/crtc
 917                  * configuration (modeswitching) and after page-flipping
 918                  * finishes. For the latter, we know that not only did
 919                  * we disable the FBC at the start of the page-flip
 920                  * sequence, but also more than one vblank has passed.
 921                  *
 922                  * For the former case of modeswitching, it is possible
 923                  * to switch between two FBC valid configurations
 924                  * instantaneously so we do need to disable the FBC
 925                  * before we can modify its control registers. We also
 926                  * have to wait for the next vblank for that to take
 927                  * effect. However, since we delay enabling FBC we can
 928                  * assume that a vblank has passed since disabling and
 929                  * that we can safely alter the registers in the deferred
 930                  * callback.
 931                  *
 932                  * In the scenario that we go from a valid to invalid
 933                  * and then back to valid FBC configuration we have
 934                  * no strict enforcement that a vblank occurred since
 935                  * disabling the FBC. However, along all current pipe
 936                  * disabling paths we do need to wait for a vblank at
 937                  * some point. And we wait before enabling FBC anyway.
 938                  */
 939                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 940                 __intel_fbc_disable(dev_priv);
 941         }
 942
 943         intel_fbc_schedule_enable(crtc);
 944         dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)";
 945         return;
 946
 947 out_disable:
 948         /* Multiple disables should be harmless */
 949         if (intel_fbc_enabled(dev_priv)) {
 950                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 951                 __intel_fbc_disable(dev_priv);
 952         }
 953         __intel_fbc_cleanup_cfb(dev_priv);
 954 }
 955
 956 /*
 957  * intel_fbc_update - enable/disable FBC as needed
 958  * @dev_priv: i915 device instance
 959  *
 960  * This function reevaluates the overall state and enables or disables FBC.
 961  */
 962 void intel_fbc_update(struct drm_i915_private *dev_priv)
 963 {
 964         if (!fbc_supported(dev_priv))
 965                 return;
 966
 967         mutex_lock(&dev_priv->fbc.lock);
 968         __intel_fbc_update(dev_priv);
 969         mutex_unlock(&dev_priv->fbc.lock);
 970 }
 971
 972 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 973                           unsigned int frontbuffer_bits,
 974                           enum fb_op_origin origin)
 975 {
 976         unsigned int fbc_bits;
 977
 978         if (!fbc_supported(dev_priv))
 979                 return;
 980
 981         if (origin == ORIGIN_GTT)
 982                 return;
 983
 984         mutex_lock(&dev_priv->fbc.lock);
 985
 986         if (dev_priv->fbc.enabled)
 987                 fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe);
 988         else if (dev_priv->fbc.fbc_work)
 989                 fbc_bits = INTEL_FRONTBUFFER_PRIMARY(
 990                                         dev_priv->fbc.fbc_work->crtc->pipe);
 991         else
 992                 fbc_bits = dev_priv->fbc.possible_framebuffer_bits;
 993
 994         dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits);
 995
 996         if (dev_priv->fbc.busy_bits)
 997                 __intel_fbc_disable(dev_priv);
 998
 999         mutex_unlock(&dev_priv->fbc.lock);
1000 }
1001
1002 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1003                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1004 {
1005         if (!fbc_supported(dev_priv))
1006                 return;
1007
1008         if (origin == ORIGIN_GTT)
1009                 return;
1010
1011         mutex_lock(&dev_priv->fbc.lock);
1012
1013         dev_priv->fbc.busy_bits &= ~frontbuffer_bits;
1014
1015         if (!dev_priv->fbc.busy_bits) {
1016                 __intel_fbc_disable(dev_priv);
1017                 __intel_fbc_update(dev_priv);
1018         }
1019
1020         mutex_unlock(&dev_priv->fbc.lock);
1021 }
1022
1023 /**
1024  * intel_fbc_init - Initialize FBC
1025  * @dev_priv: the i915 device
1026  *
1027  * This function might be called during PM init process.
1028  */
1029 void intel_fbc_init(struct drm_i915_private *dev_priv)
1030 {
1031         enum pipe pipe;
1032
1033         mutex_init(&dev_priv->fbc.lock);
1034         dev_priv->fbc.enabled = false;
1035
1036         if (!HAS_FBC(dev_priv)) {
1037                 dev_priv->fbc.no_fbc_reason = "unsupported by this chipset";
1038                 return;
1039         }
1040
1041         for_each_pipe(dev_priv, pipe) {
1042                 dev_priv->fbc.possible_framebuffer_bits |=
1043                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1044
1045                 if (fbc_on_pipe_a_only(dev_priv))
1046                         break;
1047         }
1048
1049         if (INTEL_INFO(dev_priv)->gen >= 7) {
1050                 dev_priv->fbc.fbc_enabled = ilk_fbc_enabled;
1051                 dev_priv->fbc.enable_fbc = gen7_fbc_enable;
1052                 dev_priv->fbc.disable_fbc = ilk_fbc_disable;
1053         } else if (INTEL_INFO(dev_priv)->gen >= 5) {
1054                 dev_priv->fbc.fbc_enabled = ilk_fbc_enabled;
1055                 dev_priv->fbc.enable_fbc = ilk_fbc_enable;
1056                 dev_priv->fbc.disable_fbc = ilk_fbc_disable;
1057         } else if (IS_GM45(dev_priv)) {
1058                 dev_priv->fbc.fbc_enabled = g4x_fbc_enabled;
1059                 dev_priv->fbc.enable_fbc = g4x_fbc_enable;
1060                 dev_priv->fbc.disable_fbc = g4x_fbc_disable;
1061         } else {
1062                 dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled;
1063                 dev_priv->fbc.enable_fbc = i8xx_fbc_enable;
1064                 dev_priv->fbc.disable_fbc = i8xx_fbc_disable;
1065
1066                 /* This value was pulled out of someone's hat */
1067                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1068         }
1069
1070         /* We still don't have any sort of hardware state readout for FBC, so
1071          * disable it in case the BIOS enabled it to make sure software matches
1072          * the hardware state. */
1073         if (dev_priv->fbc.fbc_enabled(dev_priv))
1074                 dev_priv->fbc.disable_fbc(dev_priv);
1075 }