2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Frame Buffer Compression (FBC)
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
41 #include "intel_drv.h"
44 static inline bool fbc_supported(struct drm_i915_private
*dev_priv
)
46 return dev_priv
->fbc
.enable_fbc
!= NULL
;
50 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
51 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
52 * origin so the x and y offsets can actually fit the registers. As a
53 * consequence, the fence doesn't really start exactly at the display plane
54 * address we program because it starts at the real start of the buffer, so we
55 * have to take this into consideration here.
57 static unsigned int get_crtc_fence_y_offset(struct intel_crtc
*crtc
)
59 return crtc
->base
.y
- crtc
->adjusted_y
;
62 static void i8xx_fbc_disable(struct drm_i915_private
*dev_priv
)
66 dev_priv
->fbc
.enabled
= false;
68 /* Disable compression */
69 fbc_ctl
= I915_READ(FBC_CONTROL
);
70 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
73 fbc_ctl
&= ~FBC_CTL_EN
;
74 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
76 /* Wait for compressing bit to clear */
77 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
78 DRM_DEBUG_KMS("FBC idle timed out\n");
82 DRM_DEBUG_KMS("disabled FBC\n");
85 static void i8xx_fbc_enable(struct intel_crtc
*crtc
)
87 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
88 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
89 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
94 dev_priv
->fbc
.enabled
= true;
96 /* Note: fbc.threshold == 1 for i8xx */
97 cfb_pitch
= dev_priv
->fbc
.uncompressed_size
/ FBC_LL_SIZE
;
98 if (fb
->pitches
[0] < cfb_pitch
)
99 cfb_pitch
= fb
->pitches
[0];
101 /* FBC_CTL wants 32B or 64B units */
102 if (IS_GEN2(dev_priv
))
103 cfb_pitch
= (cfb_pitch
/ 32) - 1;
105 cfb_pitch
= (cfb_pitch
/ 64) - 1;
108 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
109 I915_WRITE(FBC_TAG(i
), 0);
111 if (IS_GEN4(dev_priv
)) {
115 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
116 fbc_ctl2
|= FBC_CTL_PLANE(crtc
->plane
);
117 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
118 I915_WRITE(FBC_FENCE_OFF
, get_crtc_fence_y_offset(crtc
));
122 fbc_ctl
= I915_READ(FBC_CONTROL
);
123 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
124 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
125 if (IS_I945GM(dev_priv
))
126 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
127 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
128 fbc_ctl
|= obj
->fence_reg
;
129 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
131 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
132 cfb_pitch
, crtc
->base
.y
, plane_name(crtc
->plane
));
135 static bool i8xx_fbc_enabled(struct drm_i915_private
*dev_priv
)
137 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
140 static void g4x_fbc_enable(struct intel_crtc
*crtc
)
142 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
143 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
144 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
147 dev_priv
->fbc
.enabled
= true;
149 dpfc_ctl
= DPFC_CTL_PLANE(crtc
->plane
) | DPFC_SR_EN
;
150 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
151 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
153 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
154 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
156 I915_WRITE(DPFC_FENCE_YOFF
, get_crtc_fence_y_offset(crtc
));
159 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
161 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
164 static void g4x_fbc_disable(struct drm_i915_private
*dev_priv
)
168 dev_priv
->fbc
.enabled
= false;
170 /* Disable compression */
171 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
172 if (dpfc_ctl
& DPFC_CTL_EN
) {
173 dpfc_ctl
&= ~DPFC_CTL_EN
;
174 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
176 DRM_DEBUG_KMS("disabled FBC\n");
180 static bool g4x_fbc_enabled(struct drm_i915_private
*dev_priv
)
182 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
185 static void intel_fbc_nuke(struct drm_i915_private
*dev_priv
)
187 I915_WRITE(MSG_FBC_REND_STATE
, FBC_REND_NUKE
);
188 POSTING_READ(MSG_FBC_REND_STATE
);
191 static void ilk_fbc_enable(struct intel_crtc
*crtc
)
193 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
194 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
195 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
197 int threshold
= dev_priv
->fbc
.threshold
;
198 unsigned int y_offset
;
200 dev_priv
->fbc
.enabled
= true;
202 dpfc_ctl
= DPFC_CTL_PLANE(crtc
->plane
);
203 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
209 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
212 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
215 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
218 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
219 if (IS_GEN5(dev_priv
))
220 dpfc_ctl
|= obj
->fence_reg
;
222 y_offset
= get_crtc_fence_y_offset(crtc
);
223 I915_WRITE(ILK_DPFC_FENCE_YOFF
, y_offset
);
224 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
226 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
228 if (IS_GEN6(dev_priv
)) {
229 I915_WRITE(SNB_DPFC_CTL_SA
,
230 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
231 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, y_offset
);
234 intel_fbc_nuke(dev_priv
);
236 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
239 static void ilk_fbc_disable(struct drm_i915_private
*dev_priv
)
243 dev_priv
->fbc
.enabled
= false;
245 /* Disable compression */
246 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
247 if (dpfc_ctl
& DPFC_CTL_EN
) {
248 dpfc_ctl
&= ~DPFC_CTL_EN
;
249 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
251 DRM_DEBUG_KMS("disabled FBC\n");
255 static bool ilk_fbc_enabled(struct drm_i915_private
*dev_priv
)
257 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
260 static void gen7_fbc_enable(struct intel_crtc
*crtc
)
262 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
263 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
264 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
266 int threshold
= dev_priv
->fbc
.threshold
;
268 dev_priv
->fbc
.enabled
= true;
271 if (IS_IVYBRIDGE(dev_priv
))
272 dpfc_ctl
|= IVB_DPFC_CTL_PLANE(crtc
->plane
);
274 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
280 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
283 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
286 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
290 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
292 if (dev_priv
->fbc
.false_color
)
293 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
295 if (IS_IVYBRIDGE(dev_priv
)) {
296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
297 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
298 I915_READ(ILK_DISPLAY_CHICKEN1
) |
300 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
302 I915_WRITE(CHICKEN_PIPESL_1(crtc
->pipe
),
303 I915_READ(CHICKEN_PIPESL_1(crtc
->pipe
)) |
307 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
309 I915_WRITE(SNB_DPFC_CTL_SA
,
310 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
311 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, get_crtc_fence_y_offset(crtc
));
313 intel_fbc_nuke(dev_priv
);
315 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
319 * intel_fbc_enabled - Is FBC enabled?
320 * @dev_priv: i915 device instance
322 * This function is used to verify the current state of FBC.
323 * FIXME: This should be tracked in the plane config eventually
324 * instead of queried at runtime for most callers.
326 bool intel_fbc_enabled(struct drm_i915_private
*dev_priv
)
328 return dev_priv
->fbc
.enabled
;
331 static void intel_fbc_enable(struct intel_crtc
*crtc
,
332 const struct drm_framebuffer
*fb
)
334 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
336 dev_priv
->fbc
.enable_fbc(crtc
);
338 dev_priv
->fbc
.crtc
= crtc
;
339 dev_priv
->fbc
.fb_id
= fb
->base
.id
;
340 dev_priv
->fbc
.y
= crtc
->base
.y
;
343 static void intel_fbc_work_fn(struct work_struct
*__work
)
345 struct intel_fbc_work
*work
=
346 container_of(to_delayed_work(__work
),
347 struct intel_fbc_work
, work
);
348 struct drm_i915_private
*dev_priv
= work
->crtc
->base
.dev
->dev_private
;
349 struct drm_framebuffer
*crtc_fb
= work
->crtc
->base
.primary
->fb
;
351 mutex_lock(&dev_priv
->fbc
.lock
);
352 if (work
== dev_priv
->fbc
.fbc_work
) {
353 /* Double check that we haven't switched fb without cancelling
356 if (crtc_fb
== work
->fb
)
357 intel_fbc_enable(work
->crtc
, work
->fb
);
359 dev_priv
->fbc
.fbc_work
= NULL
;
361 mutex_unlock(&dev_priv
->fbc
.lock
);
366 static void intel_fbc_cancel_work(struct drm_i915_private
*dev_priv
)
368 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
370 if (dev_priv
->fbc
.fbc_work
== NULL
)
373 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
375 /* Synchronisation is provided by struct_mutex and checking of
376 * dev_priv->fbc.fbc_work, so we can perform the cancellation
377 * entirely asynchronously.
379 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
380 /* tasklet was killed before being run, clean up */
381 kfree(dev_priv
->fbc
.fbc_work
);
383 /* Mark the work as no longer wanted so that if it does
384 * wake-up (because the work was already running and waiting
385 * for our mutex), it will discover that is no longer
388 dev_priv
->fbc
.fbc_work
= NULL
;
391 static void intel_fbc_schedule_enable(struct intel_crtc
*crtc
)
393 struct intel_fbc_work
*work
;
394 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
396 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
398 intel_fbc_cancel_work(dev_priv
);
400 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
402 DRM_ERROR("Failed to allocate FBC work structure\n");
403 intel_fbc_enable(crtc
, crtc
->base
.primary
->fb
);
408 work
->fb
= crtc
->base
.primary
->fb
;
409 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
411 dev_priv
->fbc
.fbc_work
= work
;
413 /* Delay the actual enabling to let pageflipping cease and the
414 * display to settle before starting the compression. Note that
415 * this delay also serves a second purpose: it allows for a
416 * vblank to pass after disabling the FBC before we attempt
417 * to modify the control registers.
419 * A more complicated solution would involve tracking vblanks
420 * following the termination of the page-flipping sequence
421 * and indeed performing the enable as a co-routine and not
422 * waiting synchronously upon the vblank.
424 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
426 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
429 static void __intel_fbc_disable(struct drm_i915_private
*dev_priv
)
431 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
433 intel_fbc_cancel_work(dev_priv
);
435 dev_priv
->fbc
.disable_fbc(dev_priv
);
436 dev_priv
->fbc
.crtc
= NULL
;
440 * intel_fbc_disable - disable FBC
441 * @dev_priv: i915 device instance
443 * This function disables FBC.
445 void intel_fbc_disable(struct drm_i915_private
*dev_priv
)
447 if (!fbc_supported(dev_priv
))
450 mutex_lock(&dev_priv
->fbc
.lock
);
451 __intel_fbc_disable(dev_priv
);
452 mutex_unlock(&dev_priv
->fbc
.lock
);
456 * intel_fbc_disable_crtc - disable FBC if it's associated with crtc
459 * This function disables FBC if it's associated with the provided CRTC.
461 void intel_fbc_disable_crtc(struct intel_crtc
*crtc
)
463 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
465 if (!fbc_supported(dev_priv
))
468 mutex_lock(&dev_priv
->fbc
.lock
);
469 if (dev_priv
->fbc
.crtc
== crtc
)
470 __intel_fbc_disable(dev_priv
);
471 mutex_unlock(&dev_priv
->fbc
.lock
);
474 static void set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
477 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
480 dev_priv
->fbc
.no_fbc_reason
= reason
;
481 DRM_DEBUG_KMS("Disabling FBC: %s\n", reason
);
484 static struct drm_crtc
*intel_fbc_find_crtc(struct drm_i915_private
*dev_priv
)
486 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
488 bool pipe_a_only
= false;
490 if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)
493 for_each_pipe(dev_priv
, pipe
) {
494 tmp_crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
496 if (intel_crtc_active(tmp_crtc
) &&
497 to_intel_plane_state(tmp_crtc
->primary
->state
)->visible
)
504 if (!crtc
|| crtc
->primary
->fb
== NULL
)
510 static bool multiple_pipes_ok(struct drm_i915_private
*dev_priv
)
514 struct drm_crtc
*crtc
;
516 if (INTEL_INFO(dev_priv
)->gen
> 4)
519 for_each_pipe(dev_priv
, pipe
) {
520 crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
522 if (intel_crtc_active(crtc
) &&
523 to_intel_plane_state(crtc
->primary
->state
)->visible
)
527 return (n_pipes
< 2);
530 static int find_compression_threshold(struct drm_i915_private
*dev_priv
,
531 struct drm_mm_node
*node
,
535 int compression_threshold
= 1;
539 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
540 * reserved range size, so it always assumes the maximum (8mb) is used.
541 * If we enable FBC using a CFB on that memory range we'll get FIFO
542 * underruns, even if that range is not reserved by the BIOS. */
543 if (IS_BROADWELL(dev_priv
) ||
544 IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
545 end
= dev_priv
->gtt
.stolen_size
- 8 * 1024 * 1024;
547 end
= dev_priv
->gtt
.stolen_usable_size
;
549 /* HACK: This code depends on what we will do in *_enable_fbc. If that
550 * code changes, this code needs to change as well.
552 * The enable_fbc code will attempt to use one of our 2 compression
553 * thresholds, therefore, in that case, we only have 1 resort.
556 /* Try to over-allocate to reduce reallocations and fragmentation. */
557 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
<<= 1,
560 return compression_threshold
;
563 /* HW's ability to limit the CFB is 1:4 */
564 if (compression_threshold
> 4 ||
565 (fb_cpp
== 2 && compression_threshold
== 2))
568 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
>>= 1,
570 if (ret
&& INTEL_INFO(dev_priv
)->gen
<= 4) {
573 compression_threshold
<<= 1;
576 return compression_threshold
;
580 static int intel_fbc_alloc_cfb(struct drm_i915_private
*dev_priv
, int size
,
583 struct drm_mm_node
*uninitialized_var(compressed_llb
);
586 ret
= find_compression_threshold(dev_priv
, &dev_priv
->fbc
.compressed_fb
,
591 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
595 dev_priv
->fbc
.threshold
= ret
;
597 if (INTEL_INFO(dev_priv
)->gen
>= 5)
598 I915_WRITE(ILK_DPFC_CB_BASE
, dev_priv
->fbc
.compressed_fb
.start
);
599 else if (IS_GM45(dev_priv
)) {
600 I915_WRITE(DPFC_CB_BASE
, dev_priv
->fbc
.compressed_fb
.start
);
602 compressed_llb
= kzalloc(sizeof(*compressed_llb
), GFP_KERNEL
);
606 ret
= i915_gem_stolen_insert_node(dev_priv
, compressed_llb
,
611 dev_priv
->fbc
.compressed_llb
= compressed_llb
;
613 I915_WRITE(FBC_CFB_BASE
,
614 dev_priv
->mm
.stolen_base
+ dev_priv
->fbc
.compressed_fb
.start
);
615 I915_WRITE(FBC_LL_BASE
,
616 dev_priv
->mm
.stolen_base
+ compressed_llb
->start
);
619 dev_priv
->fbc
.uncompressed_size
= size
;
621 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
622 dev_priv
->fbc
.compressed_fb
.size
,
623 dev_priv
->fbc
.threshold
);
628 kfree(compressed_llb
);
629 i915_gem_stolen_remove_node(dev_priv
, &dev_priv
->fbc
.compressed_fb
);
631 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size
);
635 static void __intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
637 if (dev_priv
->fbc
.uncompressed_size
== 0)
640 i915_gem_stolen_remove_node(dev_priv
, &dev_priv
->fbc
.compressed_fb
);
642 if (dev_priv
->fbc
.compressed_llb
) {
643 i915_gem_stolen_remove_node(dev_priv
,
644 dev_priv
->fbc
.compressed_llb
);
645 kfree(dev_priv
->fbc
.compressed_llb
);
648 dev_priv
->fbc
.uncompressed_size
= 0;
651 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
653 if (!fbc_supported(dev_priv
))
656 mutex_lock(&dev_priv
->fbc
.lock
);
657 __intel_fbc_cleanup_cfb(dev_priv
);
658 mutex_unlock(&dev_priv
->fbc
.lock
);
662 * For SKL+, the plane source size used by the hardware is based on the value we
663 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
664 * we wrote to PIPESRC.
666 static void intel_fbc_get_plane_source_size(struct intel_crtc
*crtc
,
667 int *width
, int *height
)
669 struct intel_plane_state
*plane_state
=
670 to_intel_plane_state(crtc
->base
.primary
->state
);
673 if (intel_rotation_90_or_270(plane_state
->base
.rotation
)) {
674 w
= drm_rect_height(&plane_state
->src
) >> 16;
675 h
= drm_rect_width(&plane_state
->src
) >> 16;
677 w
= drm_rect_width(&plane_state
->src
) >> 16;
678 h
= drm_rect_height(&plane_state
->src
) >> 16;
687 static int intel_fbc_calculate_cfb_size(struct intel_crtc
*crtc
)
689 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
690 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
693 intel_fbc_get_plane_source_size(crtc
, NULL
, &lines
);
694 if (INTEL_INFO(dev_priv
)->gen
>= 7)
695 lines
= min(lines
, 2048);
697 return lines
* fb
->pitches
[0];
700 static int intel_fbc_setup_cfb(struct intel_crtc
*crtc
)
702 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
703 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
706 size
= intel_fbc_calculate_cfb_size(crtc
);
707 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
709 if (size
<= dev_priv
->fbc
.uncompressed_size
)
712 /* Release any current block */
713 __intel_fbc_cleanup_cfb(dev_priv
);
715 return intel_fbc_alloc_cfb(dev_priv
, size
, cpp
);
718 static bool stride_is_valid(struct drm_i915_private
*dev_priv
,
721 /* These should have been caught earlier. */
722 WARN_ON(stride
< 512);
723 WARN_ON((stride
& (64 - 1)) != 0);
725 /* Below are the additional FBC restrictions. */
727 if (IS_GEN2(dev_priv
) || IS_GEN3(dev_priv
))
728 return stride
== 4096 || stride
== 8192;
730 if (IS_GEN4(dev_priv
) && !IS_G4X(dev_priv
) && stride
< 2048)
739 static bool pixel_format_is_valid(struct drm_framebuffer
*fb
)
741 struct drm_device
*dev
= fb
->dev
;
742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
744 switch (fb
->pixel_format
) {
745 case DRM_FORMAT_XRGB8888
:
746 case DRM_FORMAT_XBGR8888
:
748 case DRM_FORMAT_XRGB1555
:
749 case DRM_FORMAT_RGB565
:
750 /* 16bpp not supported on gen2 */
753 /* WaFbcOnly1to1Ratio:ctg */
754 if (IS_G4X(dev_priv
))
763 * For some reason, the hardware tracking starts looking at whatever we
764 * programmed as the display plane base address register. It does not look at
765 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
766 * variables instead of just looking at the pipe/plane size.
768 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc
*crtc
)
770 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
771 unsigned int effective_w
, effective_h
, max_w
, max_h
;
773 if (INTEL_INFO(dev_priv
)->gen
>= 8 || IS_HASWELL(dev_priv
)) {
776 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
784 intel_fbc_get_plane_source_size(crtc
, &effective_w
, &effective_h
);
785 effective_w
+= crtc
->adjusted_x
;
786 effective_h
+= crtc
->adjusted_y
;
788 return effective_w
<= max_w
&& effective_h
<= max_h
;
792 * __intel_fbc_update - enable/disable FBC as needed, unlocked
793 * @dev_priv: i915 device instance
795 * Set up the framebuffer compression hardware at mode set time. We
796 * enable it if possible:
797 * - plane A only (on pre-965)
798 * - no pixel mulitply/line duplication
799 * - no alpha buffer discard
801 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
803 * We can't assume that any compression will take place (worst case),
804 * so the compressed buffer has to be the same size as the uncompressed
805 * one. It also must reside (along with the line length buffer) in
808 * We need to enable/disable FBC on a global basis.
810 static void __intel_fbc_update(struct drm_i915_private
*dev_priv
)
812 struct drm_crtc
*crtc
= NULL
;
813 struct intel_crtc
*intel_crtc
;
814 struct drm_framebuffer
*fb
;
815 struct drm_i915_gem_object
*obj
;
816 const struct drm_display_mode
*adjusted_mode
;
818 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
820 /* disable framebuffer compression in vGPU */
821 if (intel_vgpu_active(dev_priv
->dev
))
824 if (i915
.enable_fbc
< 0) {
825 set_no_fbc_reason(dev_priv
, "disabled per chip default");
829 if (!i915
.enable_fbc
) {
830 set_no_fbc_reason(dev_priv
, "disabled per module param");
835 * If FBC is already on, we just have to verify that we can
836 * keep it that way...
837 * Need to disable if:
838 * - more than one pipe is active
839 * - changing FBC params (stride, fence, mode)
840 * - new fb is too large to fit in compressed buffer
841 * - going to an unsupported config (interlace, pixel multiply, etc.)
843 crtc
= intel_fbc_find_crtc(dev_priv
);
845 set_no_fbc_reason(dev_priv
, "no output");
849 if (!multiple_pipes_ok(dev_priv
)) {
850 set_no_fbc_reason(dev_priv
, "more than one pipe active");
854 intel_crtc
= to_intel_crtc(crtc
);
855 fb
= crtc
->primary
->fb
;
856 obj
= intel_fb_obj(fb
);
857 adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
859 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
860 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
861 set_no_fbc_reason(dev_priv
, "incompatible mode");
865 if (!intel_fbc_hw_tracking_covers_screen(intel_crtc
)) {
866 set_no_fbc_reason(dev_priv
, "mode too large for compression");
870 if ((INTEL_INFO(dev_priv
)->gen
< 4 || HAS_DDI(dev_priv
)) &&
871 intel_crtc
->plane
!= PLANE_A
) {
872 set_no_fbc_reason(dev_priv
, "FBC unsupported on plane");
876 /* The use of a CPU fence is mandatory in order to detect writes
877 * by the CPU to the scanout and trigger updates to the FBC.
879 if (obj
->tiling_mode
!= I915_TILING_X
||
880 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
881 set_no_fbc_reason(dev_priv
, "framebuffer not tiled or fenced");
884 if (INTEL_INFO(dev_priv
)->gen
<= 4 && !IS_G4X(dev_priv
) &&
885 crtc
->primary
->state
->rotation
!= BIT(DRM_ROTATE_0
)) {
886 set_no_fbc_reason(dev_priv
, "rotation unsupported");
890 if (!stride_is_valid(dev_priv
, fb
->pitches
[0])) {
891 set_no_fbc_reason(dev_priv
, "framebuffer stride not supported");
895 if (!pixel_format_is_valid(fb
)) {
896 set_no_fbc_reason(dev_priv
, "pixel format is invalid");
900 /* If the kernel debugger is active, always disable compression */
901 if (in_dbg_master()) {
902 set_no_fbc_reason(dev_priv
, "Kernel debugger is active");
906 /* WaFbcExceedCdClockThreshold:hsw,bdw */
907 if ((IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) &&
908 ilk_pipe_pixel_rate(intel_crtc
->config
) >=
909 dev_priv
->cdclk_freq
* 95 / 100) {
910 set_no_fbc_reason(dev_priv
, "pixel rate is too big");
914 if (intel_fbc_setup_cfb(intel_crtc
)) {
915 set_no_fbc_reason(dev_priv
, "not enough stolen memory");
919 /* If the scanout has not changed, don't modify the FBC settings.
920 * Note that we make the fundamental assumption that the fb->obj
921 * cannot be unpinned (and have its GTT offset and fence revoked)
922 * without first being decoupled from the scanout and FBC disabled.
924 if (dev_priv
->fbc
.crtc
== intel_crtc
&&
925 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
926 dev_priv
->fbc
.y
== crtc
->y
)
929 if (intel_fbc_enabled(dev_priv
)) {
930 /* We update FBC along two paths, after changing fb/crtc
931 * configuration (modeswitching) and after page-flipping
932 * finishes. For the latter, we know that not only did
933 * we disable the FBC at the start of the page-flip
934 * sequence, but also more than one vblank has passed.
936 * For the former case of modeswitching, it is possible
937 * to switch between two FBC valid configurations
938 * instantaneously so we do need to disable the FBC
939 * before we can modify its control registers. We also
940 * have to wait for the next vblank for that to take
941 * effect. However, since we delay enabling FBC we can
942 * assume that a vblank has passed since disabling and
943 * that we can safely alter the registers in the deferred
946 * In the scenario that we go from a valid to invalid
947 * and then back to valid FBC configuration we have
948 * no strict enforcement that a vblank occurred since
949 * disabling the FBC. However, along all current pipe
950 * disabling paths we do need to wait for a vblank at
951 * some point. And we wait before enabling FBC anyway.
953 DRM_DEBUG_KMS("disabling active FBC for update\n");
954 __intel_fbc_disable(dev_priv
);
957 intel_fbc_schedule_enable(intel_crtc
);
958 dev_priv
->fbc
.no_fbc_reason
= "FBC enabled (not necessarily active)";
962 /* Multiple disables should be harmless */
963 if (intel_fbc_enabled(dev_priv
)) {
964 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
965 __intel_fbc_disable(dev_priv
);
967 __intel_fbc_cleanup_cfb(dev_priv
);
971 * intel_fbc_update - enable/disable FBC as needed
972 * @dev_priv: i915 device instance
974 * This function reevaluates the overall state and enables or disables FBC.
976 void intel_fbc_update(struct drm_i915_private
*dev_priv
)
978 if (!fbc_supported(dev_priv
))
981 mutex_lock(&dev_priv
->fbc
.lock
);
982 __intel_fbc_update(dev_priv
);
983 mutex_unlock(&dev_priv
->fbc
.lock
);
986 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
987 unsigned int frontbuffer_bits
,
988 enum fb_op_origin origin
)
990 unsigned int fbc_bits
;
992 if (!fbc_supported(dev_priv
))
995 if (origin
== ORIGIN_GTT
)
998 mutex_lock(&dev_priv
->fbc
.lock
);
1000 if (dev_priv
->fbc
.enabled
)
1001 fbc_bits
= INTEL_FRONTBUFFER_PRIMARY(dev_priv
->fbc
.crtc
->pipe
);
1002 else if (dev_priv
->fbc
.fbc_work
)
1003 fbc_bits
= INTEL_FRONTBUFFER_PRIMARY(
1004 dev_priv
->fbc
.fbc_work
->crtc
->pipe
);
1006 fbc_bits
= dev_priv
->fbc
.possible_framebuffer_bits
;
1008 dev_priv
->fbc
.busy_bits
|= (fbc_bits
& frontbuffer_bits
);
1010 if (dev_priv
->fbc
.busy_bits
)
1011 __intel_fbc_disable(dev_priv
);
1013 mutex_unlock(&dev_priv
->fbc
.lock
);
1016 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1017 unsigned int frontbuffer_bits
, enum fb_op_origin origin
)
1019 if (!fbc_supported(dev_priv
))
1022 if (origin
== ORIGIN_GTT
)
1025 mutex_lock(&dev_priv
->fbc
.lock
);
1027 dev_priv
->fbc
.busy_bits
&= ~frontbuffer_bits
;
1029 if (!dev_priv
->fbc
.busy_bits
) {
1030 __intel_fbc_disable(dev_priv
);
1031 __intel_fbc_update(dev_priv
);
1034 mutex_unlock(&dev_priv
->fbc
.lock
);
1038 * intel_fbc_init - Initialize FBC
1039 * @dev_priv: the i915 device
1041 * This function might be called during PM init process.
1043 void intel_fbc_init(struct drm_i915_private
*dev_priv
)
1047 mutex_init(&dev_priv
->fbc
.lock
);
1049 if (!HAS_FBC(dev_priv
)) {
1050 dev_priv
->fbc
.enabled
= false;
1051 dev_priv
->fbc
.no_fbc_reason
= "unsupported by this chipset";
1055 for_each_pipe(dev_priv
, pipe
) {
1056 dev_priv
->fbc
.possible_framebuffer_bits
|=
1057 INTEL_FRONTBUFFER_PRIMARY(pipe
);
1059 if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)
1063 if (INTEL_INFO(dev_priv
)->gen
>= 7) {
1064 dev_priv
->fbc
.fbc_enabled
= ilk_fbc_enabled
;
1065 dev_priv
->fbc
.enable_fbc
= gen7_fbc_enable
;
1066 dev_priv
->fbc
.disable_fbc
= ilk_fbc_disable
;
1067 } else if (INTEL_INFO(dev_priv
)->gen
>= 5) {
1068 dev_priv
->fbc
.fbc_enabled
= ilk_fbc_enabled
;
1069 dev_priv
->fbc
.enable_fbc
= ilk_fbc_enable
;
1070 dev_priv
->fbc
.disable_fbc
= ilk_fbc_disable
;
1071 } else if (IS_GM45(dev_priv
)) {
1072 dev_priv
->fbc
.fbc_enabled
= g4x_fbc_enabled
;
1073 dev_priv
->fbc
.enable_fbc
= g4x_fbc_enable
;
1074 dev_priv
->fbc
.disable_fbc
= g4x_fbc_disable
;
1076 dev_priv
->fbc
.fbc_enabled
= i8xx_fbc_enabled
;
1077 dev_priv
->fbc
.enable_fbc
= i8xx_fbc_enable
;
1078 dev_priv
->fbc
.disable_fbc
= i8xx_fbc_disable
;
1080 /* This value was pulled out of someone's hat */
1081 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
1084 dev_priv
->fbc
.enabled
= dev_priv
->fbc
.fbc_enabled(dev_priv
);