drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static void i8xx_fbc_disable(struct drm_device *dev)
  45 {
  46         struct drm_i915_private *dev_priv = dev->dev_private;
  47         u32 fbc_ctl;
  48
  49         dev_priv->fbc.enabled = false;
  50
  51         /* Disable compression */
  52         fbc_ctl = I915_READ(FBC_CONTROL);
  53         if ((fbc_ctl & FBC_CTL_EN) == 0)
  54                 return;
  55
  56         fbc_ctl &= ~FBC_CTL_EN;
  57         I915_WRITE(FBC_CONTROL, fbc_ctl);
  58
  59         /* Wait for compressing bit to clear */
  60         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  61                 DRM_DEBUG_KMS("FBC idle timed out\n");
  62                 return;
  63         }
  64
  65         DRM_DEBUG_KMS("disabled FBC\n");
  66 }
  67
  68 static void i8xx_fbc_enable(struct drm_crtc *crtc)
  69 {
  70         struct drm_device *dev = crtc->dev;
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         struct drm_framebuffer *fb = crtc->primary->fb;
  73         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  74         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  75         int cfb_pitch;
  76         int i;
  77         u32 fbc_ctl;
  78
  79         dev_priv->fbc.enabled = true;
  80
  81         /* Note: fbc.threshold == 1 for i8xx */
  82         cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE;
  83         if (fb->pitches[0] < cfb_pitch)
  84                 cfb_pitch = fb->pitches[0];
  85
  86         /* FBC_CTL wants 32B or 64B units */
  87         if (IS_GEN2(dev))
  88                 cfb_pitch = (cfb_pitch / 32) - 1;
  89         else
  90                 cfb_pitch = (cfb_pitch / 64) - 1;
  91
  92         /* Clear old tags */
  93         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  94                 I915_WRITE(FBC_TAG + (i * 4), 0);
  95
  96         if (IS_GEN4(dev)) {
  97                 u32 fbc_ctl2;
  98
  99                 /* Set it up... */
 100                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 101                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 102                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 103                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 104         }
 105
 106         /* enable it... */
 107         fbc_ctl = I915_READ(FBC_CONTROL);
 108         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 109         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 110         if (IS_I945GM(dev))
 111                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 112         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 113         fbc_ctl |= obj->fence_reg;
 114         I915_WRITE(FBC_CONTROL, fbc_ctl);
 115
 116         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 117                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 118 }
 119
 120 static bool i8xx_fbc_enabled(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123
 124         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 125 }
 126
 127 static void g4x_fbc_enable(struct drm_crtc *crtc)
 128 {
 129         struct drm_device *dev = crtc->dev;
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         struct drm_framebuffer *fb = crtc->primary->fb;
 132         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 134         u32 dpfc_ctl;
 135
 136         dev_priv->fbc.enabled = true;
 137
 138         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 139         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 140                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 141         else
 142                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 143         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 144
 145         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 146
 147         /* enable it... */
 148         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 149
 150         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 151 }
 152
 153 static void g4x_fbc_disable(struct drm_device *dev)
 154 {
 155         struct drm_i915_private *dev_priv = dev->dev_private;
 156         u32 dpfc_ctl;
 157
 158         dev_priv->fbc.enabled = false;
 159
 160         /* Disable compression */
 161         dpfc_ctl = I915_READ(DPFC_CONTROL);
 162         if (dpfc_ctl & DPFC_CTL_EN) {
 163                 dpfc_ctl &= ~DPFC_CTL_EN;
 164                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 165
 166                 DRM_DEBUG_KMS("disabled FBC\n");
 167         }
 168 }
 169
 170 static bool g4x_fbc_enabled(struct drm_device *dev)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173
 174         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 175 }
 176
 177 static void snb_fbc_blit_update(struct drm_device *dev)
 178 {
 179         struct drm_i915_private *dev_priv = dev->dev_private;
 180         u32 blt_ecoskpd;
 181
 182         /* Make sure blitter notifies FBC of writes */
 183
 184         /* Blitter is part of Media powerwell on VLV. No impact of
 185          * his param in other platforms for now */
 186         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
 187
 188         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 189         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 190                 GEN6_BLITTER_LOCK_SHIFT;
 191         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 192         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 193         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 194         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 195                          GEN6_BLITTER_LOCK_SHIFT);
 196         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 197         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 198
 199         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
 200 }
 201
 202 static void ilk_fbc_enable(struct drm_crtc *crtc)
 203 {
 204         struct drm_device *dev = crtc->dev;
 205         struct drm_i915_private *dev_priv = dev->dev_private;
 206         struct drm_framebuffer *fb = crtc->primary->fb;
 207         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 209         u32 dpfc_ctl;
 210
 211         dev_priv->fbc.enabled = true;
 212
 213         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 214         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 215                 dev_priv->fbc.threshold++;
 216
 217         switch (dev_priv->fbc.threshold) {
 218         case 4:
 219         case 3:
 220                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 221                 break;
 222         case 2:
 223                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 224                 break;
 225         case 1:
 226                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 227                 break;
 228         }
 229         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 230         if (IS_GEN5(dev))
 231                 dpfc_ctl |= obj->fence_reg;
 232
 233         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 234         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 235         /* enable it... */
 236         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 237
 238         if (IS_GEN6(dev)) {
 239                 I915_WRITE(SNB_DPFC_CTL_SA,
 240                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 241                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 242                 snb_fbc_blit_update(dev);
 243         }
 244
 245         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 246 }
 247
 248 static void ilk_fbc_disable(struct drm_device *dev)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         u32 dpfc_ctl;
 252
 253         dev_priv->fbc.enabled = false;
 254
 255         /* Disable compression */
 256         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 257         if (dpfc_ctl & DPFC_CTL_EN) {
 258                 dpfc_ctl &= ~DPFC_CTL_EN;
 259                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 260
 261                 DRM_DEBUG_KMS("disabled FBC\n");
 262         }
 263 }
 264
 265 static bool ilk_fbc_enabled(struct drm_device *dev)
 266 {
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268
 269         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 270 }
 271
 272 static void gen7_fbc_enable(struct drm_crtc *crtc)
 273 {
 274         struct drm_device *dev = crtc->dev;
 275         struct drm_i915_private *dev_priv = dev->dev_private;
 276         struct drm_framebuffer *fb = crtc->primary->fb;
 277         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 279         u32 dpfc_ctl;
 280
 281         dev_priv->fbc.enabled = true;
 282
 283         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 284         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 285                 dev_priv->fbc.threshold++;
 286
 287         switch (dev_priv->fbc.threshold) {
 288         case 4:
 289         case 3:
 290                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 291                 break;
 292         case 2:
 293                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 294                 break;
 295         case 1:
 296                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 297                 break;
 298         }
 299
 300         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 301
 302         if (dev_priv->fbc.false_color)
 303                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 304
 305         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 306
 307         if (IS_IVYBRIDGE(dev)) {
 308                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 309                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 310                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 311                            ILK_FBCQ_DIS);
 312         } else {
 313                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 314                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 315                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 316                            HSW_FBCQ_DIS);
 317         }
 318
 319         I915_WRITE(SNB_DPFC_CTL_SA,
 320                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 321         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 322
 323         snb_fbc_blit_update(dev);
 324
 325         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 326 }
 327
 328 /**
 329  * intel_fbc_enabled - Is FBC enabled?
 330  * @dev: the drm_device
 331  *
 332  * This function is used to verify the current state of FBC.
 333  * FIXME: This should be tracked in the plane config eventually
 334  *        instead of queried at runtime for most callers.
 335  */
 336 bool intel_fbc_enabled(struct drm_device *dev)
 337 {
 338         struct drm_i915_private *dev_priv = dev->dev_private;
 339
 340         return dev_priv->fbc.enabled;
 341 }
 342
 343 void bdw_fbc_sw_flush(struct drm_device *dev, u32 value)
 344 {
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346
 347         if (!IS_GEN8(dev))
 348                 return;
 349
 350         if (!intel_fbc_enabled(dev))
 351                 return;
 352
 353         I915_WRITE(MSG_FBC_REND_STATE, value);
 354 }
 355
 356 static void intel_fbc_work_fn(struct work_struct *__work)
 357 {
 358         struct intel_fbc_work *work =
 359                 container_of(to_delayed_work(__work),
 360                              struct intel_fbc_work, work);
 361         struct drm_device *dev = work->crtc->dev;
 362         struct drm_i915_private *dev_priv = dev->dev_private;
 363
 364         mutex_lock(&dev->struct_mutex);
 365         if (work == dev_priv->fbc.fbc_work) {
 366                 /* Double check that we haven't switched fb without cancelling
 367                  * the prior work.
 368                  */
 369                 if (work->crtc->primary->fb == work->fb) {
 370                         dev_priv->display.enable_fbc(work->crtc);
 371
 372                         dev_priv->fbc.crtc = to_intel_crtc(work->crtc);
 373                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 374                         dev_priv->fbc.y = work->crtc->y;
 375                 }
 376
 377                 dev_priv->fbc.fbc_work = NULL;
 378         }
 379         mutex_unlock(&dev->struct_mutex);
 380
 381         kfree(work);
 382 }
 383
 384 static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv)
 385 {
 386         if (dev_priv->fbc.fbc_work == NULL)
 387                 return;
 388
 389         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 390
 391         /* Synchronisation is provided by struct_mutex and checking of
 392          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 393          * entirely asynchronously.
 394          */
 395         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 396                 /* tasklet was killed before being run, clean up */
 397                 kfree(dev_priv->fbc.fbc_work);
 398
 399         /* Mark the work as no longer wanted so that if it does
 400          * wake-up (because the work was already running and waiting
 401          * for our mutex), it will discover that is no longer
 402          * necessary to run.
 403          */
 404         dev_priv->fbc.fbc_work = NULL;
 405 }
 406
 407 static void intel_fbc_enable(struct drm_crtc *crtc)
 408 {
 409         struct intel_fbc_work *work;
 410         struct drm_device *dev = crtc->dev;
 411         struct drm_i915_private *dev_priv = dev->dev_private;
 412
 413         if (!dev_priv->display.enable_fbc)
 414                 return;
 415
 416         intel_fbc_cancel_work(dev_priv);
 417
 418         work = kzalloc(sizeof(*work), GFP_KERNEL);
 419         if (work == NULL) {
 420                 DRM_ERROR("Failed to allocate FBC work structure\n");
 421                 dev_priv->display.enable_fbc(crtc);
 422                 return;
 423         }
 424
 425         work->crtc = crtc;
 426         work->fb = crtc->primary->fb;
 427         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 428
 429         dev_priv->fbc.fbc_work = work;
 430
 431         /* Delay the actual enabling to let pageflipping cease and the
 432          * display to settle before starting the compression. Note that
 433          * this delay also serves a second purpose: it allows for a
 434          * vblank to pass after disabling the FBC before we attempt
 435          * to modify the control registers.
 436          *
 437          * A more complicated solution would involve tracking vblanks
 438          * following the termination of the page-flipping sequence
 439          * and indeed performing the enable as a co-routine and not
 440          * waiting synchronously upon the vblank.
 441          *
 442          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 443          */
 444         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 445 }
 446
 447 /**
 448  * intel_fbc_disable - disable FBC
 449  * @dev: the drm_device
 450  *
 451  * This function disables FBC.
 452  */
 453 void intel_fbc_disable(struct drm_device *dev)
 454 {
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456
 457         intel_fbc_cancel_work(dev_priv);
 458
 459         if (!dev_priv->display.disable_fbc)
 460                 return;
 461
 462         dev_priv->display.disable_fbc(dev);
 463         dev_priv->fbc.crtc = NULL;
 464 }
 465
 466 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 467                               enum no_fbc_reason reason)
 468 {
 469         if (dev_priv->fbc.no_fbc_reason == reason)
 470                 return false;
 471
 472         dev_priv->fbc.no_fbc_reason = reason;
 473         return true;
 474 }
 475
 476 static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv)
 477 {
 478         struct drm_crtc *crtc = NULL, *tmp_crtc;
 479         enum pipe pipe;
 480         bool pipe_a_only = false, one_pipe_only = false;
 481
 482         if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
 483                 pipe_a_only = true;
 484         else if (INTEL_INFO(dev_priv)->gen <= 4)
 485                 one_pipe_only = true;
 486
 487         for_each_pipe(dev_priv, pipe) {
 488                 tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 489
 490                 if (intel_crtc_active(tmp_crtc) &&
 491                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 492                         if (one_pipe_only && crtc) {
 493                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 494                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 495                                 return NULL;
 496                         }
 497                         crtc = tmp_crtc;
 498                 }
 499
 500                 if (pipe_a_only)
 501                         break;
 502         }
 503
 504         if (!crtc || crtc->primary->fb == NULL) {
 505                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 506                         DRM_DEBUG_KMS("no output, disabling\n");
 507                 return NULL;
 508         }
 509
 510         return crtc;
 511 }
 512
 513 /**
 514  * intel_fbc_update - enable/disable FBC as needed
 515  * @dev: the drm_device
 516  *
 517  * Set up the framebuffer compression hardware at mode set time.  We
 518  * enable it if possible:
 519  *   - plane A only (on pre-965)
 520  *   - no pixel mulitply/line duplication
 521  *   - no alpha buffer discard
 522  *   - no dual wide
 523  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 524  *
 525  * We can't assume that any compression will take place (worst case),
 526  * so the compressed buffer has to be the same size as the uncompressed
 527  * one.  It also must reside (along with the line length buffer) in
 528  * stolen memory.
 529  *
 530  * We need to enable/disable FBC on a global basis.
 531  */
 532 void intel_fbc_update(struct drm_device *dev)
 533 {
 534         struct drm_i915_private *dev_priv = dev->dev_private;
 535         struct drm_crtc *crtc = NULL;
 536         struct intel_crtc *intel_crtc;
 537         struct drm_framebuffer *fb;
 538         struct drm_i915_gem_object *obj;
 539         const struct drm_display_mode *adjusted_mode;
 540         unsigned int max_width, max_height;
 541
 542         if (!HAS_FBC(dev))
 543                 return;
 544
 545         /* disable framebuffer compression in vGPU */
 546         if (intel_vgpu_active(dev))
 547                 i915.enable_fbc = 0;
 548
 549         if (i915.enable_fbc < 0) {
 550                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 551                         DRM_DEBUG_KMS("disabled per chip default\n");
 552                 goto out_disable;
 553         }
 554
 555         if (!i915.enable_fbc || !i915.powersave) {
 556                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 557                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 558                 goto out_disable;
 559         }
 560
 561         /*
 562          * If FBC is already on, we just have to verify that we can
 563          * keep it that way...
 564          * Need to disable if:
 565          *   - more than one pipe is active
 566          *   - changing FBC params (stride, fence, mode)
 567          *   - new fb is too large to fit in compressed buffer
 568          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 569          */
 570         crtc = intel_fbc_find_crtc(dev_priv);
 571         if (!crtc)
 572                 goto out_disable;
 573
 574         intel_crtc = to_intel_crtc(crtc);
 575         fb = crtc->primary->fb;
 576         obj = intel_fb_obj(fb);
 577         adjusted_mode = &intel_crtc->config->base.adjusted_mode;
 578
 579         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 580             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 581                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 582                         DRM_DEBUG_KMS("mode incompatible with compression, "
 583                                       "disabling\n");
 584                 goto out_disable;
 585         }
 586
 587         if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
 588                 max_width = 4096;
 589                 max_height = 4096;
 590         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 591                 max_width = 4096;
 592                 max_height = 2048;
 593         } else {
 594                 max_width = 2048;
 595                 max_height = 1536;
 596         }
 597         if (intel_crtc->config->pipe_src_w > max_width ||
 598             intel_crtc->config->pipe_src_h > max_height) {
 599                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 600                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 601                 goto out_disable;
 602         }
 603         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 604             intel_crtc->plane != PLANE_A) {
 605                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 606                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 607                 goto out_disable;
 608         }
 609
 610         /* The use of a CPU fence is mandatory in order to detect writes
 611          * by the CPU to the scanout and trigger updates to the FBC.
 612          */
 613         if (obj->tiling_mode != I915_TILING_X ||
 614             obj->fence_reg == I915_FENCE_REG_NONE) {
 615                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 616                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 617                 goto out_disable;
 618         }
 619         if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
 620             crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) {
 621                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 622                         DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
 623                 goto out_disable;
 624         }
 625
 626         /* If the kernel debugger is active, always disable compression */
 627         if (in_dbg_master())
 628                 goto out_disable;
 629
 630         if (i915_gem_stolen_setup_compression(dev, obj->base.size,
 631                                               drm_format_plane_cpp(fb->pixel_format, 0))) {
 632                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 633                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 634                 goto out_disable;
 635         }
 636
 637         /* If the scanout has not changed, don't modify the FBC settings.
 638          * Note that we make the fundamental assumption that the fb->obj
 639          * cannot be unpinned (and have its GTT offset and fence revoked)
 640          * without first being decoupled from the scanout and FBC disabled.
 641          */
 642         if (dev_priv->fbc.crtc == intel_crtc &&
 643             dev_priv->fbc.fb_id == fb->base.id &&
 644             dev_priv->fbc.y == crtc->y)
 645                 return;
 646
 647         if (intel_fbc_enabled(dev)) {
 648                 /* We update FBC along two paths, after changing fb/crtc
 649                  * configuration (modeswitching) and after page-flipping
 650                  * finishes. For the latter, we know that not only did
 651                  * we disable the FBC at the start of the page-flip
 652                  * sequence, but also more than one vblank has passed.
 653                  *
 654                  * For the former case of modeswitching, it is possible
 655                  * to switch between two FBC valid configurations
 656                  * instantaneously so we do need to disable the FBC
 657                  * before we can modify its control registers. We also
 658                  * have to wait for the next vblank for that to take
 659                  * effect. However, since we delay enabling FBC we can
 660                  * assume that a vblank has passed since disabling and
 661                  * that we can safely alter the registers in the deferred
 662                  * callback.
 663                  *
 664                  * In the scenario that we go from a valid to invalid
 665                  * and then back to valid FBC configuration we have
 666                  * no strict enforcement that a vblank occurred since
 667                  * disabling the FBC. However, along all current pipe
 668                  * disabling paths we do need to wait for a vblank at
 669                  * some point. And we wait before enabling FBC anyway.
 670                  */
 671                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 672                 intel_fbc_disable(dev);
 673         }
 674
 675         intel_fbc_enable(crtc);
 676         dev_priv->fbc.no_fbc_reason = FBC_OK;
 677         return;
 678
 679 out_disable:
 680         /* Multiple disables should be harmless */
 681         if (intel_fbc_enabled(dev)) {
 682                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 683                 intel_fbc_disable(dev);
 684         }
 685         i915_gem_stolen_cleanup_compression(dev);
 686 }
 687
 688 /**
 689  * intel_fbc_init - Initialize FBC
 690  * @dev_priv: the i915 device
 691  *
 692  * This function might be called during PM init process.
 693  */
 694 void intel_fbc_init(struct drm_i915_private *dev_priv)
 695 {
 696         if (!HAS_FBC(dev_priv)) {
 697                 dev_priv->fbc.enabled = false;
 698                 dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED;
 699                 return;
 700         }
 701
 702         if (INTEL_INFO(dev_priv)->gen >= 7) {
 703                 dev_priv->display.fbc_enabled = ilk_fbc_enabled;
 704                 dev_priv->display.enable_fbc = gen7_fbc_enable;
 705                 dev_priv->display.disable_fbc = ilk_fbc_disable;
 706         } else if (INTEL_INFO(dev_priv)->gen >= 5) {
 707                 dev_priv->display.fbc_enabled = ilk_fbc_enabled;
 708                 dev_priv->display.enable_fbc = ilk_fbc_enable;
 709                 dev_priv->display.disable_fbc = ilk_fbc_disable;
 710         } else if (IS_GM45(dev_priv)) {
 711                 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
 712                 dev_priv->display.enable_fbc = g4x_fbc_enable;
 713                 dev_priv->display.disable_fbc = g4x_fbc_disable;
 714         } else {
 715                 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
 716                 dev_priv->display.enable_fbc = i8xx_fbc_enable;
 717                 dev_priv->display.disable_fbc = i8xx_fbc_disable;
 718
 719                 /* This value was pulled out of someone's hat */
 720                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
 721         }
 722
 723         dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
 724 }