2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Frame Buffer Compression (FBC)
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
41 #include "intel_drv.h"
44 static inline bool fbc_supported(struct drm_i915_private
*dev_priv
)
46 return HAS_FBC(dev_priv
);
49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private
*dev_priv
)
51 return IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8;
54 static inline bool fbc_on_plane_a_only(struct drm_i915_private
*dev_priv
)
56 return INTEL_INFO(dev_priv
)->gen
< 4;
59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private
*dev_priv
)
61 return INTEL_INFO(dev_priv
)->gen
<= 3;
65 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
66 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
67 * origin so the x and y offsets can actually fit the registers. As a
68 * consequence, the fence doesn't really start exactly at the display plane
69 * address we program because it starts at the real start of the buffer, so we
70 * have to take this into consideration here.
72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc
*crtc
)
74 return crtc
->base
.y
- crtc
->adjusted_y
;
78 * For SKL+, the plane source size used by the hardware is based on the value we
79 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
80 * we wrote to PIPESRC.
82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache
*cache
,
83 int *width
, int *height
)
87 if (intel_rotation_90_or_270(cache
->plane
.rotation
)) {
88 w
= cache
->plane
.src_h
;
89 h
= cache
->plane
.src_w
;
91 w
= cache
->plane
.src_w
;
92 h
= cache
->plane
.src_h
;
101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private
*dev_priv
,
102 struct intel_fbc_state_cache
*cache
)
106 intel_fbc_get_plane_source_size(cache
, NULL
, &lines
);
107 if (INTEL_INFO(dev_priv
)->gen
>= 7)
108 lines
= min(lines
, 2048);
110 /* Hardware needs the full buffer stride, not just the active area. */
111 return lines
* cache
->fb
.stride
;
114 static void i8xx_fbc_deactivate(struct drm_i915_private
*dev_priv
)
118 /* Disable compression */
119 fbc_ctl
= I915_READ(FBC_CONTROL
);
120 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
123 fbc_ctl
&= ~FBC_CTL_EN
;
124 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
126 /* Wait for compressing bit to clear */
127 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
128 DRM_DEBUG_KMS("FBC idle timed out\n");
133 static void i8xx_fbc_activate(struct drm_i915_private
*dev_priv
)
135 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
140 /* Note: fbc.threshold == 1 for i8xx */
141 cfb_pitch
= params
->cfb_size
/ FBC_LL_SIZE
;
142 if (params
->fb
.stride
< cfb_pitch
)
143 cfb_pitch
= params
->fb
.stride
;
145 /* FBC_CTL wants 32B or 64B units */
146 if (IS_GEN2(dev_priv
))
147 cfb_pitch
= (cfb_pitch
/ 32) - 1;
149 cfb_pitch
= (cfb_pitch
/ 64) - 1;
152 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
153 I915_WRITE(FBC_TAG(i
), 0);
155 if (IS_GEN4(dev_priv
)) {
159 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
160 fbc_ctl2
|= FBC_CTL_PLANE(params
->crtc
.plane
);
161 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
162 I915_WRITE(FBC_FENCE_OFF
, params
->crtc
.fence_y_offset
);
166 fbc_ctl
= I915_READ(FBC_CONTROL
);
167 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
168 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
169 if (IS_I945GM(dev_priv
))
170 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
171 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
172 fbc_ctl
|= params
->fb
.fence_reg
;
173 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
176 static bool i8xx_fbc_is_active(struct drm_i915_private
*dev_priv
)
178 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
181 static void g4x_fbc_activate(struct drm_i915_private
*dev_priv
)
183 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
186 dpfc_ctl
= DPFC_CTL_PLANE(params
->crtc
.plane
) | DPFC_SR_EN
;
187 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
188 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
190 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
191 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| params
->fb
.fence_reg
;
193 I915_WRITE(DPFC_FENCE_YOFF
, params
->crtc
.fence_y_offset
);
196 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
199 static void g4x_fbc_deactivate(struct drm_i915_private
*dev_priv
)
203 /* Disable compression */
204 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
205 if (dpfc_ctl
& DPFC_CTL_EN
) {
206 dpfc_ctl
&= ~DPFC_CTL_EN
;
207 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
211 static bool g4x_fbc_is_active(struct drm_i915_private
*dev_priv
)
213 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
216 /* This function forces a CFB recompression through the nuke operation. */
217 static void intel_fbc_recompress(struct drm_i915_private
*dev_priv
)
219 I915_WRITE(MSG_FBC_REND_STATE
, FBC_REND_NUKE
);
220 POSTING_READ(MSG_FBC_REND_STATE
);
223 static void ilk_fbc_activate(struct drm_i915_private
*dev_priv
)
225 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
227 int threshold
= dev_priv
->fbc
.threshold
;
229 dpfc_ctl
= DPFC_CTL_PLANE(params
->crtc
.plane
);
230 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
236 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
239 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
242 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
245 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
246 if (IS_GEN5(dev_priv
))
247 dpfc_ctl
|= params
->fb
.fence_reg
;
249 I915_WRITE(ILK_DPFC_FENCE_YOFF
, params
->crtc
.fence_y_offset
);
250 I915_WRITE(ILK_FBC_RT_BASE
, params
->fb
.ggtt_offset
| ILK_FBC_RT_VALID
);
252 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
254 if (IS_GEN6(dev_priv
)) {
255 I915_WRITE(SNB_DPFC_CTL_SA
,
256 SNB_CPU_FENCE_ENABLE
| params
->fb
.fence_reg
);
257 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, params
->crtc
.fence_y_offset
);
260 intel_fbc_recompress(dev_priv
);
263 static void ilk_fbc_deactivate(struct drm_i915_private
*dev_priv
)
267 /* Disable compression */
268 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
269 if (dpfc_ctl
& DPFC_CTL_EN
) {
270 dpfc_ctl
&= ~DPFC_CTL_EN
;
271 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
275 static bool ilk_fbc_is_active(struct drm_i915_private
*dev_priv
)
277 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
280 static void gen7_fbc_activate(struct drm_i915_private
*dev_priv
)
282 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
284 int threshold
= dev_priv
->fbc
.threshold
;
287 if (IS_IVYBRIDGE(dev_priv
))
288 dpfc_ctl
|= IVB_DPFC_CTL_PLANE(params
->crtc
.plane
);
290 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
296 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
299 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
302 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
306 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
308 if (dev_priv
->fbc
.false_color
)
309 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
311 if (IS_IVYBRIDGE(dev_priv
)) {
312 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
313 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
314 I915_READ(ILK_DISPLAY_CHICKEN1
) |
316 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
317 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
318 I915_WRITE(CHICKEN_PIPESL_1(params
->crtc
.pipe
),
319 I915_READ(CHICKEN_PIPESL_1(params
->crtc
.pipe
)) |
323 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
325 I915_WRITE(SNB_DPFC_CTL_SA
,
326 SNB_CPU_FENCE_ENABLE
| params
->fb
.fence_reg
);
327 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, params
->crtc
.fence_y_offset
);
329 intel_fbc_recompress(dev_priv
);
332 static bool intel_fbc_hw_is_active(struct drm_i915_private
*dev_priv
)
334 if (INTEL_INFO(dev_priv
)->gen
>= 5)
335 return ilk_fbc_is_active(dev_priv
);
336 else if (IS_GM45(dev_priv
))
337 return g4x_fbc_is_active(dev_priv
);
339 return i8xx_fbc_is_active(dev_priv
);
342 static void intel_fbc_hw_activate(struct drm_i915_private
*dev_priv
)
344 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
348 if (INTEL_INFO(dev_priv
)->gen
>= 7)
349 gen7_fbc_activate(dev_priv
);
350 else if (INTEL_INFO(dev_priv
)->gen
>= 5)
351 ilk_fbc_activate(dev_priv
);
352 else if (IS_GM45(dev_priv
))
353 g4x_fbc_activate(dev_priv
);
355 i8xx_fbc_activate(dev_priv
);
358 static void intel_fbc_hw_deactivate(struct drm_i915_private
*dev_priv
)
360 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
364 if (INTEL_INFO(dev_priv
)->gen
>= 5)
365 ilk_fbc_deactivate(dev_priv
);
366 else if (IS_GM45(dev_priv
))
367 g4x_fbc_deactivate(dev_priv
);
369 i8xx_fbc_deactivate(dev_priv
);
373 * intel_fbc_is_active - Is FBC active?
374 * @dev_priv: i915 device instance
376 * This function is used to verify the current state of FBC.
377 * FIXME: This should be tracked in the plane config eventually
378 * instead of queried at runtime for most callers.
380 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
)
382 return dev_priv
->fbc
.active
;
385 static void intel_fbc_work_fn(struct work_struct
*__work
)
387 struct drm_i915_private
*dev_priv
=
388 container_of(__work
, struct drm_i915_private
, fbc
.work
.work
);
389 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
390 struct intel_fbc_work
*work
= &fbc
->work
;
391 struct intel_crtc
*crtc
= fbc
->crtc
;
392 struct drm_vblank_crtc
*vblank
= &dev_priv
->dev
->vblank
[crtc
->pipe
];
394 if (drm_crtc_vblank_get(&crtc
->base
)) {
395 DRM_ERROR("vblank not available for FBC on pipe %c\n",
396 pipe_name(crtc
->pipe
));
398 mutex_lock(&fbc
->lock
);
399 work
->scheduled
= false;
400 mutex_unlock(&fbc
->lock
);
405 /* Delay the actual enabling to let pageflipping cease and the
406 * display to settle before starting the compression. Note that
407 * this delay also serves a second purpose: it allows for a
408 * vblank to pass after disabling the FBC before we attempt
409 * to modify the control registers.
411 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
413 * It is also worth mentioning that since work->scheduled_vblank can be
414 * updated multiple times by the other threads, hitting the timeout is
415 * not an error condition. We'll just end up hitting the "goto retry"
418 wait_event_timeout(vblank
->queue
,
419 drm_crtc_vblank_count(&crtc
->base
) != work
->scheduled_vblank
,
420 msecs_to_jiffies(50));
422 mutex_lock(&fbc
->lock
);
424 /* Were we cancelled? */
425 if (!work
->scheduled
)
428 /* Were we delayed again while this function was sleeping? */
429 if (drm_crtc_vblank_count(&crtc
->base
) == work
->scheduled_vblank
) {
430 mutex_unlock(&fbc
->lock
);
434 intel_fbc_hw_activate(dev_priv
);
436 work
->scheduled
= false;
439 mutex_unlock(&fbc
->lock
);
440 drm_crtc_vblank_put(&crtc
->base
);
443 static void intel_fbc_schedule_activation(struct intel_crtc
*crtc
)
445 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
446 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
447 struct intel_fbc_work
*work
= &fbc
->work
;
449 WARN_ON(!mutex_is_locked(&fbc
->lock
));
451 if (drm_crtc_vblank_get(&crtc
->base
)) {
452 DRM_ERROR("vblank not available for FBC on pipe %c\n",
453 pipe_name(crtc
->pipe
));
457 /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
458 * this function since we're not releasing fbc.lock, so it won't have an
459 * opportunity to grab it to discover that it was cancelled. So we just
460 * update the expected jiffy count. */
461 work
->scheduled
= true;
462 work
->scheduled_vblank
= drm_crtc_vblank_count(&crtc
->base
);
463 drm_crtc_vblank_put(&crtc
->base
);
465 schedule_work(&work
->work
);
468 static void intel_fbc_deactivate(struct drm_i915_private
*dev_priv
)
470 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
472 WARN_ON(!mutex_is_locked(&fbc
->lock
));
474 /* Calling cancel_work() here won't help due to the fact that the work
475 * function grabs fbc->lock. Just set scheduled to false so the work
476 * function can know it was cancelled. */
477 fbc
->work
.scheduled
= false;
480 intel_fbc_hw_deactivate(dev_priv
);
483 static bool multiple_pipes_ok(struct intel_crtc
*crtc
)
485 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
486 struct drm_plane
*primary
= crtc
->base
.primary
;
487 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
488 enum pipe pipe
= crtc
->pipe
;
490 /* Don't even bother tracking anything we don't need. */
491 if (!no_fbc_on_multiple_pipes(dev_priv
))
494 WARN_ON(!drm_modeset_is_locked(&primary
->mutex
));
496 if (to_intel_plane_state(primary
->state
)->visible
)
497 fbc
->visible_pipes_mask
|= (1 << pipe
);
499 fbc
->visible_pipes_mask
&= ~(1 << pipe
);
501 return (fbc
->visible_pipes_mask
& ~(1 << pipe
)) != 0;
504 static int find_compression_threshold(struct drm_i915_private
*dev_priv
,
505 struct drm_mm_node
*node
,
509 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
510 int compression_threshold
= 1;
514 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
515 * reserved range size, so it always assumes the maximum (8mb) is used.
516 * If we enable FBC using a CFB on that memory range we'll get FIFO
517 * underruns, even if that range is not reserved by the BIOS. */
518 if (IS_BROADWELL(dev_priv
) ||
519 IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
520 end
= ggtt
->stolen_size
- 8 * 1024 * 1024;
522 end
= ggtt
->stolen_usable_size
;
524 /* HACK: This code depends on what we will do in *_enable_fbc. If that
525 * code changes, this code needs to change as well.
527 * The enable_fbc code will attempt to use one of our 2 compression
528 * thresholds, therefore, in that case, we only have 1 resort.
531 /* Try to over-allocate to reduce reallocations and fragmentation. */
532 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
<<= 1,
535 return compression_threshold
;
538 /* HW's ability to limit the CFB is 1:4 */
539 if (compression_threshold
> 4 ||
540 (fb_cpp
== 2 && compression_threshold
== 2))
543 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
>>= 1,
545 if (ret
&& INTEL_INFO(dev_priv
)->gen
<= 4) {
548 compression_threshold
<<= 1;
551 return compression_threshold
;
555 static int intel_fbc_alloc_cfb(struct intel_crtc
*crtc
)
557 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
558 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
559 struct drm_mm_node
*uninitialized_var(compressed_llb
);
560 int size
, fb_cpp
, ret
;
562 WARN_ON(drm_mm_node_allocated(&fbc
->compressed_fb
));
564 size
= intel_fbc_calculate_cfb_size(dev_priv
, &fbc
->state_cache
);
565 fb_cpp
= drm_format_plane_cpp(fbc
->state_cache
.fb
.pixel_format
, 0);
567 ret
= find_compression_threshold(dev_priv
, &fbc
->compressed_fb
,
572 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
576 fbc
->threshold
= ret
;
578 if (INTEL_INFO(dev_priv
)->gen
>= 5)
579 I915_WRITE(ILK_DPFC_CB_BASE
, fbc
->compressed_fb
.start
);
580 else if (IS_GM45(dev_priv
)) {
581 I915_WRITE(DPFC_CB_BASE
, fbc
->compressed_fb
.start
);
583 compressed_llb
= kzalloc(sizeof(*compressed_llb
), GFP_KERNEL
);
587 ret
= i915_gem_stolen_insert_node(dev_priv
, compressed_llb
,
592 fbc
->compressed_llb
= compressed_llb
;
594 I915_WRITE(FBC_CFB_BASE
,
595 dev_priv
->mm
.stolen_base
+ fbc
->compressed_fb
.start
);
596 I915_WRITE(FBC_LL_BASE
,
597 dev_priv
->mm
.stolen_base
+ compressed_llb
->start
);
600 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
601 fbc
->compressed_fb
.size
, fbc
->threshold
);
606 kfree(compressed_llb
);
607 i915_gem_stolen_remove_node(dev_priv
, &fbc
->compressed_fb
);
609 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size
);
613 static void __intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
615 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
617 if (drm_mm_node_allocated(&fbc
->compressed_fb
))
618 i915_gem_stolen_remove_node(dev_priv
, &fbc
->compressed_fb
);
620 if (fbc
->compressed_llb
) {
621 i915_gem_stolen_remove_node(dev_priv
, fbc
->compressed_llb
);
622 kfree(fbc
->compressed_llb
);
626 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
628 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
630 if (!fbc_supported(dev_priv
))
633 mutex_lock(&fbc
->lock
);
634 __intel_fbc_cleanup_cfb(dev_priv
);
635 mutex_unlock(&fbc
->lock
);
638 static bool stride_is_valid(struct drm_i915_private
*dev_priv
,
641 /* These should have been caught earlier. */
642 WARN_ON(stride
< 512);
643 WARN_ON((stride
& (64 - 1)) != 0);
645 /* Below are the additional FBC restrictions. */
647 if (IS_GEN2(dev_priv
) || IS_GEN3(dev_priv
))
648 return stride
== 4096 || stride
== 8192;
650 if (IS_GEN4(dev_priv
) && !IS_G4X(dev_priv
) && stride
< 2048)
659 static bool pixel_format_is_valid(struct drm_i915_private
*dev_priv
,
660 uint32_t pixel_format
)
662 switch (pixel_format
) {
663 case DRM_FORMAT_XRGB8888
:
664 case DRM_FORMAT_XBGR8888
:
666 case DRM_FORMAT_XRGB1555
:
667 case DRM_FORMAT_RGB565
:
668 /* 16bpp not supported on gen2 */
669 if (IS_GEN2(dev_priv
))
671 /* WaFbcOnly1to1Ratio:ctg */
672 if (IS_G4X(dev_priv
))
681 * For some reason, the hardware tracking starts looking at whatever we
682 * programmed as the display plane base address register. It does not look at
683 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
684 * variables instead of just looking at the pipe/plane size.
686 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc
*crtc
)
688 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
689 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
690 unsigned int effective_w
, effective_h
, max_w
, max_h
;
692 if (INTEL_INFO(dev_priv
)->gen
>= 8 || IS_HASWELL(dev_priv
)) {
695 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
703 intel_fbc_get_plane_source_size(&fbc
->state_cache
, &effective_w
,
705 effective_w
+= crtc
->adjusted_x
;
706 effective_h
+= crtc
->adjusted_y
;
708 return effective_w
<= max_w
&& effective_h
<= max_h
;
711 static void intel_fbc_update_state_cache(struct intel_crtc
*crtc
)
713 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
714 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
715 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
716 struct intel_crtc_state
*crtc_state
=
717 to_intel_crtc_state(crtc
->base
.state
);
718 struct intel_plane_state
*plane_state
=
719 to_intel_plane_state(crtc
->base
.primary
->state
);
720 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
721 struct drm_i915_gem_object
*obj
;
723 WARN_ON(!drm_modeset_is_locked(&crtc
->base
.mutex
));
724 WARN_ON(!drm_modeset_is_locked(&crtc
->base
.primary
->mutex
));
726 cache
->crtc
.mode_flags
= crtc_state
->base
.adjusted_mode
.flags
;
727 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
728 cache
->crtc
.hsw_bdw_pixel_rate
=
729 ilk_pipe_pixel_rate(crtc_state
);
731 cache
->plane
.rotation
= plane_state
->base
.rotation
;
732 cache
->plane
.src_w
= drm_rect_width(&plane_state
->src
) >> 16;
733 cache
->plane
.src_h
= drm_rect_height(&plane_state
->src
) >> 16;
734 cache
->plane
.visible
= plane_state
->visible
;
736 if (!cache
->plane
.visible
)
739 obj
= intel_fb_obj(fb
);
741 /* FIXME: We lack the proper locking here, so only run this on the
742 * platforms that need. */
743 if (INTEL_INFO(dev_priv
)->gen
>= 5 && INTEL_INFO(dev_priv
)->gen
< 7)
744 cache
->fb
.ilk_ggtt_offset
= i915_gem_obj_ggtt_offset(obj
);
745 cache
->fb
.pixel_format
= fb
->pixel_format
;
746 cache
->fb
.stride
= fb
->pitches
[0];
747 cache
->fb
.fence_reg
= obj
->fence_reg
;
748 cache
->fb
.tiling_mode
= obj
->tiling_mode
;
751 static bool intel_fbc_can_activate(struct intel_crtc
*crtc
)
753 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
754 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
755 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
757 if (!cache
->plane
.visible
) {
758 fbc
->no_fbc_reason
= "primary plane not visible";
762 if ((cache
->crtc
.mode_flags
& DRM_MODE_FLAG_INTERLACE
) ||
763 (cache
->crtc
.mode_flags
& DRM_MODE_FLAG_DBLSCAN
)) {
764 fbc
->no_fbc_reason
= "incompatible mode";
768 if (!intel_fbc_hw_tracking_covers_screen(crtc
)) {
769 fbc
->no_fbc_reason
= "mode too large for compression";
773 /* The use of a CPU fence is mandatory in order to detect writes
774 * by the CPU to the scanout and trigger updates to the FBC.
776 if (cache
->fb
.tiling_mode
!= I915_TILING_X
||
777 cache
->fb
.fence_reg
== I915_FENCE_REG_NONE
) {
778 fbc
->no_fbc_reason
= "framebuffer not tiled or fenced";
781 if (INTEL_INFO(dev_priv
)->gen
<= 4 && !IS_G4X(dev_priv
) &&
782 cache
->plane
.rotation
!= BIT(DRM_ROTATE_0
)) {
783 fbc
->no_fbc_reason
= "rotation unsupported";
787 if (!stride_is_valid(dev_priv
, cache
->fb
.stride
)) {
788 fbc
->no_fbc_reason
= "framebuffer stride not supported";
792 if (!pixel_format_is_valid(dev_priv
, cache
->fb
.pixel_format
)) {
793 fbc
->no_fbc_reason
= "pixel format is invalid";
797 /* WaFbcExceedCdClockThreshold:hsw,bdw */
798 if ((IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) &&
799 cache
->crtc
.hsw_bdw_pixel_rate
>= dev_priv
->cdclk_freq
* 95 / 100) {
800 fbc
->no_fbc_reason
= "pixel rate is too big";
804 /* It is possible for the required CFB size change without a
805 * crtc->disable + crtc->enable since it is possible to change the
806 * stride without triggering a full modeset. Since we try to
807 * over-allocate the CFB, there's a chance we may keep FBC enabled even
808 * if this happens, but if we exceed the current CFB size we'll have to
809 * disable FBC. Notice that it would be possible to disable FBC, wait
810 * for a frame, free the stolen node, then try to reenable FBC in case
811 * we didn't get any invalidate/deactivate calls, but this would require
812 * a lot of tracking just for a specific case. If we conclude it's an
813 * important case, we can implement it later. */
814 if (intel_fbc_calculate_cfb_size(dev_priv
, &fbc
->state_cache
) >
815 fbc
->compressed_fb
.size
* fbc
->threshold
) {
816 fbc
->no_fbc_reason
= "CFB requirements changed";
823 static bool intel_fbc_can_choose(struct intel_crtc
*crtc
)
825 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
826 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
827 bool enable_by_default
= IS_BROADWELL(dev_priv
);
829 if (intel_vgpu_active(dev_priv
->dev
)) {
830 fbc
->no_fbc_reason
= "VGPU is active";
834 if (i915
.enable_fbc
< 0 && !enable_by_default
) {
835 fbc
->no_fbc_reason
= "disabled per chip default";
839 if (!i915
.enable_fbc
) {
840 fbc
->no_fbc_reason
= "disabled per module param";
844 if (fbc_on_pipe_a_only(dev_priv
) && crtc
->pipe
!= PIPE_A
) {
845 fbc
->no_fbc_reason
= "no enabled pipes can have FBC";
849 if (fbc_on_plane_a_only(dev_priv
) && crtc
->plane
!= PLANE_A
) {
850 fbc
->no_fbc_reason
= "no enabled planes can have FBC";
857 static void intel_fbc_get_reg_params(struct intel_crtc
*crtc
,
858 struct intel_fbc_reg_params
*params
)
860 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
861 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
862 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
864 /* Since all our fields are integer types, use memset here so the
865 * comparison function can rely on memcmp because the padding will be
867 memset(params
, 0, sizeof(*params
));
869 params
->crtc
.pipe
= crtc
->pipe
;
870 params
->crtc
.plane
= crtc
->plane
;
871 params
->crtc
.fence_y_offset
= get_crtc_fence_y_offset(crtc
);
873 params
->fb
.pixel_format
= cache
->fb
.pixel_format
;
874 params
->fb
.stride
= cache
->fb
.stride
;
875 params
->fb
.fence_reg
= cache
->fb
.fence_reg
;
877 params
->cfb_size
= intel_fbc_calculate_cfb_size(dev_priv
, cache
);
879 params
->fb
.ggtt_offset
= cache
->fb
.ilk_ggtt_offset
;
882 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params
*params1
,
883 struct intel_fbc_reg_params
*params2
)
885 /* We can use this since intel_fbc_get_reg_params() does a memset. */
886 return memcmp(params1
, params2
, sizeof(*params1
)) == 0;
889 void intel_fbc_pre_update(struct intel_crtc
*crtc
)
891 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
892 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
894 if (!fbc_supported(dev_priv
))
897 mutex_lock(&fbc
->lock
);
899 if (!multiple_pipes_ok(crtc
)) {
900 fbc
->no_fbc_reason
= "more than one pipe active";
904 if (!fbc
->enabled
|| fbc
->crtc
!= crtc
)
907 intel_fbc_update_state_cache(crtc
);
910 intel_fbc_deactivate(dev_priv
);
912 mutex_unlock(&fbc
->lock
);
915 static void __intel_fbc_post_update(struct intel_crtc
*crtc
)
917 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
918 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
919 struct intel_fbc_reg_params old_params
;
921 WARN_ON(!mutex_is_locked(&fbc
->lock
));
923 if (!fbc
->enabled
|| fbc
->crtc
!= crtc
)
926 if (!intel_fbc_can_activate(crtc
)) {
927 WARN_ON(fbc
->active
);
931 old_params
= fbc
->params
;
932 intel_fbc_get_reg_params(crtc
, &fbc
->params
);
934 /* If the scanout has not changed, don't modify the FBC settings.
935 * Note that we make the fundamental assumption that the fb->obj
936 * cannot be unpinned (and have its GTT offset and fence revoked)
937 * without first being decoupled from the scanout and FBC disabled.
940 intel_fbc_reg_params_equal(&old_params
, &fbc
->params
))
943 intel_fbc_deactivate(dev_priv
);
944 intel_fbc_schedule_activation(crtc
);
945 fbc
->no_fbc_reason
= "FBC enabled (active or scheduled)";
948 void intel_fbc_post_update(struct intel_crtc
*crtc
)
950 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
951 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
953 if (!fbc_supported(dev_priv
))
956 mutex_lock(&fbc
->lock
);
957 __intel_fbc_post_update(crtc
);
958 mutex_unlock(&fbc
->lock
);
961 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc
*fbc
)
964 return to_intel_plane(fbc
->crtc
->base
.primary
)->frontbuffer_bit
;
966 return fbc
->possible_framebuffer_bits
;
969 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
970 unsigned int frontbuffer_bits
,
971 enum fb_op_origin origin
)
973 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
975 if (!fbc_supported(dev_priv
))
978 if (origin
== ORIGIN_GTT
|| origin
== ORIGIN_FLIP
)
981 mutex_lock(&fbc
->lock
);
983 fbc
->busy_bits
|= intel_fbc_get_frontbuffer_bit(fbc
) & frontbuffer_bits
;
985 if (fbc
->enabled
&& fbc
->busy_bits
)
986 intel_fbc_deactivate(dev_priv
);
988 mutex_unlock(&fbc
->lock
);
991 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
992 unsigned int frontbuffer_bits
, enum fb_op_origin origin
)
994 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
996 if (!fbc_supported(dev_priv
))
999 if (origin
== ORIGIN_GTT
|| origin
== ORIGIN_FLIP
)
1002 mutex_lock(&fbc
->lock
);
1004 fbc
->busy_bits
&= ~frontbuffer_bits
;
1006 if (!fbc
->busy_bits
&& fbc
->enabled
&&
1007 (frontbuffer_bits
& intel_fbc_get_frontbuffer_bit(fbc
))) {
1009 intel_fbc_recompress(dev_priv
);
1011 __intel_fbc_post_update(fbc
->crtc
);
1014 mutex_unlock(&fbc
->lock
);
1018 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1019 * @dev_priv: i915 device instance
1020 * @state: the atomic state structure
1022 * This function looks at the proposed state for CRTCs and planes, then chooses
1023 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1026 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1027 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1029 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1030 struct drm_atomic_state
*state
)
1032 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1033 struct drm_crtc
*crtc
;
1034 struct drm_crtc_state
*crtc_state
;
1035 struct drm_plane
*plane
;
1036 struct drm_plane_state
*plane_state
;
1037 bool fbc_crtc_present
= false;
1040 mutex_lock(&fbc
->lock
);
1042 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
1043 if (fbc
->crtc
== to_intel_crtc(crtc
)) {
1044 fbc_crtc_present
= true;
1048 /* This atomic commit doesn't involve the CRTC currently tied to FBC. */
1049 if (!fbc_crtc_present
&& fbc
->crtc
!= NULL
)
1052 /* Simply choose the first CRTC that is compatible and has a visible
1053 * plane. We could go for fancier schemes such as checking the plane
1054 * size, but this would just affect the few platforms that don't tie FBC
1055 * to pipe or plane A. */
1056 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
1057 struct intel_plane_state
*intel_plane_state
=
1058 to_intel_plane_state(plane_state
);
1060 if (!intel_plane_state
->visible
)
1063 for_each_crtc_in_state(state
, crtc
, crtc_state
, j
) {
1064 struct intel_crtc_state
*intel_crtc_state
=
1065 to_intel_crtc_state(crtc_state
);
1067 if (plane_state
->crtc
!= crtc
)
1070 if (!intel_fbc_can_choose(to_intel_crtc(crtc
)))
1073 intel_crtc_state
->enable_fbc
= true;
1079 mutex_unlock(&fbc
->lock
);
1083 * intel_fbc_enable: tries to enable FBC on the CRTC
1086 * This function checks if the given CRTC was chosen for FBC, then enables it if
1087 * possible. Notice that it doesn't activate FBC. It is valid to call
1088 * intel_fbc_enable multiple times for the same pipe without an
1089 * intel_fbc_disable in the middle, as long as it is deactivated.
1091 void intel_fbc_enable(struct intel_crtc
*crtc
)
1093 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1094 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1096 if (!fbc_supported(dev_priv
))
1099 mutex_lock(&fbc
->lock
);
1102 WARN_ON(fbc
->crtc
== NULL
);
1103 if (fbc
->crtc
== crtc
) {
1104 WARN_ON(!crtc
->config
->enable_fbc
);
1105 WARN_ON(fbc
->active
);
1110 if (!crtc
->config
->enable_fbc
)
1113 WARN_ON(fbc
->active
);
1114 WARN_ON(fbc
->crtc
!= NULL
);
1116 intel_fbc_update_state_cache(crtc
);
1117 if (intel_fbc_alloc_cfb(crtc
)) {
1118 fbc
->no_fbc_reason
= "not enough stolen memory";
1122 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc
->pipe
));
1123 fbc
->no_fbc_reason
= "FBC enabled but not active yet\n";
1125 fbc
->enabled
= true;
1128 mutex_unlock(&fbc
->lock
);
1132 * __intel_fbc_disable - disable FBC
1133 * @dev_priv: i915 device instance
1135 * This is the low level function that actually disables FBC. Callers should
1136 * grab the FBC lock.
1138 static void __intel_fbc_disable(struct drm_i915_private
*dev_priv
)
1140 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1141 struct intel_crtc
*crtc
= fbc
->crtc
;
1143 WARN_ON(!mutex_is_locked(&fbc
->lock
));
1144 WARN_ON(!fbc
->enabled
);
1145 WARN_ON(fbc
->active
);
1146 WARN_ON(crtc
->active
);
1148 DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc
->pipe
));
1150 __intel_fbc_cleanup_cfb(dev_priv
);
1152 fbc
->enabled
= false;
1157 * intel_fbc_disable - disable FBC if it's associated with crtc
1160 * This function disables FBC if it's associated with the provided CRTC.
1162 void intel_fbc_disable(struct intel_crtc
*crtc
)
1164 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1165 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1167 if (!fbc_supported(dev_priv
))
1170 mutex_lock(&fbc
->lock
);
1171 if (fbc
->crtc
== crtc
) {
1172 WARN_ON(!fbc
->enabled
);
1173 WARN_ON(fbc
->active
);
1174 __intel_fbc_disable(dev_priv
);
1176 mutex_unlock(&fbc
->lock
);
1178 cancel_work_sync(&fbc
->work
.work
);
1182 * intel_fbc_global_disable - globally disable FBC
1183 * @dev_priv: i915 device instance
1185 * This function disables FBC regardless of which CRTC is associated with it.
1187 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
)
1189 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1191 if (!fbc_supported(dev_priv
))
1194 mutex_lock(&fbc
->lock
);
1196 __intel_fbc_disable(dev_priv
);
1197 mutex_unlock(&fbc
->lock
);
1199 cancel_work_sync(&fbc
->work
.work
);
1203 * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1204 * @dev_priv: i915 device instance
1206 * The FBC code needs to track CRTC visibility since the older platforms can't
1207 * have FBC enabled while multiple pipes are used. This function does the
1208 * initial setup at driver load to make sure FBC is matching the real hardware.
1210 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
)
1212 struct intel_crtc
*crtc
;
1214 /* Don't even bother tracking anything if we don't need. */
1215 if (!no_fbc_on_multiple_pipes(dev_priv
))
1218 for_each_intel_crtc(dev_priv
->dev
, crtc
)
1219 if (intel_crtc_active(&crtc
->base
) &&
1220 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
)
1221 dev_priv
->fbc
.visible_pipes_mask
|= (1 << crtc
->pipe
);
1225 * intel_fbc_init - Initialize FBC
1226 * @dev_priv: the i915 device
1228 * This function might be called during PM init process.
1230 void intel_fbc_init(struct drm_i915_private
*dev_priv
)
1232 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1235 INIT_WORK(&fbc
->work
.work
, intel_fbc_work_fn
);
1236 mutex_init(&fbc
->lock
);
1237 fbc
->enabled
= false;
1238 fbc
->active
= false;
1239 fbc
->work
.scheduled
= false;
1241 if (!HAS_FBC(dev_priv
)) {
1242 fbc
->no_fbc_reason
= "unsupported by this chipset";
1246 for_each_pipe(dev_priv
, pipe
) {
1247 fbc
->possible_framebuffer_bits
|=
1248 INTEL_FRONTBUFFER_PRIMARY(pipe
);
1250 if (fbc_on_pipe_a_only(dev_priv
))
1254 /* This value was pulled out of someone's hat */
1255 if (INTEL_INFO(dev_priv
)->gen
<= 4 && !IS_GM45(dev_priv
))
1256 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
1258 /* We still don't have any sort of hardware state readout for FBC, so
1259 * deactivate it in case the BIOS activated it to make sure software
1260 * matches the hardware state. */
1261 if (intel_fbc_hw_is_active(dev_priv
))
1262 intel_fbc_hw_deactivate(dev_priv
);