2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Frame Buffer Compression (FBC)
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
41 #include "intel_drv.h"
44 static void i8xx_fbc_disable(struct drm_i915_private
*dev_priv
)
48 dev_priv
->fbc
.enabled
= false;
50 /* Disable compression */
51 fbc_ctl
= I915_READ(FBC_CONTROL
);
52 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
55 fbc_ctl
&= ~FBC_CTL_EN
;
56 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
58 /* Wait for compressing bit to clear */
59 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
60 DRM_DEBUG_KMS("FBC idle timed out\n");
64 DRM_DEBUG_KMS("disabled FBC\n");
67 static void i8xx_fbc_enable(struct intel_crtc
*crtc
)
69 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
70 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
71 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
76 dev_priv
->fbc
.enabled
= true;
78 /* Note: fbc.threshold == 1 for i8xx */
79 cfb_pitch
= dev_priv
->fbc
.uncompressed_size
/ FBC_LL_SIZE
;
80 if (fb
->pitches
[0] < cfb_pitch
)
81 cfb_pitch
= fb
->pitches
[0];
83 /* FBC_CTL wants 32B or 64B units */
84 if (IS_GEN2(dev_priv
))
85 cfb_pitch
= (cfb_pitch
/ 32) - 1;
87 cfb_pitch
= (cfb_pitch
/ 64) - 1;
90 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
91 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
93 if (IS_GEN4(dev_priv
)) {
97 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
98 fbc_ctl2
|= FBC_CTL_PLANE(crtc
->plane
);
99 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
100 I915_WRITE(FBC_FENCE_OFF
, crtc
->base
.y
);
104 fbc_ctl
= I915_READ(FBC_CONTROL
);
105 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
106 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
107 if (IS_I945GM(dev_priv
))
108 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
109 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
110 fbc_ctl
|= obj
->fence_reg
;
111 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
113 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
114 cfb_pitch
, crtc
->base
.y
, plane_name(crtc
->plane
));
117 static bool i8xx_fbc_enabled(struct drm_i915_private
*dev_priv
)
119 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
122 static void g4x_fbc_enable(struct intel_crtc
*crtc
)
124 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
125 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
126 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
129 dev_priv
->fbc
.enabled
= true;
131 dpfc_ctl
= DPFC_CTL_PLANE(crtc
->plane
) | DPFC_SR_EN
;
132 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
133 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
135 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
136 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
138 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->base
.y
);
141 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
143 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
146 static void g4x_fbc_disable(struct drm_i915_private
*dev_priv
)
150 dev_priv
->fbc
.enabled
= false;
152 /* Disable compression */
153 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
154 if (dpfc_ctl
& DPFC_CTL_EN
) {
155 dpfc_ctl
&= ~DPFC_CTL_EN
;
156 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
158 DRM_DEBUG_KMS("disabled FBC\n");
162 static bool g4x_fbc_enabled(struct drm_i915_private
*dev_priv
)
164 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
167 static void intel_fbc_nuke(struct drm_i915_private
*dev_priv
)
169 I915_WRITE(MSG_FBC_REND_STATE
, FBC_REND_NUKE
);
170 POSTING_READ(MSG_FBC_REND_STATE
);
173 static void ilk_fbc_enable(struct intel_crtc
*crtc
)
175 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
176 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
177 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
179 int threshold
= dev_priv
->fbc
.threshold
;
181 dev_priv
->fbc
.enabled
= true;
183 dpfc_ctl
= DPFC_CTL_PLANE(crtc
->plane
);
184 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
190 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
193 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
196 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
199 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
200 if (IS_GEN5(dev_priv
))
201 dpfc_ctl
|= obj
->fence_reg
;
203 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->base
.y
);
204 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
206 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
208 if (IS_GEN6(dev_priv
)) {
209 I915_WRITE(SNB_DPFC_CTL_SA
,
210 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
211 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->base
.y
);
214 intel_fbc_nuke(dev_priv
);
216 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
219 static void ilk_fbc_disable(struct drm_i915_private
*dev_priv
)
223 dev_priv
->fbc
.enabled
= false;
225 /* Disable compression */
226 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
227 if (dpfc_ctl
& DPFC_CTL_EN
) {
228 dpfc_ctl
&= ~DPFC_CTL_EN
;
229 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
231 DRM_DEBUG_KMS("disabled FBC\n");
235 static bool ilk_fbc_enabled(struct drm_i915_private
*dev_priv
)
237 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
240 static void gen7_fbc_enable(struct intel_crtc
*crtc
)
242 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
243 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
244 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
246 int threshold
= dev_priv
->fbc
.threshold
;
248 dev_priv
->fbc
.enabled
= true;
251 if (IS_IVYBRIDGE(dev_priv
))
252 dpfc_ctl
|= IVB_DPFC_CTL_PLANE(crtc
->plane
);
254 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
260 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
263 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
266 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
270 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
272 if (dev_priv
->fbc
.false_color
)
273 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
275 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
277 if (IS_IVYBRIDGE(dev_priv
)) {
278 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
279 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
280 I915_READ(ILK_DISPLAY_CHICKEN1
) |
283 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
284 I915_WRITE(CHICKEN_PIPESL_1(crtc
->pipe
),
285 I915_READ(CHICKEN_PIPESL_1(crtc
->pipe
)) |
289 I915_WRITE(SNB_DPFC_CTL_SA
,
290 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
291 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->base
.y
);
293 intel_fbc_nuke(dev_priv
);
295 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
299 * intel_fbc_enabled - Is FBC enabled?
300 * @dev_priv: i915 device instance
302 * This function is used to verify the current state of FBC.
303 * FIXME: This should be tracked in the plane config eventually
304 * instead of queried at runtime for most callers.
306 bool intel_fbc_enabled(struct drm_i915_private
*dev_priv
)
308 return dev_priv
->fbc
.enabled
;
311 static void intel_fbc_enable(struct intel_crtc
*crtc
,
312 const struct drm_framebuffer
*fb
)
314 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
316 dev_priv
->fbc
.enable_fbc(crtc
);
318 dev_priv
->fbc
.crtc
= crtc
;
319 dev_priv
->fbc
.fb_id
= fb
->base
.id
;
320 dev_priv
->fbc
.y
= crtc
->base
.y
;
323 static void intel_fbc_work_fn(struct work_struct
*__work
)
325 struct intel_fbc_work
*work
=
326 container_of(to_delayed_work(__work
),
327 struct intel_fbc_work
, work
);
328 struct drm_i915_private
*dev_priv
= work
->crtc
->base
.dev
->dev_private
;
329 struct drm_framebuffer
*crtc_fb
= work
->crtc
->base
.primary
->fb
;
331 mutex_lock(&dev_priv
->fbc
.lock
);
332 if (work
== dev_priv
->fbc
.fbc_work
) {
333 /* Double check that we haven't switched fb without cancelling
336 if (crtc_fb
== work
->fb
)
337 intel_fbc_enable(work
->crtc
, work
->fb
);
339 dev_priv
->fbc
.fbc_work
= NULL
;
341 mutex_unlock(&dev_priv
->fbc
.lock
);
346 static void intel_fbc_cancel_work(struct drm_i915_private
*dev_priv
)
348 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
350 if (dev_priv
->fbc
.fbc_work
== NULL
)
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc.fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
359 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv
->fbc
.fbc_work
);
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
368 dev_priv
->fbc
.fbc_work
= NULL
;
371 static void intel_fbc_schedule_enable(struct intel_crtc
*crtc
)
373 struct intel_fbc_work
*work
;
374 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
376 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
378 intel_fbc_cancel_work(dev_priv
);
380 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
382 DRM_ERROR("Failed to allocate FBC work structure\n");
383 intel_fbc_enable(crtc
, crtc
->base
.primary
->fb
);
388 work
->fb
= crtc
->base
.primary
->fb
;
389 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
391 dev_priv
->fbc
.fbc_work
= work
;
393 /* Delay the actual enabling to let pageflipping cease and the
394 * display to settle before starting the compression. Note that
395 * this delay also serves a second purpose: it allows for a
396 * vblank to pass after disabling the FBC before we attempt
397 * to modify the control registers.
399 * A more complicated solution would involve tracking vblanks
400 * following the termination of the page-flipping sequence
401 * and indeed performing the enable as a co-routine and not
402 * waiting synchronously upon the vblank.
404 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
406 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
409 static void __intel_fbc_disable(struct drm_i915_private
*dev_priv
)
411 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
413 intel_fbc_cancel_work(dev_priv
);
415 dev_priv
->fbc
.disable_fbc(dev_priv
);
416 dev_priv
->fbc
.crtc
= NULL
;
420 * intel_fbc_disable - disable FBC
421 * @dev_priv: i915 device instance
423 * This function disables FBC.
425 void intel_fbc_disable(struct drm_i915_private
*dev_priv
)
427 if (!dev_priv
->fbc
.enable_fbc
)
430 mutex_lock(&dev_priv
->fbc
.lock
);
431 __intel_fbc_disable(dev_priv
);
432 mutex_unlock(&dev_priv
->fbc
.lock
);
436 * intel_fbc_disable_crtc - disable FBC if it's associated with crtc
439 * This function disables FBC if it's associated with the provided CRTC.
441 void intel_fbc_disable_crtc(struct intel_crtc
*crtc
)
443 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
445 if (!dev_priv
->fbc
.enable_fbc
)
448 mutex_lock(&dev_priv
->fbc
.lock
);
449 if (dev_priv
->fbc
.crtc
== crtc
)
450 __intel_fbc_disable(dev_priv
);
451 mutex_unlock(&dev_priv
->fbc
.lock
);
454 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason
)
458 return "FBC enabled but currently disabled in hardware";
459 case FBC_UNSUPPORTED
:
460 return "unsupported by this chipset";
463 case FBC_STOLEN_TOO_SMALL
:
464 return "not enough stolen memory";
465 case FBC_UNSUPPORTED_MODE
:
466 return "mode incompatible with compression";
467 case FBC_MODE_TOO_LARGE
:
468 return "mode too large for compression";
470 return "FBC unsupported on plane";
472 return "framebuffer not tiled or fenced";
473 case FBC_MULTIPLE_PIPES
:
474 return "more than one pipe active";
475 case FBC_MODULE_PARAM
:
476 return "disabled per module param";
477 case FBC_CHIP_DEFAULT
:
478 return "disabled per chip default";
480 return "rotation unsupported";
481 case FBC_IN_DBG_MASTER
:
482 return "Kernel debugger is active";
484 return "framebuffer stride not supported";
486 MISSING_CASE(reason
);
487 return "unknown reason";
491 static void set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
492 enum no_fbc_reason reason
)
494 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
497 dev_priv
->fbc
.no_fbc_reason
= reason
;
498 DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason
));
501 static struct drm_crtc
*intel_fbc_find_crtc(struct drm_i915_private
*dev_priv
)
503 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
505 bool pipe_a_only
= false;
507 if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)
510 for_each_pipe(dev_priv
, pipe
) {
511 tmp_crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
513 if (intel_crtc_active(tmp_crtc
) &&
514 to_intel_plane_state(tmp_crtc
->primary
->state
)->visible
)
521 if (!crtc
|| crtc
->primary
->fb
== NULL
)
527 static bool multiple_pipes_ok(struct drm_i915_private
*dev_priv
)
531 struct drm_crtc
*crtc
;
533 if (INTEL_INFO(dev_priv
)->gen
> 4)
536 for_each_pipe(dev_priv
, pipe
) {
537 crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
539 if (intel_crtc_active(crtc
) &&
540 to_intel_plane_state(crtc
->primary
->state
)->visible
)
544 return (n_pipes
< 2);
547 static int find_compression_threshold(struct drm_i915_private
*dev_priv
,
548 struct drm_mm_node
*node
,
552 int compression_threshold
= 1;
556 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
557 * reserved range size, so it always assumes the maximum (8mb) is used.
558 * If we enable FBC using a CFB on that memory range we'll get FIFO
559 * underruns, even if that range is not reserved by the BIOS. */
560 if (IS_BROADWELL(dev_priv
) || IS_SKYLAKE(dev_priv
))
561 end
= dev_priv
->gtt
.stolen_size
- 8 * 1024 * 1024;
563 end
= dev_priv
->gtt
.stolen_usable_size
;
565 /* HACK: This code depends on what we will do in *_enable_fbc. If that
566 * code changes, this code needs to change as well.
568 * The enable_fbc code will attempt to use one of our 2 compression
569 * thresholds, therefore, in that case, we only have 1 resort.
572 /* Try to over-allocate to reduce reallocations and fragmentation. */
573 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
<<= 1,
576 return compression_threshold
;
579 /* HW's ability to limit the CFB is 1:4 */
580 if (compression_threshold
> 4 ||
581 (fb_cpp
== 2 && compression_threshold
== 2))
584 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
>>= 1,
586 if (ret
&& INTEL_INFO(dev_priv
)->gen
<= 4) {
589 compression_threshold
<<= 1;
592 return compression_threshold
;
596 static int intel_fbc_alloc_cfb(struct drm_i915_private
*dev_priv
, int size
,
599 struct drm_mm_node
*uninitialized_var(compressed_llb
);
602 ret
= find_compression_threshold(dev_priv
, &dev_priv
->fbc
.compressed_fb
,
607 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
611 dev_priv
->fbc
.threshold
= ret
;
613 if (INTEL_INFO(dev_priv
)->gen
>= 5)
614 I915_WRITE(ILK_DPFC_CB_BASE
, dev_priv
->fbc
.compressed_fb
.start
);
615 else if (IS_GM45(dev_priv
)) {
616 I915_WRITE(DPFC_CB_BASE
, dev_priv
->fbc
.compressed_fb
.start
);
618 compressed_llb
= kzalloc(sizeof(*compressed_llb
), GFP_KERNEL
);
622 ret
= i915_gem_stolen_insert_node(dev_priv
, compressed_llb
,
627 dev_priv
->fbc
.compressed_llb
= compressed_llb
;
629 I915_WRITE(FBC_CFB_BASE
,
630 dev_priv
->mm
.stolen_base
+ dev_priv
->fbc
.compressed_fb
.start
);
631 I915_WRITE(FBC_LL_BASE
,
632 dev_priv
->mm
.stolen_base
+ compressed_llb
->start
);
635 dev_priv
->fbc
.uncompressed_size
= size
;
637 DRM_DEBUG_KMS("reserved %d bytes of contiguous stolen space for FBC\n",
643 kfree(compressed_llb
);
644 i915_gem_stolen_remove_node(dev_priv
, &dev_priv
->fbc
.compressed_fb
);
646 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size
);
650 static void __intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
652 if (dev_priv
->fbc
.uncompressed_size
== 0)
655 i915_gem_stolen_remove_node(dev_priv
, &dev_priv
->fbc
.compressed_fb
);
657 if (dev_priv
->fbc
.compressed_llb
) {
658 i915_gem_stolen_remove_node(dev_priv
,
659 dev_priv
->fbc
.compressed_llb
);
660 kfree(dev_priv
->fbc
.compressed_llb
);
663 dev_priv
->fbc
.uncompressed_size
= 0;
666 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
668 if (!dev_priv
->fbc
.enable_fbc
)
671 mutex_lock(&dev_priv
->fbc
.lock
);
672 __intel_fbc_cleanup_cfb(dev_priv
);
673 mutex_unlock(&dev_priv
->fbc
.lock
);
676 static int intel_fbc_setup_cfb(struct drm_i915_private
*dev_priv
, int size
,
679 if (size
<= dev_priv
->fbc
.uncompressed_size
)
682 /* Release any current block */
683 __intel_fbc_cleanup_cfb(dev_priv
);
685 return intel_fbc_alloc_cfb(dev_priv
, size
, fb_cpp
);
688 static bool stride_is_valid(struct drm_i915_private
*dev_priv
,
691 /* These should have been caught earlier. */
692 WARN_ON(stride
< 512);
693 WARN_ON((stride
& (64 - 1)) != 0);
695 /* Below are the additional FBC restrictions. */
697 if (IS_GEN2(dev_priv
) || IS_GEN3(dev_priv
))
698 return stride
== 4096 || stride
== 8192;
700 if (IS_GEN4(dev_priv
) && !IS_G4X(dev_priv
) && stride
< 2048)
710 * __intel_fbc_update - enable/disable FBC as needed, unlocked
711 * @dev_priv: i915 device instance
713 * Set up the framebuffer compression hardware at mode set time. We
714 * enable it if possible:
715 * - plane A only (on pre-965)
716 * - no pixel mulitply/line duplication
717 * - no alpha buffer discard
719 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
721 * We can't assume that any compression will take place (worst case),
722 * so the compressed buffer has to be the same size as the uncompressed
723 * one. It also must reside (along with the line length buffer) in
726 * We need to enable/disable FBC on a global basis.
728 static void __intel_fbc_update(struct drm_i915_private
*dev_priv
)
730 struct drm_crtc
*crtc
= NULL
;
731 struct intel_crtc
*intel_crtc
;
732 struct drm_framebuffer
*fb
;
733 struct drm_i915_gem_object
*obj
;
734 const struct drm_display_mode
*adjusted_mode
;
735 unsigned int max_width
, max_height
;
737 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
739 /* disable framebuffer compression in vGPU */
740 if (intel_vgpu_active(dev_priv
->dev
))
743 if (i915
.enable_fbc
< 0) {
744 set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
);
748 if (!i915
.enable_fbc
) {
749 set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
);
754 * If FBC is already on, we just have to verify that we can
755 * keep it that way...
756 * Need to disable if:
757 * - more than one pipe is active
758 * - changing FBC params (stride, fence, mode)
759 * - new fb is too large to fit in compressed buffer
760 * - going to an unsupported config (interlace, pixel multiply, etc.)
762 crtc
= intel_fbc_find_crtc(dev_priv
);
764 set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
);
768 if (!multiple_pipes_ok(dev_priv
)) {
769 set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
);
773 intel_crtc
= to_intel_crtc(crtc
);
774 fb
= crtc
->primary
->fb
;
775 obj
= intel_fb_obj(fb
);
776 adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
778 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
779 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
780 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
);
784 if (INTEL_INFO(dev_priv
)->gen
>= 8 || IS_HASWELL(dev_priv
)) {
787 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
794 if (intel_crtc
->config
->pipe_src_w
> max_width
||
795 intel_crtc
->config
->pipe_src_h
> max_height
) {
796 set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
);
799 if ((INTEL_INFO(dev_priv
)->gen
< 4 || HAS_DDI(dev_priv
)) &&
800 intel_crtc
->plane
!= PLANE_A
) {
801 set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
);
805 /* The use of a CPU fence is mandatory in order to detect writes
806 * by the CPU to the scanout and trigger updates to the FBC.
808 if (obj
->tiling_mode
!= I915_TILING_X
||
809 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
810 set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
);
813 if (INTEL_INFO(dev_priv
)->gen
<= 4 && !IS_G4X(dev_priv
) &&
814 crtc
->primary
->state
->rotation
!= BIT(DRM_ROTATE_0
)) {
815 set_no_fbc_reason(dev_priv
, FBC_ROTATION
);
819 if (!stride_is_valid(dev_priv
, fb
->pitches
[0])) {
820 set_no_fbc_reason(dev_priv
, FBC_BAD_STRIDE
);
824 /* If the kernel debugger is active, always disable compression */
825 if (in_dbg_master()) {
826 set_no_fbc_reason(dev_priv
, FBC_IN_DBG_MASTER
);
830 if (intel_fbc_setup_cfb(dev_priv
, obj
->base
.size
,
831 drm_format_plane_cpp(fb
->pixel_format
, 0))) {
832 set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
);
836 /* If the scanout has not changed, don't modify the FBC settings.
837 * Note that we make the fundamental assumption that the fb->obj
838 * cannot be unpinned (and have its GTT offset and fence revoked)
839 * without first being decoupled from the scanout and FBC disabled.
841 if (dev_priv
->fbc
.crtc
== intel_crtc
&&
842 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
843 dev_priv
->fbc
.y
== crtc
->y
)
846 if (intel_fbc_enabled(dev_priv
)) {
847 /* We update FBC along two paths, after changing fb/crtc
848 * configuration (modeswitching) and after page-flipping
849 * finishes. For the latter, we know that not only did
850 * we disable the FBC at the start of the page-flip
851 * sequence, but also more than one vblank has passed.
853 * For the former case of modeswitching, it is possible
854 * to switch between two FBC valid configurations
855 * instantaneously so we do need to disable the FBC
856 * before we can modify its control registers. We also
857 * have to wait for the next vblank for that to take
858 * effect. However, since we delay enabling FBC we can
859 * assume that a vblank has passed since disabling and
860 * that we can safely alter the registers in the deferred
863 * In the scenario that we go from a valid to invalid
864 * and then back to valid FBC configuration we have
865 * no strict enforcement that a vblank occurred since
866 * disabling the FBC. However, along all current pipe
867 * disabling paths we do need to wait for a vblank at
868 * some point. And we wait before enabling FBC anyway.
870 DRM_DEBUG_KMS("disabling active FBC for update\n");
871 __intel_fbc_disable(dev_priv
);
874 intel_fbc_schedule_enable(intel_crtc
);
875 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
879 /* Multiple disables should be harmless */
880 if (intel_fbc_enabled(dev_priv
)) {
881 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
882 __intel_fbc_disable(dev_priv
);
884 __intel_fbc_cleanup_cfb(dev_priv
);
888 * intel_fbc_update - enable/disable FBC as needed
889 * @dev_priv: i915 device instance
891 * This function reevaluates the overall state and enables or disables FBC.
893 void intel_fbc_update(struct drm_i915_private
*dev_priv
)
895 if (!dev_priv
->fbc
.enable_fbc
)
898 mutex_lock(&dev_priv
->fbc
.lock
);
899 __intel_fbc_update(dev_priv
);
900 mutex_unlock(&dev_priv
->fbc
.lock
);
903 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
904 unsigned int frontbuffer_bits
,
905 enum fb_op_origin origin
)
907 unsigned int fbc_bits
;
909 if (!dev_priv
->fbc
.enable_fbc
)
912 if (origin
== ORIGIN_GTT
)
915 mutex_lock(&dev_priv
->fbc
.lock
);
917 if (dev_priv
->fbc
.enabled
)
918 fbc_bits
= INTEL_FRONTBUFFER_PRIMARY(dev_priv
->fbc
.crtc
->pipe
);
919 else if (dev_priv
->fbc
.fbc_work
)
920 fbc_bits
= INTEL_FRONTBUFFER_PRIMARY(
921 dev_priv
->fbc
.fbc_work
->crtc
->pipe
);
923 fbc_bits
= dev_priv
->fbc
.possible_framebuffer_bits
;
925 dev_priv
->fbc
.busy_bits
|= (fbc_bits
& frontbuffer_bits
);
927 if (dev_priv
->fbc
.busy_bits
)
928 __intel_fbc_disable(dev_priv
);
930 mutex_unlock(&dev_priv
->fbc
.lock
);
933 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
934 unsigned int frontbuffer_bits
, enum fb_op_origin origin
)
936 if (!dev_priv
->fbc
.enable_fbc
)
939 if (origin
== ORIGIN_GTT
)
942 mutex_lock(&dev_priv
->fbc
.lock
);
944 dev_priv
->fbc
.busy_bits
&= ~frontbuffer_bits
;
946 if (!dev_priv
->fbc
.busy_bits
) {
947 __intel_fbc_disable(dev_priv
);
948 __intel_fbc_update(dev_priv
);
951 mutex_unlock(&dev_priv
->fbc
.lock
);
955 * intel_fbc_init - Initialize FBC
956 * @dev_priv: the i915 device
958 * This function might be called during PM init process.
960 void intel_fbc_init(struct drm_i915_private
*dev_priv
)
964 mutex_init(&dev_priv
->fbc
.lock
);
966 if (!HAS_FBC(dev_priv
)) {
967 dev_priv
->fbc
.enabled
= false;
968 dev_priv
->fbc
.no_fbc_reason
= FBC_UNSUPPORTED
;
972 for_each_pipe(dev_priv
, pipe
) {
973 dev_priv
->fbc
.possible_framebuffer_bits
|=
974 INTEL_FRONTBUFFER_PRIMARY(pipe
);
976 if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)
980 if (INTEL_INFO(dev_priv
)->gen
>= 7) {
981 dev_priv
->fbc
.fbc_enabled
= ilk_fbc_enabled
;
982 dev_priv
->fbc
.enable_fbc
= gen7_fbc_enable
;
983 dev_priv
->fbc
.disable_fbc
= ilk_fbc_disable
;
984 } else if (INTEL_INFO(dev_priv
)->gen
>= 5) {
985 dev_priv
->fbc
.fbc_enabled
= ilk_fbc_enabled
;
986 dev_priv
->fbc
.enable_fbc
= ilk_fbc_enable
;
987 dev_priv
->fbc
.disable_fbc
= ilk_fbc_disable
;
988 } else if (IS_GM45(dev_priv
)) {
989 dev_priv
->fbc
.fbc_enabled
= g4x_fbc_enabled
;
990 dev_priv
->fbc
.enable_fbc
= g4x_fbc_enable
;
991 dev_priv
->fbc
.disable_fbc
= g4x_fbc_disable
;
993 dev_priv
->fbc
.fbc_enabled
= i8xx_fbc_enabled
;
994 dev_priv
->fbc
.enable_fbc
= i8xx_fbc_enable
;
995 dev_priv
->fbc
.disable_fbc
= i8xx_fbc_disable
;
997 /* This value was pulled out of someone's hat */
998 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
1001 dev_priv
->fbc
.enabled
= dev_priv
->fbc
.fbc_enabled(dev_priv
);