2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
29 #include <linux/firmware.h>
31 #include "intel_guc.h"
34 * DOC: GuC-specific firmware loader
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE
);
65 /* User-friendly representation of an enum */
66 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status
)
69 case GUC_FIRMWARE_FAIL
:
71 case GUC_FIRMWARE_NONE
:
73 case GUC_FIRMWARE_PENDING
:
75 case GUC_FIRMWARE_SUCCESS
:
82 static void direct_interrupts_to_host(struct drm_i915_private
*dev_priv
)
84 struct intel_engine_cs
*ring
;
87 /* tell all command streamers NOT to forward interrupts and vblank to GuC */
88 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_NEVER
);
89 irqs
|= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING
);
90 for_each_ring(ring
, dev_priv
, i
)
91 I915_WRITE(RING_MODE_GEN7(ring
), irqs
);
93 /* route all GT interrupts to the host */
94 I915_WRITE(GUC_BCS_RCS_IER
, 0);
95 I915_WRITE(GUC_VCS2_VCS1_IER
, 0);
96 I915_WRITE(GUC_WD_VECS_IER
, 0);
99 static void direct_interrupts_to_guc(struct drm_i915_private
*dev_priv
)
101 struct intel_engine_cs
*ring
;
104 /* tell all command streamers to forward interrupts and vblank to GuC */
105 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_ALWAYS
);
106 irqs
|= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING
);
107 for_each_ring(ring
, dev_priv
, i
)
108 I915_WRITE(RING_MODE_GEN7(ring
), irqs
);
110 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
111 irqs
= GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
112 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
113 /* These three registers have the same bit definitions */
114 I915_WRITE(GUC_BCS_RCS_IER
, ~irqs
);
115 I915_WRITE(GUC_VCS2_VCS1_IER
, ~irqs
);
116 I915_WRITE(GUC_WD_VECS_IER
, ~irqs
);
119 static u32
get_gttype(struct drm_i915_private
*dev_priv
)
121 /* XXX: GT type based on PCI device ID? field seems unused by fw */
125 static u32
get_core_family(struct drm_i915_private
*dev_priv
)
127 switch (INTEL_INFO(dev_priv
)->gen
) {
129 return GFXCORE_FAMILY_GEN9
;
132 DRM_ERROR("GUC: unsupported core family\n");
133 return GFXCORE_FAMILY_UNKNOWN
;
137 static void set_guc_init_params(struct drm_i915_private
*dev_priv
)
139 struct intel_guc
*guc
= &dev_priv
->guc
;
140 u32 params
[GUC_CTL_MAX_DWORDS
];
143 memset(¶ms
, 0, sizeof(params
));
145 params
[GUC_CTL_DEVICE_INFO
] |=
146 (get_gttype(dev_priv
) << GUC_CTL_GTTYPE_SHIFT
) |
147 (get_core_family(dev_priv
) << GUC_CTL_COREFAMILY_SHIFT
);
150 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
151 * second. This ARAR is calculated by:
152 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
154 params
[GUC_CTL_ARAT_HIGH
] = 0;
155 params
[GUC_CTL_ARAT_LOW
] = 100000000;
157 params
[GUC_CTL_WA
] |= GUC_CTL_WA_UK_BY_DRIVER
;
159 params
[GUC_CTL_FEATURE
] |= GUC_CTL_DISABLE_SCHEDULER
|
160 GUC_CTL_VCS2_ENABLED
;
162 if (i915
.guc_log_level
>= 0) {
163 params
[GUC_CTL_LOG_PARAMS
] = guc
->log_flags
;
164 params
[GUC_CTL_DEBUG
] =
165 i915
.guc_log_level
<< GUC_LOG_VERBOSITY_SHIFT
;
168 /* If GuC submission is enabled, set up additional parameters here */
169 if (i915
.enable_guc_submission
) {
170 u32 pgs
= i915_gem_obj_ggtt_offset(dev_priv
->guc
.ctx_pool_obj
);
171 u32 ctx_in_16
= GUC_MAX_GPU_CONTEXTS
/ 16;
174 params
[GUC_CTL_CTXINFO
] = (pgs
<< GUC_CTL_BASE_ADDR_SHIFT
) |
175 (ctx_in_16
<< GUC_CTL_CTXNUM_IN16_SHIFT
);
177 params
[GUC_CTL_FEATURE
] |= GUC_CTL_KERNEL_SUBMISSIONS
;
179 /* Unmask this bit to enable the GuC's internal scheduler */
180 params
[GUC_CTL_FEATURE
] &= ~GUC_CTL_DISABLE_SCHEDULER
;
183 I915_WRITE(SOFT_SCRATCH(0), 0);
185 for (i
= 0; i
< GUC_CTL_MAX_DWORDS
; i
++)
186 I915_WRITE(SOFT_SCRATCH(1 + i
), params
[i
]);
190 * Read the GuC status register (GUC_STATUS) and store it in the
191 * specified location; then return a boolean indicating whether
192 * the value matches either of two values representing completion
193 * of the GuC boot process.
195 * This is used for polling the GuC status in a wait_for_atomic()
198 static inline bool guc_ucode_response(struct drm_i915_private
*dev_priv
,
201 u32 val
= I915_READ(GUC_STATUS
);
202 u32 uk_val
= val
& GS_UKERNEL_MASK
;
204 return (uk_val
== GS_UKERNEL_READY
||
205 ((val
& GS_MIA_CORE_STATE
) && uk_val
== GS_UKERNEL_LAPIC_DONE
));
209 * Transfer the firmware image to RAM for execution by the microcontroller.
211 * Architecturally, the DMA engine is bidirectional, and can potentially even
212 * transfer between GTT locations. This functionality is left out of the API
213 * for now as there is no need for it.
215 * Note that GuC needs the CSS header plus uKernel code to be copied by the
216 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
218 static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv
)
220 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
221 struct drm_i915_gem_object
*fw_obj
= guc_fw
->guc_fw_obj
;
222 unsigned long offset
;
223 struct sg_table
*sg
= fw_obj
->pages
;
224 u32 status
, rsa
[UOS_RSA_SCRATCH_MAX_COUNT
];
227 /* where RSA signature starts */
228 offset
= guc_fw
->rsa_offset
;
230 /* Copy RSA signature from the fw image to HW for verification */
231 sg_pcopy_to_buffer(sg
->sgl
, sg
->nents
, rsa
, sizeof(rsa
), offset
);
232 for (i
= 0; i
< UOS_RSA_SCRATCH_MAX_COUNT
; i
++)
233 I915_WRITE(UOS_RSA_SCRATCH(i
), rsa
[i
]);
235 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
236 * other components */
237 I915_WRITE(DMA_COPY_SIZE
, guc_fw
->header_size
+ guc_fw
->ucode_size
);
239 /* Set the source address for the new blob */
240 offset
= i915_gem_obj_ggtt_offset(fw_obj
) + guc_fw
->header_offset
;
241 I915_WRITE(DMA_ADDR_0_LOW
, lower_32_bits(offset
));
242 I915_WRITE(DMA_ADDR_0_HIGH
, upper_32_bits(offset
) & 0xFFFF);
245 * Set the DMA destination. Current uCode expects the code to be
246 * loaded at 8k; locations below this are used for the stack.
248 I915_WRITE(DMA_ADDR_1_LOW
, 0x2000);
249 I915_WRITE(DMA_ADDR_1_HIGH
, DMA_ADDRESS_SPACE_WOPCM
);
251 /* Finally start the DMA */
252 I915_WRITE(DMA_CTRL
, _MASKED_BIT_ENABLE(UOS_MOVE
| START_DMA
));
255 * Spin-wait for the DMA to complete & the GuC to start up.
256 * NB: Docs recommend not using the interrupt for completion.
257 * Measurements indicate this should take no more than 20ms, so a
258 * timeout here indicates that the GuC has failed and is unusable.
259 * (Higher levels of the driver will attempt to fall back to
260 * execlist mode if this happens.)
262 ret
= wait_for_atomic(guc_ucode_response(dev_priv
, &status
), 100);
264 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
265 I915_READ(DMA_CTRL
), status
);
267 if ((status
& GS_BOOTROM_MASK
) == GS_BOOTROM_RSA_FAILED
) {
268 DRM_ERROR("GuC firmware signature verification failed\n");
272 DRM_DEBUG_DRIVER("returning %d\n", ret
);
278 * Load the GuC firmware blob into the MinuteIA.
280 static int guc_ucode_xfer(struct drm_i915_private
*dev_priv
)
282 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
283 struct drm_device
*dev
= dev_priv
->dev
;
286 ret
= i915_gem_object_set_to_gtt_domain(guc_fw
->guc_fw_obj
, false);
288 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret
);
292 ret
= i915_gem_obj_ggtt_pin(guc_fw
->guc_fw_obj
, 0, 0);
294 DRM_DEBUG_DRIVER("pin failed %d\n", ret
);
298 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
299 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
301 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
304 I915_WRITE(GUC_WOPCM_SIZE
, GUC_WOPCM_SIZE_VALUE
);
305 I915_WRITE(DMA_GUC_WOPCM_OFFSET
, GUC_WOPCM_OFFSET_VALUE
);
307 /* Enable MIA caching. GuC clock gating is disabled. */
308 I915_WRITE(GUC_SHIM_CONTROL
, GUC_SHIM_CONTROL_VALUE
);
310 /* WaDisableMinuteIaClockGating:skl,bxt */
311 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
312 IS_BXT_REVID(dev
, 0, BXT_REVID_A0
)) {
313 I915_WRITE(GUC_SHIM_CONTROL
, (I915_READ(GUC_SHIM_CONTROL
) &
314 ~GUC_ENABLE_MIA_CLOCK_GATING
));
317 /* WaC6DisallowByGfxPause*/
318 I915_WRITE(GEN6_GFXPAUSE
, 0x30FFF);
321 I915_WRITE(GEN9LP_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
323 I915_WRITE(GEN9_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
326 /* DOP Clock Gating Enable for GuC clocks */
327 I915_WRITE(GEN7_MISCCPCTL
, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE
|
328 I915_READ(GEN7_MISCCPCTL
)));
330 /* allows for 5us before GT can go to RC6 */
331 I915_WRITE(GUC_ARAT_C6DIS
, 0x1FF);
334 set_guc_init_params(dev_priv
);
336 ret
= guc_ucode_xfer_dma(dev_priv
);
338 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
341 * We keep the object pages for reuse during resume. But we can unpin it
342 * now that DMA has completed, so it doesn't continue to take up space.
344 i915_gem_object_ggtt_unpin(guc_fw
->guc_fw_obj
);
350 * intel_guc_ucode_load() - load GuC uCode into the device
353 * Called from gem_init_hw() during driver loading and also after a GPU reset.
355 * The firmware image should have already been fetched into memory by the
356 * earlier call to intel_guc_ucode_init(), so here we need only check that
357 * is succeeded, and then transfer the image to the h/w.
359 * Return: non-zero code on error
361 int intel_guc_ucode_load(struct drm_device
*dev
)
363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
364 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
367 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
368 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
369 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
371 direct_interrupts_to_host(dev_priv
);
373 if (guc_fw
->guc_fw_fetch_status
== GUC_FIRMWARE_NONE
)
376 if (guc_fw
->guc_fw_fetch_status
== GUC_FIRMWARE_SUCCESS
&&
377 guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_FAIL
)
380 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_PENDING
;
382 DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
383 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
385 switch (guc_fw
->guc_fw_fetch_status
) {
386 case GUC_FIRMWARE_FAIL
:
387 /* something went wrong :( */
391 case GUC_FIRMWARE_NONE
:
392 case GUC_FIRMWARE_PENDING
:
395 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
397 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
398 guc_fw
->guc_fw_fetch_status
);
402 case GUC_FIRMWARE_SUCCESS
:
406 err
= i915_guc_submission_init(dev
);
410 err
= guc_ucode_xfer(dev_priv
);
414 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_SUCCESS
;
416 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
417 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
418 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
420 if (i915
.enable_guc_submission
) {
421 /* The execbuf_client will be recreated. Release it first. */
422 i915_guc_submission_disable(dev
);
424 err
= i915_guc_submission_enable(dev
);
427 direct_interrupts_to_guc(dev_priv
);
433 if (guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_PENDING
)
434 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_FAIL
;
436 direct_interrupts_to_host(dev_priv
);
437 i915_guc_submission_disable(dev
);
442 static void guc_fw_fetch(struct drm_device
*dev
, struct intel_guc_fw
*guc_fw
)
444 struct drm_i915_gem_object
*obj
;
445 const struct firmware
*fw
;
446 struct guc_css_header
*css
;
450 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
451 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
453 err
= request_firmware(&fw
, guc_fw
->guc_fw_path
, &dev
->pdev
->dev
);
459 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
460 guc_fw
->guc_fw_path
, fw
);
462 /* Check the size of the blob before examining buffer contents */
463 if (fw
->size
< sizeof(struct guc_css_header
)) {
464 DRM_ERROR("Firmware header is missing\n");
468 css
= (struct guc_css_header
*)fw
->data
;
470 /* Firmware bits always start from header */
471 guc_fw
->header_offset
= 0;
472 guc_fw
->header_size
= (css
->header_size_dw
- css
->modulus_size_dw
-
473 css
->key_size_dw
- css
->exponent_size_dw
) * sizeof(u32
);
475 if (guc_fw
->header_size
!= sizeof(struct guc_css_header
)) {
476 DRM_ERROR("CSS header definition mismatch\n");
481 guc_fw
->ucode_offset
= guc_fw
->header_offset
+ guc_fw
->header_size
;
482 guc_fw
->ucode_size
= (css
->size_dw
- css
->header_size_dw
) * sizeof(u32
);
485 if (css
->key_size_dw
!= UOS_RSA_SCRATCH_MAX_COUNT
) {
486 DRM_ERROR("RSA key size is bad\n");
489 guc_fw
->rsa_offset
= guc_fw
->ucode_offset
+ guc_fw
->ucode_size
;
490 guc_fw
->rsa_size
= css
->key_size_dw
* sizeof(u32
);
492 /* At least, it should have header, uCode and RSA. Size of all three. */
493 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
+ guc_fw
->rsa_size
;
494 if (fw
->size
< size
) {
495 DRM_ERROR("Missing firmware components\n");
499 /* Header and uCode will be loaded to WOPCM. Size of the two. */
500 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
;
502 /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
503 if (size
> GUC_WOPCM_SIZE_VALUE
- 0x8000) {
504 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
509 * The GuC firmware image has the version number embedded at a well-known
510 * offset within the firmware blob; note that major / minor version are
511 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
512 * in terms of bytes (u8).
514 guc_fw
->guc_fw_major_found
= css
->guc_sw_version
>> 16;
515 guc_fw
->guc_fw_minor_found
= css
->guc_sw_version
& 0xFFFF;
517 if (guc_fw
->guc_fw_major_found
!= guc_fw
->guc_fw_major_wanted
||
518 guc_fw
->guc_fw_minor_found
< guc_fw
->guc_fw_minor_wanted
) {
519 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
520 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
521 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
526 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
527 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
528 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
530 obj
= i915_gem_object_create_from_data(dev
, fw
->data
, fw
->size
);
531 if (IS_ERR_OR_NULL(obj
)) {
532 err
= obj
? PTR_ERR(obj
) : -ENOMEM
;
536 guc_fw
->guc_fw_obj
= obj
;
537 guc_fw
->guc_fw_size
= fw
->size
;
539 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
542 release_firmware(fw
);
543 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_SUCCESS
;
547 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
548 err
, fw
, guc_fw
->guc_fw_obj
);
549 DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
550 guc_fw
->guc_fw_path
, err
);
552 obj
= guc_fw
->guc_fw_obj
;
554 drm_gem_object_unreference(&obj
->base
);
555 guc_fw
->guc_fw_obj
= NULL
;
557 release_firmware(fw
); /* OK even if fw is NULL */
558 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_FAIL
;
562 * intel_guc_ucode_init() - define parameters and fetch firmware
565 * Called early during driver load, but after GEM is initialised.
566 * The device struct_mutex must be held by the caller, as we're
567 * going to allocate a GEM object to hold the firmware image.
569 * The firmware will be transferred to the GuC's memory later,
570 * when intel_guc_ucode_load() is called.
572 void intel_guc_ucode_init(struct drm_device
*dev
)
574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
575 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
578 if (!HAS_GUC_SCHED(dev
))
579 i915
.enable_guc_submission
= false;
581 if (!HAS_GUC_UCODE(dev
)) {
583 } else if (IS_SKYLAKE(dev
)) {
584 fw_path
= I915_SKL_GUC_UCODE
;
585 guc_fw
->guc_fw_major_wanted
= 4;
586 guc_fw
->guc_fw_minor_wanted
= 3;
588 i915
.enable_guc_submission
= false;
589 fw_path
= ""; /* unknown device */
592 guc_fw
->guc_dev
= dev
;
593 guc_fw
->guc_fw_path
= fw_path
;
594 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;
595 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_NONE
;
600 if (*fw_path
== '\0') {
601 DRM_ERROR("No GuC firmware known for this platform\n");
602 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_FAIL
;
606 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_PENDING
;
607 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path
);
608 guc_fw_fetch(dev
, guc_fw
);
609 /* status must now be FAIL or SUCCESS */
613 * intel_guc_ucode_fini() - clean up all allocated resources
616 void intel_guc_ucode_fini(struct drm_device
*dev
)
618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
619 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
621 direct_interrupts_to_host(dev_priv
);
622 i915_guc_submission_fini(dev
);
624 if (guc_fw
->guc_fw_obj
)
625 drm_gem_object_unreference(&guc_fw
->guc_fw_obj
->base
);
626 guc_fw
->guc_fw_obj
= NULL
;
628 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;