2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
29 #include <linux/firmware.h>
31 #include "intel_guc.h"
34 * DOC: GuC-specific firmware loader
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin"
63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE
);
65 #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
66 MODULE_FIRMWARE(I915_BXT_GUC_UCODE
);
68 #define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin"
69 MODULE_FIRMWARE(I915_KBL_GUC_UCODE
);
71 /* User-friendly representation of an enum */
72 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status
)
75 case GUC_FIRMWARE_FAIL
:
77 case GUC_FIRMWARE_NONE
:
79 case GUC_FIRMWARE_PENDING
:
81 case GUC_FIRMWARE_SUCCESS
:
88 static void direct_interrupts_to_host(struct drm_i915_private
*dev_priv
)
90 struct intel_engine_cs
*engine
;
93 /* tell all command streamers NOT to forward interrupts or vblank to GuC */
94 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_NEVER
);
95 irqs
|= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING
);
96 for_each_engine(engine
, dev_priv
)
97 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
99 /* route all GT interrupts to the host */
100 I915_WRITE(GUC_BCS_RCS_IER
, 0);
101 I915_WRITE(GUC_VCS2_VCS1_IER
, 0);
102 I915_WRITE(GUC_WD_VECS_IER
, 0);
105 static void direct_interrupts_to_guc(struct drm_i915_private
*dev_priv
)
107 struct intel_engine_cs
*engine
;
111 /* tell all command streamers to forward interrupts (but not vblank) to GuC */
112 irqs
= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING
);
113 for_each_engine(engine
, dev_priv
)
114 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
116 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
117 irqs
= GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
118 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
119 /* These three registers have the same bit definitions */
120 I915_WRITE(GUC_BCS_RCS_IER
, ~irqs
);
121 I915_WRITE(GUC_VCS2_VCS1_IER
, ~irqs
);
122 I915_WRITE(GUC_WD_VECS_IER
, ~irqs
);
125 * If GuC has routed PM interrupts to itself, don't keep it.
126 * and keep other interrupts those are unmasked by GuC.
128 tmp
= I915_READ(GEN6_PMINTRMSK
);
129 if (tmp
& GEN8_PMINTR_REDIRECT_TO_NON_DISP
) {
130 dev_priv
->rps
.pm_intr_keep
|= ~(tmp
& ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
);
131 dev_priv
->rps
.pm_intr_keep
&= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
135 static u32
get_gttype(struct drm_i915_private
*dev_priv
)
137 /* XXX: GT type based on PCI device ID? field seems unused by fw */
141 static u32
get_core_family(struct drm_i915_private
*dev_priv
)
143 switch (INTEL_INFO(dev_priv
)->gen
) {
145 return GFXCORE_FAMILY_GEN9
;
148 DRM_ERROR("GUC: unsupported core family\n");
149 return GFXCORE_FAMILY_UNKNOWN
;
153 static void set_guc_init_params(struct drm_i915_private
*dev_priv
)
155 struct intel_guc
*guc
= &dev_priv
->guc
;
156 u32 params
[GUC_CTL_MAX_DWORDS
];
159 memset(¶ms
, 0, sizeof(params
));
161 params
[GUC_CTL_DEVICE_INFO
] |=
162 (get_gttype(dev_priv
) << GUC_CTL_GTTYPE_SHIFT
) |
163 (get_core_family(dev_priv
) << GUC_CTL_COREFAMILY_SHIFT
);
166 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
167 * second. This ARAR is calculated by:
168 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
170 params
[GUC_CTL_ARAT_HIGH
] = 0;
171 params
[GUC_CTL_ARAT_LOW
] = 100000000;
173 params
[GUC_CTL_WA
] |= GUC_CTL_WA_UK_BY_DRIVER
;
175 params
[GUC_CTL_FEATURE
] |= GUC_CTL_DISABLE_SCHEDULER
|
176 GUC_CTL_VCS2_ENABLED
;
178 if (i915
.guc_log_level
>= 0) {
179 params
[GUC_CTL_LOG_PARAMS
] = guc
->log_flags
;
180 params
[GUC_CTL_DEBUG
] =
181 i915
.guc_log_level
<< GUC_LOG_VERBOSITY_SHIFT
;
185 u32 ads
= (u32
)i915_gem_obj_ggtt_offset(guc
->ads_obj
)
187 params
[GUC_CTL_DEBUG
] |= ads
<< GUC_ADS_ADDR_SHIFT
;
188 params
[GUC_CTL_DEBUG
] |= GUC_ADS_ENABLED
;
191 /* If GuC submission is enabled, set up additional parameters here */
192 if (i915
.enable_guc_submission
) {
193 u32 pgs
= i915_gem_obj_ggtt_offset(dev_priv
->guc
.ctx_pool_obj
);
194 u32 ctx_in_16
= GUC_MAX_GPU_CONTEXTS
/ 16;
197 params
[GUC_CTL_CTXINFO
] = (pgs
<< GUC_CTL_BASE_ADDR_SHIFT
) |
198 (ctx_in_16
<< GUC_CTL_CTXNUM_IN16_SHIFT
);
200 params
[GUC_CTL_FEATURE
] |= GUC_CTL_KERNEL_SUBMISSIONS
;
202 /* Unmask this bit to enable the GuC's internal scheduler */
203 params
[GUC_CTL_FEATURE
] &= ~GUC_CTL_DISABLE_SCHEDULER
;
206 I915_WRITE(SOFT_SCRATCH(0), 0);
208 for (i
= 0; i
< GUC_CTL_MAX_DWORDS
; i
++)
209 I915_WRITE(SOFT_SCRATCH(1 + i
), params
[i
]);
213 * Read the GuC status register (GUC_STATUS) and store it in the
214 * specified location; then return a boolean indicating whether
215 * the value matches either of two values representing completion
216 * of the GuC boot process.
218 * This is used for polling the GuC status in a wait_for()
221 static inline bool guc_ucode_response(struct drm_i915_private
*dev_priv
,
224 u32 val
= I915_READ(GUC_STATUS
);
225 u32 uk_val
= val
& GS_UKERNEL_MASK
;
227 return (uk_val
== GS_UKERNEL_READY
||
228 ((val
& GS_MIA_CORE_STATE
) && uk_val
== GS_UKERNEL_LAPIC_DONE
));
232 * Transfer the firmware image to RAM for execution by the microcontroller.
234 * Architecturally, the DMA engine is bidirectional, and can potentially even
235 * transfer between GTT locations. This functionality is left out of the API
236 * for now as there is no need for it.
238 * Note that GuC needs the CSS header plus uKernel code to be copied by the
239 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
241 static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv
)
243 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
244 struct drm_i915_gem_object
*fw_obj
= guc_fw
->guc_fw_obj
;
245 unsigned long offset
;
246 struct sg_table
*sg
= fw_obj
->pages
;
247 u32 status
, rsa
[UOS_RSA_SCRATCH_MAX_COUNT
];
250 /* where RSA signature starts */
251 offset
= guc_fw
->rsa_offset
;
253 /* Copy RSA signature from the fw image to HW for verification */
254 sg_pcopy_to_buffer(sg
->sgl
, sg
->nents
, rsa
, sizeof(rsa
), offset
);
255 for (i
= 0; i
< UOS_RSA_SCRATCH_MAX_COUNT
; i
++)
256 I915_WRITE(UOS_RSA_SCRATCH(i
), rsa
[i
]);
258 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
259 * other components */
260 I915_WRITE(DMA_COPY_SIZE
, guc_fw
->header_size
+ guc_fw
->ucode_size
);
262 /* Set the source address for the new blob */
263 offset
= i915_gem_obj_ggtt_offset(fw_obj
) + guc_fw
->header_offset
;
264 I915_WRITE(DMA_ADDR_0_LOW
, lower_32_bits(offset
));
265 I915_WRITE(DMA_ADDR_0_HIGH
, upper_32_bits(offset
) & 0xFFFF);
268 * Set the DMA destination. Current uCode expects the code to be
269 * loaded at 8k; locations below this are used for the stack.
271 I915_WRITE(DMA_ADDR_1_LOW
, 0x2000);
272 I915_WRITE(DMA_ADDR_1_HIGH
, DMA_ADDRESS_SPACE_WOPCM
);
274 /* Finally start the DMA */
275 I915_WRITE(DMA_CTRL
, _MASKED_BIT_ENABLE(UOS_MOVE
| START_DMA
));
278 * Wait for the DMA to complete & the GuC to start up.
279 * NB: Docs recommend not using the interrupt for completion.
280 * Measurements indicate this should take no more than 20ms, so a
281 * timeout here indicates that the GuC has failed and is unusable.
282 * (Higher levels of the driver will attempt to fall back to
283 * execlist mode if this happens.)
285 ret
= wait_for(guc_ucode_response(dev_priv
, &status
), 100);
287 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
288 I915_READ(DMA_CTRL
), status
);
290 if ((status
& GS_BOOTROM_MASK
) == GS_BOOTROM_RSA_FAILED
) {
291 DRM_ERROR("GuC firmware signature verification failed\n");
295 DRM_DEBUG_DRIVER("returning %d\n", ret
);
300 static u32
guc_wopcm_size(struct drm_i915_private
*dev_priv
)
302 u32 wopcm_size
= GUC_WOPCM_TOP
;
304 /* On BXT, the top of WOPCM is reserved for RC6 context */
305 if (IS_BROXTON(dev_priv
))
306 wopcm_size
-= BXT_GUC_WOPCM_RC6_RESERVED
;
312 * Load the GuC firmware blob into the MinuteIA.
314 static int guc_ucode_xfer(struct drm_i915_private
*dev_priv
)
316 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
317 struct drm_device
*dev
= &dev_priv
->drm
;
320 ret
= i915_gem_object_set_to_gtt_domain(guc_fw
->guc_fw_obj
, false);
322 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret
);
326 ret
= i915_gem_obj_ggtt_pin(guc_fw
->guc_fw_obj
, 0, 0);
328 DRM_DEBUG_DRIVER("pin failed %d\n", ret
);
332 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
333 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
335 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
338 I915_WRITE(GUC_WOPCM_SIZE
, guc_wopcm_size(dev_priv
));
339 I915_WRITE(DMA_GUC_WOPCM_OFFSET
, GUC_WOPCM_OFFSET_VALUE
);
341 /* Enable MIA caching. GuC clock gating is disabled. */
342 I915_WRITE(GUC_SHIM_CONTROL
, GUC_SHIM_CONTROL_VALUE
);
344 /* WaDisableMinuteIaClockGating:skl,bxt */
345 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
346 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
347 I915_WRITE(GUC_SHIM_CONTROL
, (I915_READ(GUC_SHIM_CONTROL
) &
348 ~GUC_ENABLE_MIA_CLOCK_GATING
));
351 /* WaC6DisallowByGfxPause*/
352 I915_WRITE(GEN6_GFXPAUSE
, 0x30FFF);
355 I915_WRITE(GEN9LP_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
357 I915_WRITE(GEN9_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
360 /* DOP Clock Gating Enable for GuC clocks */
361 I915_WRITE(GEN7_MISCCPCTL
, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE
|
362 I915_READ(GEN7_MISCCPCTL
)));
364 /* allows for 5us before GT can go to RC6 */
365 I915_WRITE(GUC_ARAT_C6DIS
, 0x1FF);
368 set_guc_init_params(dev_priv
);
370 ret
= guc_ucode_xfer_dma(dev_priv
);
372 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
375 * We keep the object pages for reuse during resume. But we can unpin it
376 * now that DMA has completed, so it doesn't continue to take up space.
378 i915_gem_object_ggtt_unpin(guc_fw
->guc_fw_obj
);
383 static int i915_reset_guc(struct drm_i915_private
*dev_priv
)
388 ret
= intel_guc_reset(dev_priv
);
390 DRM_ERROR("GuC reset failed, ret = %d\n", ret
);
394 guc_status
= I915_READ(GUC_STATUS
);
395 WARN(!(guc_status
& GS_MIA_IN_RESET
),
396 "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status
);
402 * intel_guc_setup() - finish preparing the GuC for activity
405 * Called from gem_init_hw() during driver loading and also after a GPU reset.
407 * The main action required here it to load the GuC uCode into the device.
408 * The firmware image should have already been fetched into memory by the
409 * earlier call to intel_guc_init(), so here we need only check that worked,
410 * and then transfer the image to the h/w.
412 * Return: non-zero code on error
414 int intel_guc_setup(struct drm_device
*dev
)
416 struct drm_i915_private
*dev_priv
= to_i915(dev
);
417 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
418 const char *fw_path
= guc_fw
->guc_fw_path
;
419 int retries
, ret
, err
;
421 DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
423 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
424 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
426 /* Loading forbidden, or no firmware to load? */
427 if (!i915
.enable_guc_loading
) {
430 } else if (fw_path
== NULL
) {
431 /* Device is known to have no uCode (e.g. no GuC) */
434 } else if (*fw_path
== '\0') {
435 /* Device has a GuC but we don't know what f/w to load? */
436 DRM_INFO("No GuC firmware known for this platform\n");
441 /* Fetch failed, or already fetched but failed to load? */
442 if (guc_fw
->guc_fw_fetch_status
!= GUC_FIRMWARE_SUCCESS
) {
445 } else if (guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_FAIL
) {
450 direct_interrupts_to_host(dev_priv
);
452 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_PENDING
;
454 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
455 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
456 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
458 err
= i915_guc_submission_init(dev_priv
);
463 * WaEnableuKernelHeaderValidFix:skl,bxt
464 * For BXT, this is only upto B0 but below WA is required for later
465 * steppings also so this is extended as well.
467 /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
468 for (retries
= 3; ; ) {
470 * Always reset the GuC just before (re)loading, so
471 * that the state and timing are fairly predictable
473 err
= i915_reset_guc(dev_priv
);
475 DRM_ERROR("GuC reset failed: %d\n", err
);
479 err
= guc_ucode_xfer(dev_priv
);
486 DRM_INFO("GuC fw load failed: %d; will reset and "
487 "retry %d more time(s)\n", err
, retries
);
490 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_SUCCESS
;
492 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
493 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
494 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
496 if (i915
.enable_guc_submission
) {
497 err
= i915_guc_submission_enable(dev_priv
);
500 direct_interrupts_to_guc(dev_priv
);
506 if (guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_PENDING
)
507 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_FAIL
;
509 direct_interrupts_to_host(dev_priv
);
510 i915_guc_submission_disable(dev_priv
);
511 i915_guc_submission_fini(dev_priv
);
514 * We've failed to load the firmware :(
516 * Decide whether to disable GuC submission and fall back to
517 * execlist mode, and whether to hide the error by returning
518 * zero or to return -EIO, which the caller will treat as a
519 * nonfatal error (i.e. it doesn't prevent driver load, but
520 * marks the GPU as wedged until reset).
522 if (i915
.enable_guc_loading
> 1) {
524 } else if (i915
.enable_guc_submission
> 1) {
530 if (err
== 0 && !HAS_GUC_UCODE(dev
))
531 ; /* Don't mention the GuC! */
533 DRM_INFO("GuC firmware load skipped\n");
534 else if (ret
!= -EIO
)
535 DRM_INFO("GuC firmware load failed: %d\n", err
);
537 DRM_ERROR("GuC firmware load failed: %d\n", err
);
539 if (i915
.enable_guc_submission
) {
541 DRM_INFO("GuC submission without firmware not supported\n");
543 DRM_INFO("Falling back from GuC submission to execlist mode\n");
545 DRM_ERROR("GuC init failed: %d\n", ret
);
547 i915
.enable_guc_submission
= 0;
552 static void guc_fw_fetch(struct drm_device
*dev
, struct intel_guc_fw
*guc_fw
)
554 struct drm_i915_gem_object
*obj
;
555 const struct firmware
*fw
;
556 struct guc_css_header
*css
;
560 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
561 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
563 err
= request_firmware(&fw
, guc_fw
->guc_fw_path
, &dev
->pdev
->dev
);
569 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
570 guc_fw
->guc_fw_path
, fw
);
572 /* Check the size of the blob before examining buffer contents */
573 if (fw
->size
< sizeof(struct guc_css_header
)) {
574 DRM_ERROR("Firmware header is missing\n");
578 css
= (struct guc_css_header
*)fw
->data
;
580 /* Firmware bits always start from header */
581 guc_fw
->header_offset
= 0;
582 guc_fw
->header_size
= (css
->header_size_dw
- css
->modulus_size_dw
-
583 css
->key_size_dw
- css
->exponent_size_dw
) * sizeof(u32
);
585 if (guc_fw
->header_size
!= sizeof(struct guc_css_header
)) {
586 DRM_ERROR("CSS header definition mismatch\n");
591 guc_fw
->ucode_offset
= guc_fw
->header_offset
+ guc_fw
->header_size
;
592 guc_fw
->ucode_size
= (css
->size_dw
- css
->header_size_dw
) * sizeof(u32
);
595 if (css
->key_size_dw
!= UOS_RSA_SCRATCH_MAX_COUNT
) {
596 DRM_ERROR("RSA key size is bad\n");
599 guc_fw
->rsa_offset
= guc_fw
->ucode_offset
+ guc_fw
->ucode_size
;
600 guc_fw
->rsa_size
= css
->key_size_dw
* sizeof(u32
);
602 /* At least, it should have header, uCode and RSA. Size of all three. */
603 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
+ guc_fw
->rsa_size
;
604 if (fw
->size
< size
) {
605 DRM_ERROR("Missing firmware components\n");
609 /* Header and uCode will be loaded to WOPCM. Size of the two. */
610 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
;
611 if (size
> guc_wopcm_size(to_i915(dev
))) {
612 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
617 * The GuC firmware image has the version number embedded at a well-known
618 * offset within the firmware blob; note that major / minor version are
619 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
620 * in terms of bytes (u8).
622 guc_fw
->guc_fw_major_found
= css
->guc_sw_version
>> 16;
623 guc_fw
->guc_fw_minor_found
= css
->guc_sw_version
& 0xFFFF;
625 if (guc_fw
->guc_fw_major_found
!= guc_fw
->guc_fw_major_wanted
||
626 guc_fw
->guc_fw_minor_found
< guc_fw
->guc_fw_minor_wanted
) {
627 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
628 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
629 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
634 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
635 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
636 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
638 mutex_lock(&dev
->struct_mutex
);
639 obj
= i915_gem_object_create_from_data(dev
, fw
->data
, fw
->size
);
640 mutex_unlock(&dev
->struct_mutex
);
641 if (IS_ERR_OR_NULL(obj
)) {
642 err
= obj
? PTR_ERR(obj
) : -ENOMEM
;
646 guc_fw
->guc_fw_obj
= obj
;
647 guc_fw
->guc_fw_size
= fw
->size
;
649 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
652 release_firmware(fw
);
653 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_SUCCESS
;
657 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
658 err
, fw
, guc_fw
->guc_fw_obj
);
659 DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
660 guc_fw
->guc_fw_path
, err
);
662 mutex_lock(&dev
->struct_mutex
);
663 obj
= guc_fw
->guc_fw_obj
;
665 drm_gem_object_unreference(&obj
->base
);
666 guc_fw
->guc_fw_obj
= NULL
;
667 mutex_unlock(&dev
->struct_mutex
);
669 release_firmware(fw
); /* OK even if fw is NULL */
670 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_FAIL
;
674 * intel_guc_init() - define parameters and fetch firmware
677 * Called early during driver load, but after GEM is initialised.
679 * The firmware will be transferred to the GuC's memory later,
680 * when intel_guc_setup() is called.
682 void intel_guc_init(struct drm_device
*dev
)
684 struct drm_i915_private
*dev_priv
= to_i915(dev
);
685 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
688 /* A negative value means "use platform default" */
689 if (i915
.enable_guc_loading
< 0)
690 i915
.enable_guc_loading
= HAS_GUC_UCODE(dev
);
691 if (i915
.enable_guc_submission
< 0)
692 i915
.enable_guc_submission
= HAS_GUC_SCHED(dev
);
694 if (!HAS_GUC_UCODE(dev
)) {
696 } else if (IS_SKYLAKE(dev
)) {
697 fw_path
= I915_SKL_GUC_UCODE
;
698 guc_fw
->guc_fw_major_wanted
= 6;
699 guc_fw
->guc_fw_minor_wanted
= 1;
700 } else if (IS_BROXTON(dev
)) {
701 fw_path
= I915_BXT_GUC_UCODE
;
702 guc_fw
->guc_fw_major_wanted
= 8;
703 guc_fw
->guc_fw_minor_wanted
= 7;
704 } else if (IS_KABYLAKE(dev
)) {
705 fw_path
= I915_KBL_GUC_UCODE
;
706 guc_fw
->guc_fw_major_wanted
= 9;
707 guc_fw
->guc_fw_minor_wanted
= 14;
709 fw_path
= ""; /* unknown device */
712 guc_fw
->guc_dev
= dev
;
713 guc_fw
->guc_fw_path
= fw_path
;
714 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;
715 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_NONE
;
717 /* Early (and silent) return if GuC loading is disabled */
718 if (!i915
.enable_guc_loading
)
722 if (*fw_path
== '\0')
725 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_PENDING
;
726 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path
);
727 guc_fw_fetch(dev
, guc_fw
);
728 /* status must now be FAIL or SUCCESS */
732 * intel_guc_fini() - clean up all allocated resources
735 void intel_guc_fini(struct drm_device
*dev
)
737 struct drm_i915_private
*dev_priv
= to_i915(dev
);
738 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
740 mutex_lock(&dev
->struct_mutex
);
741 direct_interrupts_to_host(dev_priv
);
742 i915_guc_submission_disable(dev_priv
);
743 i915_guc_submission_fini(dev_priv
);
745 if (guc_fw
->guc_fw_obj
)
746 drm_gem_object_unreference(&guc_fw
->guc_fw_obj
->base
);
747 guc_fw
->guc_fw_obj
= NULL
;
748 mutex_unlock(&dev
->struct_mutex
);
750 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;