2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
29 #include <linux/firmware.h>
31 #include "intel_guc.h"
34 * DOC: GuC-specific firmware loader
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin"
63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE
);
65 #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
66 MODULE_FIRMWARE(I915_BXT_GUC_UCODE
);
68 /* User-friendly representation of an enum */
69 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status
)
72 case GUC_FIRMWARE_FAIL
:
74 case GUC_FIRMWARE_NONE
:
76 case GUC_FIRMWARE_PENDING
:
78 case GUC_FIRMWARE_SUCCESS
:
85 static void direct_interrupts_to_host(struct drm_i915_private
*dev_priv
)
87 struct intel_engine_cs
*engine
;
90 /* tell all command streamers NOT to forward interrupts and vblank to GuC */
91 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_NEVER
);
92 irqs
|= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING
);
93 for_each_engine(engine
, dev_priv
)
94 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
96 /* route all GT interrupts to the host */
97 I915_WRITE(GUC_BCS_RCS_IER
, 0);
98 I915_WRITE(GUC_VCS2_VCS1_IER
, 0);
99 I915_WRITE(GUC_WD_VECS_IER
, 0);
102 static void direct_interrupts_to_guc(struct drm_i915_private
*dev_priv
)
104 struct intel_engine_cs
*engine
;
107 /* tell all command streamers to forward interrupts and vblank to GuC */
108 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_ALWAYS
);
109 irqs
|= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING
);
110 for_each_engine(engine
, dev_priv
)
111 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
113 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
114 irqs
= GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
115 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
116 /* These three registers have the same bit definitions */
117 I915_WRITE(GUC_BCS_RCS_IER
, ~irqs
);
118 I915_WRITE(GUC_VCS2_VCS1_IER
, ~irqs
);
119 I915_WRITE(GUC_WD_VECS_IER
, ~irqs
);
122 static u32
get_gttype(struct drm_i915_private
*dev_priv
)
124 /* XXX: GT type based on PCI device ID? field seems unused by fw */
128 static u32
get_core_family(struct drm_i915_private
*dev_priv
)
130 switch (INTEL_INFO(dev_priv
)->gen
) {
132 return GFXCORE_FAMILY_GEN9
;
135 DRM_ERROR("GUC: unsupported core family\n");
136 return GFXCORE_FAMILY_UNKNOWN
;
140 static void set_guc_init_params(struct drm_i915_private
*dev_priv
)
142 struct intel_guc
*guc
= &dev_priv
->guc
;
143 u32 params
[GUC_CTL_MAX_DWORDS
];
146 memset(¶ms
, 0, sizeof(params
));
148 params
[GUC_CTL_DEVICE_INFO
] |=
149 (get_gttype(dev_priv
) << GUC_CTL_GTTYPE_SHIFT
) |
150 (get_core_family(dev_priv
) << GUC_CTL_COREFAMILY_SHIFT
);
153 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
154 * second. This ARAR is calculated by:
155 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
157 params
[GUC_CTL_ARAT_HIGH
] = 0;
158 params
[GUC_CTL_ARAT_LOW
] = 100000000;
160 params
[GUC_CTL_WA
] |= GUC_CTL_WA_UK_BY_DRIVER
;
162 params
[GUC_CTL_FEATURE
] |= GUC_CTL_DISABLE_SCHEDULER
|
163 GUC_CTL_VCS2_ENABLED
;
165 if (i915
.guc_log_level
>= 0) {
166 params
[GUC_CTL_LOG_PARAMS
] = guc
->log_flags
;
167 params
[GUC_CTL_DEBUG
] =
168 i915
.guc_log_level
<< GUC_LOG_VERBOSITY_SHIFT
;
172 u32 ads
= (u32
)i915_gem_obj_ggtt_offset(guc
->ads_obj
)
174 params
[GUC_CTL_DEBUG
] |= ads
<< GUC_ADS_ADDR_SHIFT
;
175 params
[GUC_CTL_DEBUG
] |= GUC_ADS_ENABLED
;
178 /* If GuC submission is enabled, set up additional parameters here */
179 if (i915
.enable_guc_submission
) {
180 u32 pgs
= i915_gem_obj_ggtt_offset(dev_priv
->guc
.ctx_pool_obj
);
181 u32 ctx_in_16
= GUC_MAX_GPU_CONTEXTS
/ 16;
184 params
[GUC_CTL_CTXINFO
] = (pgs
<< GUC_CTL_BASE_ADDR_SHIFT
) |
185 (ctx_in_16
<< GUC_CTL_CTXNUM_IN16_SHIFT
);
187 params
[GUC_CTL_FEATURE
] |= GUC_CTL_KERNEL_SUBMISSIONS
;
189 /* Unmask this bit to enable the GuC's internal scheduler */
190 params
[GUC_CTL_FEATURE
] &= ~GUC_CTL_DISABLE_SCHEDULER
;
193 I915_WRITE(SOFT_SCRATCH(0), 0);
195 for (i
= 0; i
< GUC_CTL_MAX_DWORDS
; i
++)
196 I915_WRITE(SOFT_SCRATCH(1 + i
), params
[i
]);
200 * Read the GuC status register (GUC_STATUS) and store it in the
201 * specified location; then return a boolean indicating whether
202 * the value matches either of two values representing completion
203 * of the GuC boot process.
205 * This is used for polling the GuC status in a wait_for()
208 static inline bool guc_ucode_response(struct drm_i915_private
*dev_priv
,
211 u32 val
= I915_READ(GUC_STATUS
);
212 u32 uk_val
= val
& GS_UKERNEL_MASK
;
214 return (uk_val
== GS_UKERNEL_READY
||
215 ((val
& GS_MIA_CORE_STATE
) && uk_val
== GS_UKERNEL_LAPIC_DONE
));
219 * Transfer the firmware image to RAM for execution by the microcontroller.
221 * Architecturally, the DMA engine is bidirectional, and can potentially even
222 * transfer between GTT locations. This functionality is left out of the API
223 * for now as there is no need for it.
225 * Note that GuC needs the CSS header plus uKernel code to be copied by the
226 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
228 static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv
)
230 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
231 struct drm_i915_gem_object
*fw_obj
= guc_fw
->guc_fw_obj
;
232 unsigned long offset
;
233 struct sg_table
*sg
= fw_obj
->pages
;
234 u32 status
, rsa
[UOS_RSA_SCRATCH_MAX_COUNT
];
237 /* where RSA signature starts */
238 offset
= guc_fw
->rsa_offset
;
240 /* Copy RSA signature from the fw image to HW for verification */
241 sg_pcopy_to_buffer(sg
->sgl
, sg
->nents
, rsa
, sizeof(rsa
), offset
);
242 for (i
= 0; i
< UOS_RSA_SCRATCH_MAX_COUNT
; i
++)
243 I915_WRITE(UOS_RSA_SCRATCH(i
), rsa
[i
]);
245 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
246 * other components */
247 I915_WRITE(DMA_COPY_SIZE
, guc_fw
->header_size
+ guc_fw
->ucode_size
);
249 /* Set the source address for the new blob */
250 offset
= i915_gem_obj_ggtt_offset(fw_obj
) + guc_fw
->header_offset
;
251 I915_WRITE(DMA_ADDR_0_LOW
, lower_32_bits(offset
));
252 I915_WRITE(DMA_ADDR_0_HIGH
, upper_32_bits(offset
) & 0xFFFF);
255 * Set the DMA destination. Current uCode expects the code to be
256 * loaded at 8k; locations below this are used for the stack.
258 I915_WRITE(DMA_ADDR_1_LOW
, 0x2000);
259 I915_WRITE(DMA_ADDR_1_HIGH
, DMA_ADDRESS_SPACE_WOPCM
);
261 /* Finally start the DMA */
262 I915_WRITE(DMA_CTRL
, _MASKED_BIT_ENABLE(UOS_MOVE
| START_DMA
));
265 * Wait for the DMA to complete & the GuC to start up.
266 * NB: Docs recommend not using the interrupt for completion.
267 * Measurements indicate this should take no more than 20ms, so a
268 * timeout here indicates that the GuC has failed and is unusable.
269 * (Higher levels of the driver will attempt to fall back to
270 * execlist mode if this happens.)
272 ret
= wait_for(guc_ucode_response(dev_priv
, &status
), 100);
274 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
275 I915_READ(DMA_CTRL
), status
);
277 if ((status
& GS_BOOTROM_MASK
) == GS_BOOTROM_RSA_FAILED
) {
278 DRM_ERROR("GuC firmware signature verification failed\n");
282 DRM_DEBUG_DRIVER("returning %d\n", ret
);
288 * Load the GuC firmware blob into the MinuteIA.
290 static int guc_ucode_xfer(struct drm_i915_private
*dev_priv
)
292 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
293 struct drm_device
*dev
= dev_priv
->dev
;
296 ret
= i915_gem_object_set_to_gtt_domain(guc_fw
->guc_fw_obj
, false);
298 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret
);
302 ret
= i915_gem_obj_ggtt_pin(guc_fw
->guc_fw_obj
, 0, 0);
304 DRM_DEBUG_DRIVER("pin failed %d\n", ret
);
308 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
309 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
311 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
314 I915_WRITE(GUC_WOPCM_SIZE
, GUC_WOPCM_SIZE_VALUE
);
315 I915_WRITE(DMA_GUC_WOPCM_OFFSET
, GUC_WOPCM_OFFSET_VALUE
);
317 /* Enable MIA caching. GuC clock gating is disabled. */
318 I915_WRITE(GUC_SHIM_CONTROL
, GUC_SHIM_CONTROL_VALUE
);
320 /* WaDisableMinuteIaClockGating:skl,bxt */
321 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
322 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
323 I915_WRITE(GUC_SHIM_CONTROL
, (I915_READ(GUC_SHIM_CONTROL
) &
324 ~GUC_ENABLE_MIA_CLOCK_GATING
));
327 /* WaC6DisallowByGfxPause*/
328 I915_WRITE(GEN6_GFXPAUSE
, 0x30FFF);
331 I915_WRITE(GEN9LP_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
333 I915_WRITE(GEN9_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
336 /* DOP Clock Gating Enable for GuC clocks */
337 I915_WRITE(GEN7_MISCCPCTL
, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE
|
338 I915_READ(GEN7_MISCCPCTL
)));
340 /* allows for 5us before GT can go to RC6 */
341 I915_WRITE(GUC_ARAT_C6DIS
, 0x1FF);
344 set_guc_init_params(dev_priv
);
346 ret
= guc_ucode_xfer_dma(dev_priv
);
348 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
351 * We keep the object pages for reuse during resume. But we can unpin it
352 * now that DMA has completed, so it doesn't continue to take up space.
354 i915_gem_object_ggtt_unpin(guc_fw
->guc_fw_obj
);
359 static int i915_reset_guc(struct drm_i915_private
*dev_priv
)
364 ret
= intel_guc_reset(dev_priv
);
366 DRM_ERROR("GuC reset failed, ret = %d\n", ret
);
370 guc_status
= I915_READ(GUC_STATUS
);
371 WARN(!(guc_status
& GS_MIA_IN_RESET
),
372 "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status
);
378 * intel_guc_ucode_load() - load GuC uCode into the device
381 * Called from gem_init_hw() during driver loading and also after a GPU reset.
383 * The firmware image should have already been fetched into memory by the
384 * earlier call to intel_guc_ucode_init(), so here we need only check that
385 * is succeeded, and then transfer the image to the h/w.
387 * Return: non-zero code on error
389 int intel_guc_ucode_load(struct drm_device
*dev
)
391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
392 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
393 int retries
, err
= 0;
395 if (!i915
.enable_guc_submission
)
398 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
399 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
400 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
402 direct_interrupts_to_host(dev_priv
);
404 if (guc_fw
->guc_fw_fetch_status
== GUC_FIRMWARE_NONE
)
407 if (guc_fw
->guc_fw_fetch_status
== GUC_FIRMWARE_SUCCESS
&&
408 guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_FAIL
)
411 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_PENDING
;
413 DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
414 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
416 switch (guc_fw
->guc_fw_fetch_status
) {
417 case GUC_FIRMWARE_FAIL
:
418 /* something went wrong :( */
422 case GUC_FIRMWARE_NONE
:
423 case GUC_FIRMWARE_PENDING
:
426 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
428 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
429 guc_fw
->guc_fw_fetch_status
);
433 case GUC_FIRMWARE_SUCCESS
:
437 err
= i915_guc_submission_init(dev
);
442 * WaEnableuKernelHeaderValidFix:skl,bxt
443 * For BXT, this is only upto B0 but below WA is required for later
444 * steppings also so this is extended as well.
446 /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
447 for (retries
= 3; ; ) {
449 * Always reset the GuC just before (re)loading, so
450 * that the state and timing are fairly predictable
452 err
= i915_reset_guc(dev_priv
);
454 DRM_ERROR("GuC reset failed, err %d\n", err
);
458 err
= guc_ucode_xfer(dev_priv
);
465 DRM_INFO("GuC fw load failed, err %d; will reset and "
466 "retry %d more time(s)\n", err
, retries
);
469 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_SUCCESS
;
471 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
472 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
473 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
475 if (i915
.enable_guc_submission
) {
476 /* The execbuf_client will be recreated. Release it first. */
477 i915_guc_submission_disable(dev
);
479 err
= i915_guc_submission_enable(dev
);
482 direct_interrupts_to_guc(dev_priv
);
488 DRM_ERROR("GuC firmware load failed, err %d\n", err
);
489 if (guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_PENDING
)
490 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_FAIL
;
492 direct_interrupts_to_host(dev_priv
);
493 i915_guc_submission_disable(dev
);
494 i915_guc_submission_fini(dev
);
499 static void guc_fw_fetch(struct drm_device
*dev
, struct intel_guc_fw
*guc_fw
)
501 struct drm_i915_gem_object
*obj
;
502 const struct firmware
*fw
;
503 struct guc_css_header
*css
;
507 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
508 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
510 err
= request_firmware(&fw
, guc_fw
->guc_fw_path
, &dev
->pdev
->dev
);
516 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
517 guc_fw
->guc_fw_path
, fw
);
519 /* Check the size of the blob before examining buffer contents */
520 if (fw
->size
< sizeof(struct guc_css_header
)) {
521 DRM_ERROR("Firmware header is missing\n");
525 css
= (struct guc_css_header
*)fw
->data
;
527 /* Firmware bits always start from header */
528 guc_fw
->header_offset
= 0;
529 guc_fw
->header_size
= (css
->header_size_dw
- css
->modulus_size_dw
-
530 css
->key_size_dw
- css
->exponent_size_dw
) * sizeof(u32
);
532 if (guc_fw
->header_size
!= sizeof(struct guc_css_header
)) {
533 DRM_ERROR("CSS header definition mismatch\n");
538 guc_fw
->ucode_offset
= guc_fw
->header_offset
+ guc_fw
->header_size
;
539 guc_fw
->ucode_size
= (css
->size_dw
- css
->header_size_dw
) * sizeof(u32
);
542 if (css
->key_size_dw
!= UOS_RSA_SCRATCH_MAX_COUNT
) {
543 DRM_ERROR("RSA key size is bad\n");
546 guc_fw
->rsa_offset
= guc_fw
->ucode_offset
+ guc_fw
->ucode_size
;
547 guc_fw
->rsa_size
= css
->key_size_dw
* sizeof(u32
);
549 /* At least, it should have header, uCode and RSA. Size of all three. */
550 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
+ guc_fw
->rsa_size
;
551 if (fw
->size
< size
) {
552 DRM_ERROR("Missing firmware components\n");
556 /* Header and uCode will be loaded to WOPCM. Size of the two. */
557 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
;
559 /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
560 if (size
> GUC_WOPCM_SIZE_VALUE
- 0x8000) {
561 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
566 * The GuC firmware image has the version number embedded at a well-known
567 * offset within the firmware blob; note that major / minor version are
568 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
569 * in terms of bytes (u8).
571 guc_fw
->guc_fw_major_found
= css
->guc_sw_version
>> 16;
572 guc_fw
->guc_fw_minor_found
= css
->guc_sw_version
& 0xFFFF;
574 if (guc_fw
->guc_fw_major_found
!= guc_fw
->guc_fw_major_wanted
||
575 guc_fw
->guc_fw_minor_found
< guc_fw
->guc_fw_minor_wanted
) {
576 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
577 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
578 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
583 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
584 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
585 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
587 mutex_lock(&dev
->struct_mutex
);
588 obj
= i915_gem_object_create_from_data(dev
, fw
->data
, fw
->size
);
589 mutex_unlock(&dev
->struct_mutex
);
590 if (IS_ERR_OR_NULL(obj
)) {
591 err
= obj
? PTR_ERR(obj
) : -ENOMEM
;
595 guc_fw
->guc_fw_obj
= obj
;
596 guc_fw
->guc_fw_size
= fw
->size
;
598 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
601 release_firmware(fw
);
602 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_SUCCESS
;
606 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
607 err
, fw
, guc_fw
->guc_fw_obj
);
608 DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
609 guc_fw
->guc_fw_path
, err
);
611 mutex_lock(&dev
->struct_mutex
);
612 obj
= guc_fw
->guc_fw_obj
;
614 drm_gem_object_unreference(&obj
->base
);
615 guc_fw
->guc_fw_obj
= NULL
;
616 mutex_unlock(&dev
->struct_mutex
);
618 release_firmware(fw
); /* OK even if fw is NULL */
619 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_FAIL
;
623 * intel_guc_ucode_init() - define parameters and fetch firmware
626 * Called early during driver load, but after GEM is initialised.
628 * The firmware will be transferred to the GuC's memory later,
629 * when intel_guc_ucode_load() is called.
631 void intel_guc_ucode_init(struct drm_device
*dev
)
633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
634 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
637 if (!HAS_GUC_SCHED(dev
))
638 i915
.enable_guc_submission
= false;
640 if (!HAS_GUC_UCODE(dev
)) {
642 } else if (IS_SKYLAKE(dev
)) {
643 fw_path
= I915_SKL_GUC_UCODE
;
644 guc_fw
->guc_fw_major_wanted
= 6;
645 guc_fw
->guc_fw_minor_wanted
= 1;
646 } else if (IS_BROXTON(dev
)) {
647 fw_path
= I915_BXT_GUC_UCODE
;
648 guc_fw
->guc_fw_major_wanted
= 8;
649 guc_fw
->guc_fw_minor_wanted
= 7;
651 i915
.enable_guc_submission
= false;
652 fw_path
= ""; /* unknown device */
655 if (!i915
.enable_guc_submission
)
658 guc_fw
->guc_dev
= dev
;
659 guc_fw
->guc_fw_path
= fw_path
;
660 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;
661 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_NONE
;
666 if (*fw_path
== '\0') {
667 DRM_ERROR("No GuC firmware known for this platform\n");
668 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_FAIL
;
672 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_PENDING
;
673 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path
);
674 guc_fw_fetch(dev
, guc_fw
);
675 /* status must now be FAIL or SUCCESS */
679 * intel_guc_ucode_fini() - clean up all allocated resources
682 void intel_guc_ucode_fini(struct drm_device
*dev
)
684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
685 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
687 mutex_lock(&dev
->struct_mutex
);
688 direct_interrupts_to_host(dev_priv
);
689 i915_guc_submission_disable(dev
);
690 i915_guc_submission_fini(dev
);
692 if (guc_fw
->guc_fw_obj
)
693 drm_gem_object_unreference(&guc_fw
->guc_fw_obj
->base
);
694 guc_fw
->guc_fw_obj
= NULL
;
695 mutex_unlock(&dev
->struct_mutex
);
697 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;