drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_crtc.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 static void
  41 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  42 {
  43         struct drm_device *dev = intel_hdmi->base.base.dev;
  44         struct drm_i915_private *dev_priv = dev->dev_private;
  45         uint32_t enabled_bits;
  46
  47         enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  48
  49         WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
  50              "HDMI port enabled, expecting disabled\n");
  51 }
  52
  53 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  54 {
  55         return container_of(encoder, struct intel_hdmi, base.base);
  56 }
  57
  58 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  59 {
  60         return container_of(intel_attached_encoder(connector),
  61                             struct intel_hdmi, base);
  62 }
  63
  64 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  65 {
  66         uint8_t *data = (uint8_t *)frame;
  67         uint8_t sum = 0;
  68         unsigned i;
  69
  70         frame->checksum = 0;
  71         frame->ecc = 0;
  72
  73         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  74                 sum += data[i];
  75
  76         frame->checksum = 0x100 - sum;
  77 }
  78
  79 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  80 {
  81         switch (frame->type) {
  82         case DIP_TYPE_AVI:
  83                 return VIDEO_DIP_SELECT_AVI;
  84         case DIP_TYPE_SPD:
  85                 return VIDEO_DIP_SELECT_SPD;
  86         default:
  87                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  88                 return 0;
  89         }
  90 }
  91
  92 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  93 {
  94         switch (frame->type) {
  95         case DIP_TYPE_AVI:
  96                 return VIDEO_DIP_ENABLE_AVI;
  97         case DIP_TYPE_SPD:
  98                 return VIDEO_DIP_ENABLE_SPD;
  99         default:
 100                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 101                 return 0;
 102         }
 103 }
 104
 105 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
 106 {
 107         switch (frame->type) {
 108         case DIP_TYPE_AVI:
 109                 return VIDEO_DIP_ENABLE_AVI_HSW;
 110         case DIP_TYPE_SPD:
 111                 return VIDEO_DIP_ENABLE_SPD_HSW;
 112         default:
 113                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 114                 return 0;
 115         }
 116 }
 117
 118 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
 119 {
 120         switch (frame->type) {
 121         case DIP_TYPE_AVI:
 122                 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
 123         case DIP_TYPE_SPD:
 124                 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
 125         default:
 126                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 127                 return 0;
 128         }
 129 }
 130
 131 static void g4x_write_infoframe(struct drm_encoder *encoder,
 132                                 struct dip_infoframe *frame)
 133 {
 134         uint32_t *data = (uint32_t *)frame;
 135         struct drm_device *dev = encoder->dev;
 136         struct drm_i915_private *dev_priv = dev->dev_private;
 137         u32 val = I915_READ(VIDEO_DIP_CTL);
 138         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 139
 140         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 141
 142         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 143         val |= g4x_infoframe_index(frame);
 144
 145         val &= ~g4x_infoframe_enable(frame);
 146
 147         I915_WRITE(VIDEO_DIP_CTL, val);
 148
 149         mmiowb();
 150         for (i = 0; i < len; i += 4) {
 151                 I915_WRITE(VIDEO_DIP_DATA, *data);
 152                 data++;
 153         }
 154         /* Write every possible data byte to force correct ECC calculation. */
 155         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 156                 I915_WRITE(VIDEO_DIP_DATA, 0);
 157         mmiowb();
 158
 159         val |= g4x_infoframe_enable(frame);
 160         val &= ~VIDEO_DIP_FREQ_MASK;
 161         val |= VIDEO_DIP_FREQ_VSYNC;
 162
 163         I915_WRITE(VIDEO_DIP_CTL, val);
 164         POSTING_READ(VIDEO_DIP_CTL);
 165 }
 166
 167 static void ibx_write_infoframe(struct drm_encoder *encoder,
 168                                 struct dip_infoframe *frame)
 169 {
 170         uint32_t *data = (uint32_t *)frame;
 171         struct drm_device *dev = encoder->dev;
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 174         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 175         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 176         u32 val = I915_READ(reg);
 177
 178         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 179
 180         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 181         val |= g4x_infoframe_index(frame);
 182
 183         val &= ~g4x_infoframe_enable(frame);
 184
 185         I915_WRITE(reg, val);
 186
 187         mmiowb();
 188         for (i = 0; i < len; i += 4) {
 189                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 190                 data++;
 191         }
 192         /* Write every possible data byte to force correct ECC calculation. */
 193         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 194                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 195         mmiowb();
 196
 197         val |= g4x_infoframe_enable(frame);
 198         val &= ~VIDEO_DIP_FREQ_MASK;
 199         val |= VIDEO_DIP_FREQ_VSYNC;
 200
 201         I915_WRITE(reg, val);
 202         POSTING_READ(reg);
 203 }
 204
 205 static void cpt_write_infoframe(struct drm_encoder *encoder,
 206                                 struct dip_infoframe *frame)
 207 {
 208         uint32_t *data = (uint32_t *)frame;
 209         struct drm_device *dev = encoder->dev;
 210         struct drm_i915_private *dev_priv = dev->dev_private;
 211         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 212         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 213         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 214         u32 val = I915_READ(reg);
 215
 216         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 217
 218         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 219         val |= g4x_infoframe_index(frame);
 220
 221         /* The DIP control register spec says that we need to update the AVI
 222          * infoframe without clearing its enable bit */
 223         if (frame->type != DIP_TYPE_AVI)
 224                 val &= ~g4x_infoframe_enable(frame);
 225
 226         I915_WRITE(reg, val);
 227
 228         mmiowb();
 229         for (i = 0; i < len; i += 4) {
 230                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 231                 data++;
 232         }
 233         /* Write every possible data byte to force correct ECC calculation. */
 234         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 235                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 236         mmiowb();
 237
 238         val |= g4x_infoframe_enable(frame);
 239         val &= ~VIDEO_DIP_FREQ_MASK;
 240         val |= VIDEO_DIP_FREQ_VSYNC;
 241
 242         I915_WRITE(reg, val);
 243         POSTING_READ(reg);
 244 }
 245
 246 static void vlv_write_infoframe(struct drm_encoder *encoder,
 247                                      struct dip_infoframe *frame)
 248 {
 249         uint32_t *data = (uint32_t *)frame;
 250         struct drm_device *dev = encoder->dev;
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 253         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 254         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 255         u32 val = I915_READ(reg);
 256
 257         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 258
 259         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 260         val |= g4x_infoframe_index(frame);
 261
 262         val &= ~g4x_infoframe_enable(frame);
 263
 264         I915_WRITE(reg, val);
 265
 266         mmiowb();
 267         for (i = 0; i < len; i += 4) {
 268                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 269                 data++;
 270         }
 271         /* Write every possible data byte to force correct ECC calculation. */
 272         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 273                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 274         mmiowb();
 275
 276         val |= g4x_infoframe_enable(frame);
 277         val &= ~VIDEO_DIP_FREQ_MASK;
 278         val |= VIDEO_DIP_FREQ_VSYNC;
 279
 280         I915_WRITE(reg, val);
 281         POSTING_READ(reg);
 282 }
 283
 284 static void hsw_write_infoframe(struct drm_encoder *encoder,
 285                                 struct dip_infoframe *frame)
 286 {
 287         uint32_t *data = (uint32_t *)frame;
 288         struct drm_device *dev = encoder->dev;
 289         struct drm_i915_private *dev_priv = dev->dev_private;
 290         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 291         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 292         u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
 293         unsigned int i, len = DIP_HEADER_SIZE + frame->len;
 294         u32 val = I915_READ(ctl_reg);
 295
 296         if (data_reg == 0)
 297                 return;
 298
 299         val &= ~hsw_infoframe_enable(frame);
 300         I915_WRITE(ctl_reg, val);
 301
 302         mmiowb();
 303         for (i = 0; i < len; i += 4) {
 304                 I915_WRITE(data_reg + i, *data);
 305                 data++;
 306         }
 307         /* Write every possible data byte to force correct ECC calculation. */
 308         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 309                 I915_WRITE(data_reg + i, 0);
 310         mmiowb();
 311
 312         val |= hsw_infoframe_enable(frame);
 313         I915_WRITE(ctl_reg, val);
 314         POSTING_READ(ctl_reg);
 315 }
 316
 317 static void intel_set_infoframe(struct drm_encoder *encoder,
 318                                 struct dip_infoframe *frame)
 319 {
 320         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 321
 322         intel_dip_infoframe_csum(frame);
 323         intel_hdmi->write_infoframe(encoder, frame);
 324 }
 325
 326 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 327                                          struct drm_display_mode *adjusted_mode)
 328 {
 329         struct dip_infoframe avi_if = {
 330                 .type = DIP_TYPE_AVI,
 331                 .ver = DIP_VERSION_AVI,
 332                 .len = DIP_LEN_AVI,
 333         };
 334
 335         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 336                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 337
 338         intel_set_infoframe(encoder, &avi_if);
 339 }
 340
 341 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 342 {
 343         struct dip_infoframe spd_if;
 344
 345         memset(&spd_if, 0, sizeof(spd_if));
 346         spd_if.type = DIP_TYPE_SPD;
 347         spd_if.ver = DIP_VERSION_SPD;
 348         spd_if.len = DIP_LEN_SPD;
 349         strcpy(spd_if.body.spd.vn, "Intel");
 350         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 351         spd_if.body.spd.sdi = DIP_SPD_PC;
 352
 353         intel_set_infoframe(encoder, &spd_if);
 354 }
 355
 356 static void g4x_set_infoframes(struct drm_encoder *encoder,
 357                                struct drm_display_mode *adjusted_mode)
 358 {
 359         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 360         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 361         u32 reg = VIDEO_DIP_CTL;
 362         u32 val = I915_READ(reg);
 363         u32 port;
 364
 365         assert_hdmi_port_disabled(intel_hdmi);
 366
 367         /* If the registers were not initialized yet, they might be zeroes,
 368          * which means we're selecting the AVI DIP and we're setting its
 369          * frequency to once. This seems to really confuse the HW and make
 370          * things stop working (the register spec says the AVI always needs to
 371          * be sent every VSync). So here we avoid writing to the register more
 372          * than we need and also explicitly select the AVI DIP and explicitly
 373          * set its frequency to every VSync. Avoiding to write it twice seems to
 374          * be enough to solve the problem, but being defensive shouldn't hurt us
 375          * either. */
 376         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 377
 378         if (!intel_hdmi->has_hdmi_sink) {
 379                 if (!(val & VIDEO_DIP_ENABLE))
 380                         return;
 381                 val &= ~VIDEO_DIP_ENABLE;
 382                 I915_WRITE(reg, val);
 383                 POSTING_READ(reg);
 384                 return;
 385         }
 386
 387         switch (intel_hdmi->sdvox_reg) {
 388         case SDVOB:
 389                 port = VIDEO_DIP_PORT_B;
 390                 break;
 391         case SDVOC:
 392                 port = VIDEO_DIP_PORT_C;
 393                 break;
 394         default:
 395                 BUG();
 396                 return;
 397         }
 398
 399         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 400                 if (val & VIDEO_DIP_ENABLE) {
 401                         val &= ~VIDEO_DIP_ENABLE;
 402                         I915_WRITE(reg, val);
 403                         POSTING_READ(reg);
 404                 }
 405                 val &= ~VIDEO_DIP_PORT_MASK;
 406                 val |= port;
 407         }
 408
 409         val |= VIDEO_DIP_ENABLE;
 410         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 411
 412         I915_WRITE(reg, val);
 413         POSTING_READ(reg);
 414
 415         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 416         intel_hdmi_set_spd_infoframe(encoder);
 417 }
 418
 419 static void ibx_set_infoframes(struct drm_encoder *encoder,
 420                                struct drm_display_mode *adjusted_mode)
 421 {
 422         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 423         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 424         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 425         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 426         u32 val = I915_READ(reg);
 427         u32 port;
 428
 429         assert_hdmi_port_disabled(intel_hdmi);
 430
 431         /* See the big comment in g4x_set_infoframes() */
 432         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 433
 434         if (!intel_hdmi->has_hdmi_sink) {
 435                 if (!(val & VIDEO_DIP_ENABLE))
 436                         return;
 437                 val &= ~VIDEO_DIP_ENABLE;
 438                 I915_WRITE(reg, val);
 439                 POSTING_READ(reg);
 440                 return;
 441         }
 442
 443         switch (intel_hdmi->sdvox_reg) {
 444         case HDMIB:
 445                 port = VIDEO_DIP_PORT_B;
 446                 break;
 447         case HDMIC:
 448                 port = VIDEO_DIP_PORT_C;
 449                 break;
 450         case HDMID:
 451                 port = VIDEO_DIP_PORT_D;
 452                 break;
 453         default:
 454                 BUG();
 455                 return;
 456         }
 457
 458         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 459                 if (val & VIDEO_DIP_ENABLE) {
 460                         val &= ~VIDEO_DIP_ENABLE;
 461                         I915_WRITE(reg, val);
 462                         POSTING_READ(reg);
 463                 }
 464                 val &= ~VIDEO_DIP_PORT_MASK;
 465                 val |= port;
 466         }
 467
 468         val |= VIDEO_DIP_ENABLE;
 469         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 470                  VIDEO_DIP_ENABLE_GCP);
 471
 472         I915_WRITE(reg, val);
 473         POSTING_READ(reg);
 474
 475         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 476         intel_hdmi_set_spd_infoframe(encoder);
 477 }
 478
 479 static void cpt_set_infoframes(struct drm_encoder *encoder,
 480                                struct drm_display_mode *adjusted_mode)
 481 {
 482         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 483         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 484         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 485         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 486         u32 val = I915_READ(reg);
 487
 488         assert_hdmi_port_disabled(intel_hdmi);
 489
 490         /* See the big comment in g4x_set_infoframes() */
 491         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 492
 493         if (!intel_hdmi->has_hdmi_sink) {
 494                 if (!(val & VIDEO_DIP_ENABLE))
 495                         return;
 496                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 497                 I915_WRITE(reg, val);
 498                 POSTING_READ(reg);
 499                 return;
 500         }
 501
 502         /* Set both together, unset both together: see the spec. */
 503         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 504         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 505                  VIDEO_DIP_ENABLE_GCP);
 506
 507         I915_WRITE(reg, val);
 508         POSTING_READ(reg);
 509
 510         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 511         intel_hdmi_set_spd_infoframe(encoder);
 512 }
 513
 514 static void vlv_set_infoframes(struct drm_encoder *encoder,
 515                                struct drm_display_mode *adjusted_mode)
 516 {
 517         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 518         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 519         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 520         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 521         u32 val = I915_READ(reg);
 522
 523         assert_hdmi_port_disabled(intel_hdmi);
 524
 525         /* See the big comment in g4x_set_infoframes() */
 526         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 527
 528         if (!intel_hdmi->has_hdmi_sink) {
 529                 if (!(val & VIDEO_DIP_ENABLE))
 530                         return;
 531                 val &= ~VIDEO_DIP_ENABLE;
 532                 I915_WRITE(reg, val);
 533                 POSTING_READ(reg);
 534                 return;
 535         }
 536
 537         val |= VIDEO_DIP_ENABLE;
 538         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 539                  VIDEO_DIP_ENABLE_GCP);
 540
 541         I915_WRITE(reg, val);
 542         POSTING_READ(reg);
 543
 544         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 545         intel_hdmi_set_spd_infoframe(encoder);
 546 }
 547
 548 static void hsw_set_infoframes(struct drm_encoder *encoder,
 549                                struct drm_display_mode *adjusted_mode)
 550 {
 551         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 552         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 553         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 554         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 555         u32 val = I915_READ(reg);
 556
 557         assert_hdmi_port_disabled(intel_hdmi);
 558
 559         if (!intel_hdmi->has_hdmi_sink) {
 560                 I915_WRITE(reg, 0);
 561                 POSTING_READ(reg);
 562                 return;
 563         }
 564
 565         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 566                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 567
 568         I915_WRITE(reg, val);
 569         POSTING_READ(reg);
 570
 571         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 572         intel_hdmi_set_spd_infoframe(encoder);
 573 }
 574
 575 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 576                                 struct drm_display_mode *mode,
 577                                 struct drm_display_mode *adjusted_mode)
 578 {
 579         struct drm_device *dev = encoder->dev;
 580         struct drm_i915_private *dev_priv = dev->dev_private;
 581         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 582         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 583         u32 sdvox;
 584
 585         sdvox = SDVO_ENCODING_HDMI;
 586         if (!HAS_PCH_SPLIT(dev))
 587                 sdvox |= intel_hdmi->color_range;
 588         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 589                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 590         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 591                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 592
 593         if (intel_crtc->bpp > 24)
 594                 sdvox |= COLOR_FORMAT_12bpc;
 595         else
 596                 sdvox |= COLOR_FORMAT_8bpc;
 597
 598         /* Required on CPT */
 599         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 600                 sdvox |= HDMI_MODE_SELECT;
 601
 602         if (intel_hdmi->has_audio) {
 603                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 604                                  pipe_name(intel_crtc->pipe));
 605                 sdvox |= SDVO_AUDIO_ENABLE;
 606                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 607                 intel_write_eld(encoder, adjusted_mode);
 608         }
 609
 610         if (HAS_PCH_CPT(dev))
 611                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 612         else if (intel_crtc->pipe == PIPE_B)
 613                 sdvox |= SDVO_PIPE_B_SELECT;
 614
 615         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 616         POSTING_READ(intel_hdmi->sdvox_reg);
 617
 618         intel_hdmi->set_infoframes(encoder, adjusted_mode);
 619 }
 620
 621 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 622                                     enum pipe *pipe)
 623 {
 624         struct drm_device *dev = encoder->base.dev;
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 627         u32 tmp;
 628
 629         tmp = I915_READ(intel_hdmi->sdvox_reg);
 630
 631         if (!(tmp & SDVO_ENABLE))
 632                 return false;
 633
 634         if (HAS_PCH_CPT(dev))
 635                 *pipe = PORT_TO_PIPE_CPT(tmp);
 636         else
 637                 *pipe = PORT_TO_PIPE(tmp);
 638
 639         return true;
 640 }
 641
 642 static void intel_enable_hdmi(struct intel_encoder *encoder)
 643 {
 644         struct drm_device *dev = encoder->base.dev;
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 647         u32 temp;
 648         u32 enable_bits = SDVO_ENABLE;
 649
 650         if (intel_hdmi->has_audio)
 651                 enable_bits |= SDVO_AUDIO_ENABLE;
 652
 653         temp = I915_READ(intel_hdmi->sdvox_reg);
 654
 655         /* HW workaround for IBX, we need to move the port to transcoder A
 656          * before disabling it. */
 657         if (HAS_PCH_IBX(dev)) {
 658                 struct drm_crtc *crtc = encoder->base.crtc;
 659                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 660
 661                 /* Restore the transcoder select bit. */
 662                 if (pipe == PIPE_B)
 663                         enable_bits |= SDVO_PIPE_B_SELECT;
 664         }
 665
 666         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 667          * we do this anyway which shows more stable in testing.
 668          */
 669         if (HAS_PCH_SPLIT(dev)) {
 670                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 671                 POSTING_READ(intel_hdmi->sdvox_reg);
 672         }
 673
 674         temp |= enable_bits;
 675
 676         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 677         POSTING_READ(intel_hdmi->sdvox_reg);
 678
 679         /* HW workaround, need to write this twice for issue that may result
 680          * in first write getting masked.
 681          */
 682         if (HAS_PCH_SPLIT(dev)) {
 683                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 684                 POSTING_READ(intel_hdmi->sdvox_reg);
 685         }
 686 }
 687
 688 static void intel_disable_hdmi(struct intel_encoder *encoder)
 689 {
 690         struct drm_device *dev = encoder->base.dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 693         u32 temp;
 694         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 695
 696         temp = I915_READ(intel_hdmi->sdvox_reg);
 697
 698         /* HW workaround for IBX, we need to move the port to transcoder A
 699          * before disabling it. */
 700         if (HAS_PCH_IBX(dev)) {
 701                 struct drm_crtc *crtc = encoder->base.crtc;
 702                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 703
 704                 if (temp & SDVO_PIPE_B_SELECT) {
 705                         temp &= ~SDVO_PIPE_B_SELECT;
 706                         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 707                         POSTING_READ(intel_hdmi->sdvox_reg);
 708
 709                         /* Again we need to write this twice. */
 710                         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 711                         POSTING_READ(intel_hdmi->sdvox_reg);
 712
 713                         /* Transcoder selection bits only update
 714                          * effectively on vblank. */
 715                         if (crtc)
 716                                 intel_wait_for_vblank(dev, pipe);
 717                         else
 718                                 msleep(50);
 719                 }
 720         }
 721
 722         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 723          * we do this anyway which shows more stable in testing.
 724          */
 725         if (HAS_PCH_SPLIT(dev)) {
 726                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 727                 POSTING_READ(intel_hdmi->sdvox_reg);
 728         }
 729
 730         temp &= ~enable_bits;
 731
 732         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 733         POSTING_READ(intel_hdmi->sdvox_reg);
 734
 735         /* HW workaround, need to write this twice for issue that may result
 736          * in first write getting masked.
 737          */
 738         if (HAS_PCH_SPLIT(dev)) {
 739                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 740                 POSTING_READ(intel_hdmi->sdvox_reg);
 741         }
 742 }
 743
 744 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 745                                  struct drm_display_mode *mode)
 746 {
 747         if (mode->clock > 165000)
 748                 return MODE_CLOCK_HIGH;
 749         if (mode->clock < 20000)
 750                 return MODE_CLOCK_LOW;
 751
 752         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 753                 return MODE_NO_DBLESCAN;
 754
 755         return MODE_OK;
 756 }
 757
 758 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 759                                   const struct drm_display_mode *mode,
 760                                   struct drm_display_mode *adjusted_mode)
 761 {
 762         return true;
 763 }
 764
 765 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
 766 {
 767         struct drm_device *dev = intel_hdmi->base.base.dev;
 768         struct drm_i915_private *dev_priv = dev->dev_private;
 769         uint32_t bit;
 770
 771         switch (intel_hdmi->sdvox_reg) {
 772         case SDVOB:
 773                 bit = HDMIB_HOTPLUG_LIVE_STATUS;
 774                 break;
 775         case SDVOC:
 776                 bit = HDMIC_HOTPLUG_LIVE_STATUS;
 777                 break;
 778         default:
 779                 bit = 0;
 780                 break;
 781         }
 782
 783         return I915_READ(PORT_HOTPLUG_STAT) & bit;
 784 }
 785
 786 static enum drm_connector_status
 787 intel_hdmi_detect(struct drm_connector *connector, bool force)
 788 {
 789         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 790         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 791         struct edid *edid;
 792         enum drm_connector_status status = connector_status_disconnected;
 793
 794         if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
 795                 return status;
 796
 797         intel_hdmi->has_hdmi_sink = false;
 798         intel_hdmi->has_audio = false;
 799         edid = drm_get_edid(connector,
 800                             intel_gmbus_get_adapter(dev_priv,
 801                                                     intel_hdmi->ddc_bus));
 802
 803         if (edid) {
 804                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 805                         status = connector_status_connected;
 806                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 807                                 intel_hdmi->has_hdmi_sink =
 808                                                 drm_detect_hdmi_monitor(edid);
 809                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 810                 }
 811                 kfree(edid);
 812         }
 813
 814         if (status == connector_status_connected) {
 815                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 816                         intel_hdmi->has_audio =
 817                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 818         }
 819
 820         return status;
 821 }
 822
 823 static int intel_hdmi_get_modes(struct drm_connector *connector)
 824 {
 825         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 826         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 827
 828         /* We should parse the EDID data and find out if it's an HDMI sink so
 829          * we can send audio to it.
 830          */
 831
 832         return intel_ddc_get_modes(connector,
 833                                    intel_gmbus_get_adapter(dev_priv,
 834                                                            intel_hdmi->ddc_bus));
 835 }
 836
 837 static bool
 838 intel_hdmi_detect_audio(struct drm_connector *connector)
 839 {
 840         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 841         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 842         struct edid *edid;
 843         bool has_audio = false;
 844
 845         edid = drm_get_edid(connector,
 846                             intel_gmbus_get_adapter(dev_priv,
 847                                                     intel_hdmi->ddc_bus));
 848         if (edid) {
 849                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 850                         has_audio = drm_detect_monitor_audio(edid);
 851                 kfree(edid);
 852         }
 853
 854         return has_audio;
 855 }
 856
 857 static int
 858 intel_hdmi_set_property(struct drm_connector *connector,
 859                         struct drm_property *property,
 860                         uint64_t val)
 861 {
 862         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 863         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 864         int ret;
 865
 866         ret = drm_connector_property_set_value(connector, property, val);
 867         if (ret)
 868                 return ret;
 869
 870         if (property == dev_priv->force_audio_property) {
 871                 enum hdmi_force_audio i = val;
 872                 bool has_audio;
 873
 874                 if (i == intel_hdmi->force_audio)
 875                         return 0;
 876
 877                 intel_hdmi->force_audio = i;
 878
 879                 if (i == HDMI_AUDIO_AUTO)
 880                         has_audio = intel_hdmi_detect_audio(connector);
 881                 else
 882                         has_audio = (i == HDMI_AUDIO_ON);
 883
 884                 if (i == HDMI_AUDIO_OFF_DVI)
 885                         intel_hdmi->has_hdmi_sink = 0;
 886
 887                 intel_hdmi->has_audio = has_audio;
 888                 goto done;
 889         }
 890
 891         if (property == dev_priv->broadcast_rgb_property) {
 892                 if (val == !!intel_hdmi->color_range)
 893                         return 0;
 894
 895                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 896                 goto done;
 897         }
 898
 899         return -EINVAL;
 900
 901 done:
 902         if (intel_hdmi->base.base.crtc) {
 903                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
 904                 intel_set_mode(crtc, &crtc->mode,
 905                                crtc->x, crtc->y, crtc->fb);
 906         }
 907
 908         return 0;
 909 }
 910
 911 static void intel_hdmi_destroy(struct drm_connector *connector)
 912 {
 913         drm_sysfs_connector_remove(connector);
 914         drm_connector_cleanup(connector);
 915         kfree(connector);
 916 }
 917
 918 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
 919         .mode_fixup = intel_hdmi_mode_fixup,
 920         .mode_set = intel_ddi_mode_set,
 921         .disable = intel_encoder_noop,
 922 };
 923
 924 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 925         .mode_fixup = intel_hdmi_mode_fixup,
 926         .mode_set = intel_hdmi_mode_set,
 927         .disable = intel_encoder_noop,
 928 };
 929
 930 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 931         .dpms = intel_connector_dpms,
 932         .detect = intel_hdmi_detect,
 933         .fill_modes = drm_helper_probe_single_connector_modes,
 934         .set_property = intel_hdmi_set_property,
 935         .destroy = intel_hdmi_destroy,
 936 };
 937
 938 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 939         .get_modes = intel_hdmi_get_modes,
 940         .mode_valid = intel_hdmi_mode_valid,
 941         .best_encoder = intel_best_encoder,
 942 };
 943
 944 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 945         .destroy = intel_encoder_destroy,
 946 };
 947
 948 static void
 949 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 950 {
 951         intel_attach_force_audio_property(connector);
 952         intel_attach_broadcast_rgb_property(connector);
 953 }
 954
 955 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
 956 {
 957         struct drm_i915_private *dev_priv = dev->dev_private;
 958         struct drm_connector *connector;
 959         struct intel_encoder *intel_encoder;
 960         struct intel_connector *intel_connector;
 961         struct intel_hdmi *intel_hdmi;
 962
 963         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 964         if (!intel_hdmi)
 965                 return;
 966
 967         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 968         if (!intel_connector) {
 969                 kfree(intel_hdmi);
 970                 return;
 971         }
 972
 973         intel_encoder = &intel_hdmi->base;
 974         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
 975                          DRM_MODE_ENCODER_TMDS);
 976
 977         connector = &intel_connector->base;
 978         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 979                            DRM_MODE_CONNECTOR_HDMIA);
 980         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 981
 982         intel_encoder->type = INTEL_OUTPUT_HDMI;
 983
 984         connector->polled = DRM_CONNECTOR_POLL_HPD;
 985         connector->interlace_allowed = 1;
 986         connector->doublescan_allowed = 0;
 987         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 988
 989         intel_encoder->cloneable = false;
 990
 991         intel_hdmi->ddi_port = port;
 992         switch (port) {
 993         case PORT_B:
 994                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 995                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 996                 break;
 997         case PORT_C:
 998                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 999                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
1000                 break;
1001         case PORT_D:
1002                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1003                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
1004                 break;
1005         case PORT_A:
1006                 /* Internal port only for eDP. */
1007         default:
1008                 BUG();
1009         }
1010
1011         intel_hdmi->sdvox_reg = sdvox_reg;
1012
1013         if (!HAS_PCH_SPLIT(dev)) {
1014                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1015                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1016         } else if (IS_VALLEYVIEW(dev)) {
1017                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1018                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1019         } else if (IS_HASWELL(dev)) {
1020                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1021                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1022         } else if (HAS_PCH_IBX(dev)) {
1023                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1024                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1025         } else {
1026                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1027                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1028         }
1029
1030         if (IS_HASWELL(dev)) {
1031                 intel_encoder->enable = intel_enable_ddi;
1032                 intel_encoder->disable = intel_disable_ddi;
1033                 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1034                 drm_encoder_helper_add(&intel_encoder->base,
1035                                        &intel_hdmi_helper_funcs_hsw);
1036         } else {
1037                 intel_encoder->enable = intel_enable_hdmi;
1038                 intel_encoder->disable = intel_disable_hdmi;
1039                 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1040                 drm_encoder_helper_add(&intel_encoder->base,
1041                                        &intel_hdmi_helper_funcs);
1042         }
1043         intel_connector->get_hw_state = intel_connector_get_hw_state;
1044
1045
1046         intel_hdmi_add_properties(intel_hdmi, connector);
1047
1048         intel_connector_attach_encoder(intel_connector, intel_encoder);
1049         drm_sysfs_connector_add(connector);
1050
1051         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1052          * 0xd.  Failure to do so will result in spurious interrupts being
1053          * generated on the port when a cable is not attached.
1054          */
1055         if (IS_G4X(dev) && !IS_GM45(dev)) {
1056                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1057                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1058         }
1059 }