2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
36 #include "intel_drv.h"
41 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
43 struct drm_device
*dev
= intel_hdmi
->base
.base
.dev
;
44 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
45 uint32_t enabled_bits
;
47 enabled_bits
= IS_HASWELL(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
49 WARN(I915_READ(intel_hdmi
->sdvox_reg
) & enabled_bits
,
50 "HDMI port enabled, expecting disabled\n");
53 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
55 return container_of(encoder
, struct intel_hdmi
, base
.base
);
58 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
60 return container_of(intel_attached_encoder(connector
),
61 struct intel_hdmi
, base
);
64 void intel_dip_infoframe_csum(struct dip_infoframe
*frame
)
66 uint8_t *data
= (uint8_t *)frame
;
73 for (i
= 0; i
< frame
->len
+ DIP_HEADER_SIZE
; i
++)
76 frame
->checksum
= 0x100 - sum
;
79 static u32
g4x_infoframe_index(struct dip_infoframe
*frame
)
81 switch (frame
->type
) {
83 return VIDEO_DIP_SELECT_AVI
;
85 return VIDEO_DIP_SELECT_SPD
;
87 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
92 static u32
g4x_infoframe_enable(struct dip_infoframe
*frame
)
94 switch (frame
->type
) {
96 return VIDEO_DIP_ENABLE_AVI
;
98 return VIDEO_DIP_ENABLE_SPD
;
100 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
105 static u32
hsw_infoframe_enable(struct dip_infoframe
*frame
)
107 switch (frame
->type
) {
109 return VIDEO_DIP_ENABLE_AVI_HSW
;
111 return VIDEO_DIP_ENABLE_SPD_HSW
;
113 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
118 static u32
hsw_infoframe_data_reg(struct dip_infoframe
*frame
, enum pipe pipe
)
120 switch (frame
->type
) {
122 return HSW_TVIDEO_DIP_AVI_DATA(pipe
);
124 return HSW_TVIDEO_DIP_SPD_DATA(pipe
);
126 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
131 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
132 struct dip_infoframe
*frame
)
134 uint32_t *data
= (uint32_t *)frame
;
135 struct drm_device
*dev
= encoder
->dev
;
136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
137 u32 val
= I915_READ(VIDEO_DIP_CTL
);
138 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
140 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
142 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
143 val
|= g4x_infoframe_index(frame
);
145 val
&= ~g4x_infoframe_enable(frame
);
147 I915_WRITE(VIDEO_DIP_CTL
, val
);
150 for (i
= 0; i
< len
; i
+= 4) {
151 I915_WRITE(VIDEO_DIP_DATA
, *data
);
154 /* Write every possible data byte to force correct ECC calculation. */
155 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
156 I915_WRITE(VIDEO_DIP_DATA
, 0);
159 val
|= g4x_infoframe_enable(frame
);
160 val
&= ~VIDEO_DIP_FREQ_MASK
;
161 val
|= VIDEO_DIP_FREQ_VSYNC
;
163 I915_WRITE(VIDEO_DIP_CTL
, val
);
164 POSTING_READ(VIDEO_DIP_CTL
);
167 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
168 struct dip_infoframe
*frame
)
170 uint32_t *data
= (uint32_t *)frame
;
171 struct drm_device
*dev
= encoder
->dev
;
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
174 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
175 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
176 u32 val
= I915_READ(reg
);
178 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
180 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
181 val
|= g4x_infoframe_index(frame
);
183 val
&= ~g4x_infoframe_enable(frame
);
185 I915_WRITE(reg
, val
);
188 for (i
= 0; i
< len
; i
+= 4) {
189 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
192 /* Write every possible data byte to force correct ECC calculation. */
193 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
194 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
197 val
|= g4x_infoframe_enable(frame
);
198 val
&= ~VIDEO_DIP_FREQ_MASK
;
199 val
|= VIDEO_DIP_FREQ_VSYNC
;
201 I915_WRITE(reg
, val
);
205 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
206 struct dip_infoframe
*frame
)
208 uint32_t *data
= (uint32_t *)frame
;
209 struct drm_device
*dev
= encoder
->dev
;
210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
211 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
212 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
213 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
214 u32 val
= I915_READ(reg
);
216 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
218 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
219 val
|= g4x_infoframe_index(frame
);
221 /* The DIP control register spec says that we need to update the AVI
222 * infoframe without clearing its enable bit */
223 if (frame
->type
!= DIP_TYPE_AVI
)
224 val
&= ~g4x_infoframe_enable(frame
);
226 I915_WRITE(reg
, val
);
229 for (i
= 0; i
< len
; i
+= 4) {
230 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
233 /* Write every possible data byte to force correct ECC calculation. */
234 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
235 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
238 val
|= g4x_infoframe_enable(frame
);
239 val
&= ~VIDEO_DIP_FREQ_MASK
;
240 val
|= VIDEO_DIP_FREQ_VSYNC
;
242 I915_WRITE(reg
, val
);
246 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
247 struct dip_infoframe
*frame
)
249 uint32_t *data
= (uint32_t *)frame
;
250 struct drm_device
*dev
= encoder
->dev
;
251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
253 int reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
254 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
255 u32 val
= I915_READ(reg
);
257 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
259 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
260 val
|= g4x_infoframe_index(frame
);
262 val
&= ~g4x_infoframe_enable(frame
);
264 I915_WRITE(reg
, val
);
267 for (i
= 0; i
< len
; i
+= 4) {
268 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
271 /* Write every possible data byte to force correct ECC calculation. */
272 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
273 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
276 val
|= g4x_infoframe_enable(frame
);
277 val
&= ~VIDEO_DIP_FREQ_MASK
;
278 val
|= VIDEO_DIP_FREQ_VSYNC
;
280 I915_WRITE(reg
, val
);
284 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
285 struct dip_infoframe
*frame
)
287 uint32_t *data
= (uint32_t *)frame
;
288 struct drm_device
*dev
= encoder
->dev
;
289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
290 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
291 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
292 u32 data_reg
= hsw_infoframe_data_reg(frame
, intel_crtc
->pipe
);
293 unsigned int i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
294 u32 val
= I915_READ(ctl_reg
);
299 val
&= ~hsw_infoframe_enable(frame
);
300 I915_WRITE(ctl_reg
, val
);
303 for (i
= 0; i
< len
; i
+= 4) {
304 I915_WRITE(data_reg
+ i
, *data
);
307 /* Write every possible data byte to force correct ECC calculation. */
308 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
309 I915_WRITE(data_reg
+ i
, 0);
312 val
|= hsw_infoframe_enable(frame
);
313 I915_WRITE(ctl_reg
, val
);
314 POSTING_READ(ctl_reg
);
317 static void intel_set_infoframe(struct drm_encoder
*encoder
,
318 struct dip_infoframe
*frame
)
320 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
322 intel_dip_infoframe_csum(frame
);
323 intel_hdmi
->write_infoframe(encoder
, frame
);
326 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
327 struct drm_display_mode
*adjusted_mode
)
329 struct dip_infoframe avi_if
= {
330 .type
= DIP_TYPE_AVI
,
331 .ver
= DIP_VERSION_AVI
,
335 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
336 avi_if
.body
.avi
.YQ_CN_PR
|= DIP_AVI_PR_2
;
338 intel_set_infoframe(encoder
, &avi_if
);
341 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
343 struct dip_infoframe spd_if
;
345 memset(&spd_if
, 0, sizeof(spd_if
));
346 spd_if
.type
= DIP_TYPE_SPD
;
347 spd_if
.ver
= DIP_VERSION_SPD
;
348 spd_if
.len
= DIP_LEN_SPD
;
349 strcpy(spd_if
.body
.spd
.vn
, "Intel");
350 strcpy(spd_if
.body
.spd
.pd
, "Integrated gfx");
351 spd_if
.body
.spd
.sdi
= DIP_SPD_PC
;
353 intel_set_infoframe(encoder
, &spd_if
);
356 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
357 struct drm_display_mode
*adjusted_mode
)
359 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
360 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
361 u32 reg
= VIDEO_DIP_CTL
;
362 u32 val
= I915_READ(reg
);
365 assert_hdmi_port_disabled(intel_hdmi
);
367 /* If the registers were not initialized yet, they might be zeroes,
368 * which means we're selecting the AVI DIP and we're setting its
369 * frequency to once. This seems to really confuse the HW and make
370 * things stop working (the register spec says the AVI always needs to
371 * be sent every VSync). So here we avoid writing to the register more
372 * than we need and also explicitly select the AVI DIP and explicitly
373 * set its frequency to every VSync. Avoiding to write it twice seems to
374 * be enough to solve the problem, but being defensive shouldn't hurt us
376 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
378 if (!intel_hdmi
->has_hdmi_sink
) {
379 if (!(val
& VIDEO_DIP_ENABLE
))
381 val
&= ~VIDEO_DIP_ENABLE
;
382 I915_WRITE(reg
, val
);
387 switch (intel_hdmi
->sdvox_reg
) {
389 port
= VIDEO_DIP_PORT_B
;
392 port
= VIDEO_DIP_PORT_C
;
399 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
400 if (val
& VIDEO_DIP_ENABLE
) {
401 val
&= ~VIDEO_DIP_ENABLE
;
402 I915_WRITE(reg
, val
);
405 val
&= ~VIDEO_DIP_PORT_MASK
;
409 val
|= VIDEO_DIP_ENABLE
;
410 val
&= ~VIDEO_DIP_ENABLE_VENDOR
;
412 I915_WRITE(reg
, val
);
415 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
416 intel_hdmi_set_spd_infoframe(encoder
);
419 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
420 struct drm_display_mode
*adjusted_mode
)
422 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
423 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
424 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
425 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
426 u32 val
= I915_READ(reg
);
429 assert_hdmi_port_disabled(intel_hdmi
);
431 /* See the big comment in g4x_set_infoframes() */
432 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
434 if (!intel_hdmi
->has_hdmi_sink
) {
435 if (!(val
& VIDEO_DIP_ENABLE
))
437 val
&= ~VIDEO_DIP_ENABLE
;
438 I915_WRITE(reg
, val
);
443 switch (intel_hdmi
->sdvox_reg
) {
445 port
= VIDEO_DIP_PORT_B
;
448 port
= VIDEO_DIP_PORT_C
;
451 port
= VIDEO_DIP_PORT_D
;
458 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
459 if (val
& VIDEO_DIP_ENABLE
) {
460 val
&= ~VIDEO_DIP_ENABLE
;
461 I915_WRITE(reg
, val
);
464 val
&= ~VIDEO_DIP_PORT_MASK
;
468 val
|= VIDEO_DIP_ENABLE
;
469 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
470 VIDEO_DIP_ENABLE_GCP
);
472 I915_WRITE(reg
, val
);
475 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
476 intel_hdmi_set_spd_infoframe(encoder
);
479 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
480 struct drm_display_mode
*adjusted_mode
)
482 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
483 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
484 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
485 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
486 u32 val
= I915_READ(reg
);
488 assert_hdmi_port_disabled(intel_hdmi
);
490 /* See the big comment in g4x_set_infoframes() */
491 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
493 if (!intel_hdmi
->has_hdmi_sink
) {
494 if (!(val
& VIDEO_DIP_ENABLE
))
496 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
);
497 I915_WRITE(reg
, val
);
502 /* Set both together, unset both together: see the spec. */
503 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
504 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
505 VIDEO_DIP_ENABLE_GCP
);
507 I915_WRITE(reg
, val
);
510 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
511 intel_hdmi_set_spd_infoframe(encoder
);
514 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
515 struct drm_display_mode
*adjusted_mode
)
517 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
518 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
519 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
520 u32 reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
521 u32 val
= I915_READ(reg
);
523 assert_hdmi_port_disabled(intel_hdmi
);
525 /* See the big comment in g4x_set_infoframes() */
526 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
528 if (!intel_hdmi
->has_hdmi_sink
) {
529 if (!(val
& VIDEO_DIP_ENABLE
))
531 val
&= ~VIDEO_DIP_ENABLE
;
532 I915_WRITE(reg
, val
);
537 val
|= VIDEO_DIP_ENABLE
;
538 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
539 VIDEO_DIP_ENABLE_GCP
);
541 I915_WRITE(reg
, val
);
544 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
545 intel_hdmi_set_spd_infoframe(encoder
);
548 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
549 struct drm_display_mode
*adjusted_mode
)
551 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
552 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
553 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
554 u32 reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
555 u32 val
= I915_READ(reg
);
557 assert_hdmi_port_disabled(intel_hdmi
);
559 if (!intel_hdmi
->has_hdmi_sink
) {
565 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_GCP_HSW
|
566 VIDEO_DIP_ENABLE_VS_HSW
| VIDEO_DIP_ENABLE_GMP_HSW
);
568 I915_WRITE(reg
, val
);
571 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
572 intel_hdmi_set_spd_infoframe(encoder
);
575 static void intel_hdmi_mode_set(struct drm_encoder
*encoder
,
576 struct drm_display_mode
*mode
,
577 struct drm_display_mode
*adjusted_mode
)
579 struct drm_device
*dev
= encoder
->dev
;
580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
581 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
582 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
585 sdvox
= SDVO_ENCODING_HDMI
;
586 if (!HAS_PCH_SPLIT(dev
))
587 sdvox
|= intel_hdmi
->color_range
;
588 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
589 sdvox
|= SDVO_VSYNC_ACTIVE_HIGH
;
590 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
591 sdvox
|= SDVO_HSYNC_ACTIVE_HIGH
;
593 if (intel_crtc
->bpp
> 24)
594 sdvox
|= COLOR_FORMAT_12bpc
;
596 sdvox
|= COLOR_FORMAT_8bpc
;
598 /* Required on CPT */
599 if (intel_hdmi
->has_hdmi_sink
&& HAS_PCH_CPT(dev
))
600 sdvox
|= HDMI_MODE_SELECT
;
602 if (intel_hdmi
->has_audio
) {
603 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
604 pipe_name(intel_crtc
->pipe
));
605 sdvox
|= SDVO_AUDIO_ENABLE
;
606 sdvox
|= SDVO_NULL_PACKETS_DURING_VSYNC
;
607 intel_write_eld(encoder
, adjusted_mode
);
610 if (HAS_PCH_CPT(dev
))
611 sdvox
|= PORT_TRANS_SEL_CPT(intel_crtc
->pipe
);
612 else if (intel_crtc
->pipe
== PIPE_B
)
613 sdvox
|= SDVO_PIPE_B_SELECT
;
615 I915_WRITE(intel_hdmi
->sdvox_reg
, sdvox
);
616 POSTING_READ(intel_hdmi
->sdvox_reg
);
618 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
621 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
624 struct drm_device
*dev
= encoder
->base
.dev
;
625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
626 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
629 tmp
= I915_READ(intel_hdmi
->sdvox_reg
);
631 if (!(tmp
& SDVO_ENABLE
))
634 if (HAS_PCH_CPT(dev
))
635 *pipe
= PORT_TO_PIPE_CPT(tmp
);
637 *pipe
= PORT_TO_PIPE(tmp
);
642 static void intel_enable_hdmi(struct intel_encoder
*encoder
)
644 struct drm_device
*dev
= encoder
->base
.dev
;
645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
646 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
648 u32 enable_bits
= SDVO_ENABLE
;
650 if (intel_hdmi
->has_audio
)
651 enable_bits
|= SDVO_AUDIO_ENABLE
;
653 temp
= I915_READ(intel_hdmi
->sdvox_reg
);
655 /* HW workaround for IBX, we need to move the port to transcoder A
656 * before disabling it. */
657 if (HAS_PCH_IBX(dev
)) {
658 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
659 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
661 /* Restore the transcoder select bit. */
663 enable_bits
|= SDVO_PIPE_B_SELECT
;
666 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
667 * we do this anyway which shows more stable in testing.
669 if (HAS_PCH_SPLIT(dev
)) {
670 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
& ~SDVO_ENABLE
);
671 POSTING_READ(intel_hdmi
->sdvox_reg
);
676 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
677 POSTING_READ(intel_hdmi
->sdvox_reg
);
679 /* HW workaround, need to write this twice for issue that may result
680 * in first write getting masked.
682 if (HAS_PCH_SPLIT(dev
)) {
683 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
684 POSTING_READ(intel_hdmi
->sdvox_reg
);
688 static void intel_disable_hdmi(struct intel_encoder
*encoder
)
690 struct drm_device
*dev
= encoder
->base
.dev
;
691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
692 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
694 u32 enable_bits
= SDVO_ENABLE
| SDVO_AUDIO_ENABLE
;
696 temp
= I915_READ(intel_hdmi
->sdvox_reg
);
698 /* HW workaround for IBX, we need to move the port to transcoder A
699 * before disabling it. */
700 if (HAS_PCH_IBX(dev
)) {
701 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
702 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
704 if (temp
& SDVO_PIPE_B_SELECT
) {
705 temp
&= ~SDVO_PIPE_B_SELECT
;
706 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
707 POSTING_READ(intel_hdmi
->sdvox_reg
);
709 /* Again we need to write this twice. */
710 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
711 POSTING_READ(intel_hdmi
->sdvox_reg
);
713 /* Transcoder selection bits only update
714 * effectively on vblank. */
716 intel_wait_for_vblank(dev
, pipe
);
722 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
723 * we do this anyway which shows more stable in testing.
725 if (HAS_PCH_SPLIT(dev
)) {
726 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
& ~SDVO_ENABLE
);
727 POSTING_READ(intel_hdmi
->sdvox_reg
);
730 temp
&= ~enable_bits
;
732 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
733 POSTING_READ(intel_hdmi
->sdvox_reg
);
735 /* HW workaround, need to write this twice for issue that may result
736 * in first write getting masked.
738 if (HAS_PCH_SPLIT(dev
)) {
739 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
740 POSTING_READ(intel_hdmi
->sdvox_reg
);
744 static int intel_hdmi_mode_valid(struct drm_connector
*connector
,
745 struct drm_display_mode
*mode
)
747 if (mode
->clock
> 165000)
748 return MODE_CLOCK_HIGH
;
749 if (mode
->clock
< 20000)
750 return MODE_CLOCK_LOW
;
752 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
753 return MODE_NO_DBLESCAN
;
758 static bool intel_hdmi_mode_fixup(struct drm_encoder
*encoder
,
759 const struct drm_display_mode
*mode
,
760 struct drm_display_mode
*adjusted_mode
)
765 static bool g4x_hdmi_connected(struct intel_hdmi
*intel_hdmi
)
767 struct drm_device
*dev
= intel_hdmi
->base
.base
.dev
;
768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
771 switch (intel_hdmi
->sdvox_reg
) {
773 bit
= HDMIB_HOTPLUG_LIVE_STATUS
;
776 bit
= HDMIC_HOTPLUG_LIVE_STATUS
;
783 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
786 static enum drm_connector_status
787 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
789 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
790 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
792 enum drm_connector_status status
= connector_status_disconnected
;
794 if (IS_G4X(connector
->dev
) && !g4x_hdmi_connected(intel_hdmi
))
797 intel_hdmi
->has_hdmi_sink
= false;
798 intel_hdmi
->has_audio
= false;
799 edid
= drm_get_edid(connector
,
800 intel_gmbus_get_adapter(dev_priv
,
801 intel_hdmi
->ddc_bus
));
804 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
805 status
= connector_status_connected
;
806 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
807 intel_hdmi
->has_hdmi_sink
=
808 drm_detect_hdmi_monitor(edid
);
809 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
814 if (status
== connector_status_connected
) {
815 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
816 intel_hdmi
->has_audio
=
817 (intel_hdmi
->force_audio
== HDMI_AUDIO_ON
);
823 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
825 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
826 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
828 /* We should parse the EDID data and find out if it's an HDMI sink so
829 * we can send audio to it.
832 return intel_ddc_get_modes(connector
,
833 intel_gmbus_get_adapter(dev_priv
,
834 intel_hdmi
->ddc_bus
));
838 intel_hdmi_detect_audio(struct drm_connector
*connector
)
840 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
841 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
843 bool has_audio
= false;
845 edid
= drm_get_edid(connector
,
846 intel_gmbus_get_adapter(dev_priv
,
847 intel_hdmi
->ddc_bus
));
849 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
)
850 has_audio
= drm_detect_monitor_audio(edid
);
858 intel_hdmi_set_property(struct drm_connector
*connector
,
859 struct drm_property
*property
,
862 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
863 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
866 ret
= drm_connector_property_set_value(connector
, property
, val
);
870 if (property
== dev_priv
->force_audio_property
) {
871 enum hdmi_force_audio i
= val
;
874 if (i
== intel_hdmi
->force_audio
)
877 intel_hdmi
->force_audio
= i
;
879 if (i
== HDMI_AUDIO_AUTO
)
880 has_audio
= intel_hdmi_detect_audio(connector
);
882 has_audio
= (i
== HDMI_AUDIO_ON
);
884 if (i
== HDMI_AUDIO_OFF_DVI
)
885 intel_hdmi
->has_hdmi_sink
= 0;
887 intel_hdmi
->has_audio
= has_audio
;
891 if (property
== dev_priv
->broadcast_rgb_property
) {
892 if (val
== !!intel_hdmi
->color_range
)
895 intel_hdmi
->color_range
= val
? SDVO_COLOR_RANGE_16_235
: 0;
902 if (intel_hdmi
->base
.base
.crtc
) {
903 struct drm_crtc
*crtc
= intel_hdmi
->base
.base
.crtc
;
904 intel_set_mode(crtc
, &crtc
->mode
,
905 crtc
->x
, crtc
->y
, crtc
->fb
);
911 static void intel_hdmi_destroy(struct drm_connector
*connector
)
913 drm_sysfs_connector_remove(connector
);
914 drm_connector_cleanup(connector
);
918 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw
= {
919 .mode_fixup
= intel_hdmi_mode_fixup
,
920 .mode_set
= intel_ddi_mode_set
,
921 .disable
= intel_encoder_noop
,
924 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs
= {
925 .mode_fixup
= intel_hdmi_mode_fixup
,
926 .mode_set
= intel_hdmi_mode_set
,
927 .disable
= intel_encoder_noop
,
930 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
931 .dpms
= intel_connector_dpms
,
932 .detect
= intel_hdmi_detect
,
933 .fill_modes
= drm_helper_probe_single_connector_modes
,
934 .set_property
= intel_hdmi_set_property
,
935 .destroy
= intel_hdmi_destroy
,
938 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
939 .get_modes
= intel_hdmi_get_modes
,
940 .mode_valid
= intel_hdmi_mode_valid
,
941 .best_encoder
= intel_best_encoder
,
944 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
945 .destroy
= intel_encoder_destroy
,
949 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
951 intel_attach_force_audio_property(connector
);
952 intel_attach_broadcast_rgb_property(connector
);
955 void intel_hdmi_init(struct drm_device
*dev
, int sdvox_reg
, enum port port
)
957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
958 struct drm_connector
*connector
;
959 struct intel_encoder
*intel_encoder
;
960 struct intel_connector
*intel_connector
;
961 struct intel_hdmi
*intel_hdmi
;
963 intel_hdmi
= kzalloc(sizeof(struct intel_hdmi
), GFP_KERNEL
);
967 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
968 if (!intel_connector
) {
973 intel_encoder
= &intel_hdmi
->base
;
974 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
975 DRM_MODE_ENCODER_TMDS
);
977 connector
= &intel_connector
->base
;
978 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
979 DRM_MODE_CONNECTOR_HDMIA
);
980 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
982 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
984 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
985 connector
->interlace_allowed
= 1;
986 connector
->doublescan_allowed
= 0;
987 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
989 intel_encoder
->cloneable
= false;
991 intel_hdmi
->ddi_port
= port
;
994 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
995 dev_priv
->hotplug_supported_mask
|= HDMIB_HOTPLUG_INT_STATUS
;
998 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
999 dev_priv
->hotplug_supported_mask
|= HDMIC_HOTPLUG_INT_STATUS
;
1002 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
1003 dev_priv
->hotplug_supported_mask
|= HDMID_HOTPLUG_INT_STATUS
;
1006 /* Internal port only for eDP. */
1011 intel_hdmi
->sdvox_reg
= sdvox_reg
;
1013 if (!HAS_PCH_SPLIT(dev
)) {
1014 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
1015 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
1016 } else if (IS_VALLEYVIEW(dev
)) {
1017 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
1018 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
1019 } else if (IS_HASWELL(dev
)) {
1020 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
1021 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
1022 } else if (HAS_PCH_IBX(dev
)) {
1023 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
1024 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
1026 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
1027 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
1030 if (IS_HASWELL(dev
)) {
1031 intel_encoder
->enable
= intel_enable_ddi
;
1032 intel_encoder
->disable
= intel_disable_ddi
;
1033 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1034 drm_encoder_helper_add(&intel_encoder
->base
,
1035 &intel_hdmi_helper_funcs_hsw
);
1037 intel_encoder
->enable
= intel_enable_hdmi
;
1038 intel_encoder
->disable
= intel_disable_hdmi
;
1039 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
1040 drm_encoder_helper_add(&intel_encoder
->base
,
1041 &intel_hdmi_helper_funcs
);
1043 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1046 intel_hdmi_add_properties(intel_hdmi
, connector
);
1048 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1049 drm_sysfs_connector_add(connector
);
1051 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1052 * 0xd. Failure to do so will result in spurious interrupts being
1053 * generated on the port when a cable is not attached.
1055 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1056 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1057 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);