drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41 {
  42         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43 }
  44
  45 static void
  46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47 {
  48         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         uint32_t enabled_bits;
  51
  52         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53
  54         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55              "HDMI port enabled, expecting disabled\n");
  56 }
  57
  58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59 {
  60         struct intel_digital_port *intel_dig_port =
  61                 container_of(encoder, struct intel_digital_port, base.base);
  62         return &intel_dig_port->hdmi;
  63 }
  64
  65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66 {
  67         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68 }
  69
  70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71 {
  72         switch (type) {
  73         case HDMI_INFOFRAME_TYPE_AVI:
  74                 return VIDEO_DIP_SELECT_AVI;
  75         case HDMI_INFOFRAME_TYPE_SPD:
  76                 return VIDEO_DIP_SELECT_SPD;
  77         case HDMI_INFOFRAME_TYPE_VENDOR:
  78                 return VIDEO_DIP_SELECT_VENDOR;
  79         default:
  80                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  81                 return 0;
  82         }
  83 }
  84
  85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  86 {
  87         switch (type) {
  88         case HDMI_INFOFRAME_TYPE_AVI:
  89                 return VIDEO_DIP_ENABLE_AVI;
  90         case HDMI_INFOFRAME_TYPE_SPD:
  91                 return VIDEO_DIP_ENABLE_SPD;
  92         case HDMI_INFOFRAME_TYPE_VENDOR:
  93                 return VIDEO_DIP_ENABLE_VENDOR;
  94         default:
  95                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  96                 return 0;
  97         }
  98 }
  99
 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 101 {
 102         switch (type) {
 103         case HDMI_INFOFRAME_TYPE_AVI:
 104                 return VIDEO_DIP_ENABLE_AVI_HSW;
 105         case HDMI_INFOFRAME_TYPE_SPD:
 106                 return VIDEO_DIP_ENABLE_SPD_HSW;
 107         case HDMI_INFOFRAME_TYPE_VENDOR:
 108                 return VIDEO_DIP_ENABLE_VS_HSW;
 109         default:
 110                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 111                 return 0;
 112         }
 113 }
 114
 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 116                                   enum transcoder cpu_transcoder,
 117                                   struct drm_i915_private *dev_priv)
 118 {
 119         switch (type) {
 120         case HDMI_INFOFRAME_TYPE_AVI:
 121                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 122         case HDMI_INFOFRAME_TYPE_SPD:
 123                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 124         case HDMI_INFOFRAME_TYPE_VENDOR:
 125                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 126         default:
 127                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 128                 return 0;
 129         }
 130 }
 131
 132 static void g4x_write_infoframe(struct drm_encoder *encoder,
 133                                 enum hdmi_infoframe_type type,
 134                                 const void *frame, ssize_t len)
 135 {
 136         const uint32_t *data = frame;
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         u32 val = I915_READ(VIDEO_DIP_CTL);
 140         int i;
 141
 142         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 143
 144         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 145         val |= g4x_infoframe_index(type);
 146
 147         val &= ~g4x_infoframe_enable(type);
 148
 149         I915_WRITE(VIDEO_DIP_CTL, val);
 150
 151         mmiowb();
 152         for (i = 0; i < len; i += 4) {
 153                 I915_WRITE(VIDEO_DIP_DATA, *data);
 154                 data++;
 155         }
 156         /* Write every possible data byte to force correct ECC calculation. */
 157         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 158                 I915_WRITE(VIDEO_DIP_DATA, 0);
 159         mmiowb();
 160
 161         val |= g4x_infoframe_enable(type);
 162         val &= ~VIDEO_DIP_FREQ_MASK;
 163         val |= VIDEO_DIP_FREQ_VSYNC;
 164
 165         I915_WRITE(VIDEO_DIP_CTL, val);
 166         POSTING_READ(VIDEO_DIP_CTL);
 167 }
 168
 169 static void ibx_write_infoframe(struct drm_encoder *encoder,
 170                                 enum hdmi_infoframe_type type,
 171                                 const void *frame, ssize_t len)
 172 {
 173         const uint32_t *data = frame;
 174         struct drm_device *dev = encoder->dev;
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 177         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 178         u32 val = I915_READ(reg);
 179
 180         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 181
 182         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 183         val |= g4x_infoframe_index(type);
 184
 185         val &= ~g4x_infoframe_enable(type);
 186
 187         I915_WRITE(reg, val);
 188
 189         mmiowb();
 190         for (i = 0; i < len; i += 4) {
 191                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 192                 data++;
 193         }
 194         /* Write every possible data byte to force correct ECC calculation. */
 195         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 196                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 197         mmiowb();
 198
 199         val |= g4x_infoframe_enable(type);
 200         val &= ~VIDEO_DIP_FREQ_MASK;
 201         val |= VIDEO_DIP_FREQ_VSYNC;
 202
 203         I915_WRITE(reg, val);
 204         POSTING_READ(reg);
 205 }
 206
 207 static void cpt_write_infoframe(struct drm_encoder *encoder,
 208                                 enum hdmi_infoframe_type type,
 209                                 const void *frame, ssize_t len)
 210 {
 211         const uint32_t *data = frame;
 212         struct drm_device *dev = encoder->dev;
 213         struct drm_i915_private *dev_priv = dev->dev_private;
 214         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 215         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 216         u32 val = I915_READ(reg);
 217
 218         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 219
 220         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 221         val |= g4x_infoframe_index(type);
 222
 223         /* The DIP control register spec says that we need to update the AVI
 224          * infoframe without clearing its enable bit */
 225         if (type != HDMI_INFOFRAME_TYPE_AVI)
 226                 val &= ~g4x_infoframe_enable(type);
 227
 228         I915_WRITE(reg, val);
 229
 230         mmiowb();
 231         for (i = 0; i < len; i += 4) {
 232                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 233                 data++;
 234         }
 235         /* Write every possible data byte to force correct ECC calculation. */
 236         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 237                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 238         mmiowb();
 239
 240         val |= g4x_infoframe_enable(type);
 241         val &= ~VIDEO_DIP_FREQ_MASK;
 242         val |= VIDEO_DIP_FREQ_VSYNC;
 243
 244         I915_WRITE(reg, val);
 245         POSTING_READ(reg);
 246 }
 247
 248 static void vlv_write_infoframe(struct drm_encoder *encoder,
 249                                 enum hdmi_infoframe_type type,
 250                                 const void *frame, ssize_t len)
 251 {
 252         const uint32_t *data = frame;
 253         struct drm_device *dev = encoder->dev;
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 256         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 257         u32 val = I915_READ(reg);
 258
 259         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 260
 261         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 262         val |= g4x_infoframe_index(type);
 263
 264         val &= ~g4x_infoframe_enable(type);
 265
 266         I915_WRITE(reg, val);
 267
 268         mmiowb();
 269         for (i = 0; i < len; i += 4) {
 270                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 271                 data++;
 272         }
 273         /* Write every possible data byte to force correct ECC calculation. */
 274         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 275                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 276         mmiowb();
 277
 278         val |= g4x_infoframe_enable(type);
 279         val &= ~VIDEO_DIP_FREQ_MASK;
 280         val |= VIDEO_DIP_FREQ_VSYNC;
 281
 282         I915_WRITE(reg, val);
 283         POSTING_READ(reg);
 284 }
 285
 286 static void hsw_write_infoframe(struct drm_encoder *encoder,
 287                                 enum hdmi_infoframe_type type,
 288                                 const void *frame, ssize_t len)
 289 {
 290         const uint32_t *data = frame;
 291         struct drm_device *dev = encoder->dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 294         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 295         u32 data_reg;
 296         int i;
 297         u32 val = I915_READ(ctl_reg);
 298
 299         data_reg = hsw_infoframe_data_reg(type,
 300                                           intel_crtc->config.cpu_transcoder,
 301                                           dev_priv);
 302         if (data_reg == 0)
 303                 return;
 304
 305         val &= ~hsw_infoframe_enable(type);
 306         I915_WRITE(ctl_reg, val);
 307
 308         mmiowb();
 309         for (i = 0; i < len; i += 4) {
 310                 I915_WRITE(data_reg + i, *data);
 311                 data++;
 312         }
 313         /* Write every possible data byte to force correct ECC calculation. */
 314         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 315                 I915_WRITE(data_reg + i, 0);
 316         mmiowb();
 317
 318         val |= hsw_infoframe_enable(type);
 319         I915_WRITE(ctl_reg, val);
 320         POSTING_READ(ctl_reg);
 321 }
 322
 323 /*
 324  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 325  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 326  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 327  * used for both technologies.
 328  *
 329  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 330  * DW1:       DB3       | DB2 | DB1 | DB0
 331  * DW2:       DB7       | DB6 | DB5 | DB4
 332  * DW3: ...
 333  *
 334  * (HB is Header Byte, DB is Data Byte)
 335  *
 336  * The hdmi pack() functions don't know about that hardware specific hole so we
 337  * trick them by giving an offset into the buffer and moving back the header
 338  * bytes by one.
 339  */
 340 static void intel_write_infoframe(struct drm_encoder *encoder,
 341                                   union hdmi_infoframe *frame)
 342 {
 343         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 344         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 345         ssize_t len;
 346
 347         /* see comment above for the reason for this offset */
 348         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 349         if (len < 0)
 350                 return;
 351
 352         /* Insert the 'hole' (see big comment above) at position 3 */
 353         buffer[0] = buffer[1];
 354         buffer[1] = buffer[2];
 355         buffer[2] = buffer[3];
 356         buffer[3] = 0;
 357         len++;
 358
 359         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 360 }
 361
 362 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 363                                          struct drm_display_mode *adjusted_mode)
 364 {
 365         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 366         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 367         union hdmi_infoframe frame;
 368         int ret;
 369
 370         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 371                                                        adjusted_mode);
 372         if (ret < 0) {
 373                 DRM_ERROR("couldn't fill AVI infoframe\n");
 374                 return;
 375         }
 376
 377         if (intel_hdmi->rgb_quant_range_selectable) {
 378                 if (intel_crtc->config.limited_color_range)
 379                         frame.avi.quantization_range =
 380                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 381                 else
 382                         frame.avi.quantization_range =
 383                                 HDMI_QUANTIZATION_RANGE_FULL;
 384         }
 385
 386         intel_write_infoframe(encoder, &frame);
 387 }
 388
 389 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 390 {
 391         union hdmi_infoframe frame;
 392         int ret;
 393
 394         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 395         if (ret < 0) {
 396                 DRM_ERROR("couldn't fill SPD infoframe\n");
 397                 return;
 398         }
 399
 400         frame.spd.sdi = HDMI_SPD_SDI_PC;
 401
 402         intel_write_infoframe(encoder, &frame);
 403 }
 404
 405 static void
 406 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 407                               struct drm_display_mode *adjusted_mode)
 408 {
 409         union hdmi_infoframe frame;
 410         int ret;
 411
 412         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 413                                                           adjusted_mode);
 414         if (ret < 0)
 415                 return;
 416
 417         intel_write_infoframe(encoder, &frame);
 418 }
 419
 420 static void g4x_set_infoframes(struct drm_encoder *encoder,
 421                                bool enable,
 422                                struct drm_display_mode *adjusted_mode)
 423 {
 424         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 425         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 426         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 427         u32 reg = VIDEO_DIP_CTL;
 428         u32 val = I915_READ(reg);
 429         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 430
 431         assert_hdmi_port_disabled(intel_hdmi);
 432
 433         /* If the registers were not initialized yet, they might be zeroes,
 434          * which means we're selecting the AVI DIP and we're setting its
 435          * frequency to once. This seems to really confuse the HW and make
 436          * things stop working (the register spec says the AVI always needs to
 437          * be sent every VSync). So here we avoid writing to the register more
 438          * than we need and also explicitly select the AVI DIP and explicitly
 439          * set its frequency to every VSync. Avoiding to write it twice seems to
 440          * be enough to solve the problem, but being defensive shouldn't hurt us
 441          * either. */
 442         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 443
 444         if (!enable) {
 445                 if (!(val & VIDEO_DIP_ENABLE))
 446                         return;
 447                 val &= ~VIDEO_DIP_ENABLE;
 448                 I915_WRITE(reg, val);
 449                 POSTING_READ(reg);
 450                 return;
 451         }
 452
 453         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 454                 if (val & VIDEO_DIP_ENABLE) {
 455                         val &= ~VIDEO_DIP_ENABLE;
 456                         I915_WRITE(reg, val);
 457                         POSTING_READ(reg);
 458                 }
 459                 val &= ~VIDEO_DIP_PORT_MASK;
 460                 val |= port;
 461         }
 462
 463         val |= VIDEO_DIP_ENABLE;
 464         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 465
 466         I915_WRITE(reg, val);
 467         POSTING_READ(reg);
 468
 469         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 470         intel_hdmi_set_spd_infoframe(encoder);
 471         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 472 }
 473
 474 static void ibx_set_infoframes(struct drm_encoder *encoder,
 475                                bool enable,
 476                                struct drm_display_mode *adjusted_mode)
 477 {
 478         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 479         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 480         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 481         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 482         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 483         u32 val = I915_READ(reg);
 484         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 485
 486         assert_hdmi_port_disabled(intel_hdmi);
 487
 488         /* See the big comment in g4x_set_infoframes() */
 489         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 490
 491         if (!enable) {
 492                 if (!(val & VIDEO_DIP_ENABLE))
 493                         return;
 494                 val &= ~VIDEO_DIP_ENABLE;
 495                 I915_WRITE(reg, val);
 496                 POSTING_READ(reg);
 497                 return;
 498         }
 499
 500         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 501                 if (val & VIDEO_DIP_ENABLE) {
 502                         val &= ~VIDEO_DIP_ENABLE;
 503                         I915_WRITE(reg, val);
 504                         POSTING_READ(reg);
 505                 }
 506                 val &= ~VIDEO_DIP_PORT_MASK;
 507                 val |= port;
 508         }
 509
 510         val |= VIDEO_DIP_ENABLE;
 511         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 512                  VIDEO_DIP_ENABLE_GCP);
 513
 514         I915_WRITE(reg, val);
 515         POSTING_READ(reg);
 516
 517         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 518         intel_hdmi_set_spd_infoframe(encoder);
 519         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 520 }
 521
 522 static void cpt_set_infoframes(struct drm_encoder *encoder,
 523                                bool enable,
 524                                struct drm_display_mode *adjusted_mode)
 525 {
 526         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 527         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 528         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 529         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 530         u32 val = I915_READ(reg);
 531
 532         assert_hdmi_port_disabled(intel_hdmi);
 533
 534         /* See the big comment in g4x_set_infoframes() */
 535         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 536
 537         if (!enable) {
 538                 if (!(val & VIDEO_DIP_ENABLE))
 539                         return;
 540                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 541                 I915_WRITE(reg, val);
 542                 POSTING_READ(reg);
 543                 return;
 544         }
 545
 546         /* Set both together, unset both together: see the spec. */
 547         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 548         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 549                  VIDEO_DIP_ENABLE_GCP);
 550
 551         I915_WRITE(reg, val);
 552         POSTING_READ(reg);
 553
 554         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 555         intel_hdmi_set_spd_infoframe(encoder);
 556         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 557 }
 558
 559 static void vlv_set_infoframes(struct drm_encoder *encoder,
 560                                bool enable,
 561                                struct drm_display_mode *adjusted_mode)
 562 {
 563         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 564         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 565         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 566         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 567         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 568         u32 val = I915_READ(reg);
 569         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 570
 571         assert_hdmi_port_disabled(intel_hdmi);
 572
 573         /* See the big comment in g4x_set_infoframes() */
 574         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 575
 576         if (!enable) {
 577                 if (!(val & VIDEO_DIP_ENABLE))
 578                         return;
 579                 val &= ~VIDEO_DIP_ENABLE;
 580                 I915_WRITE(reg, val);
 581                 POSTING_READ(reg);
 582                 return;
 583         }
 584
 585         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 586                 if (val & VIDEO_DIP_ENABLE) {
 587                         val &= ~VIDEO_DIP_ENABLE;
 588                         I915_WRITE(reg, val);
 589                         POSTING_READ(reg);
 590                 }
 591                 val &= ~VIDEO_DIP_PORT_MASK;
 592                 val |= port;
 593         }
 594
 595         val |= VIDEO_DIP_ENABLE;
 596         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 597                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 598
 599         I915_WRITE(reg, val);
 600         POSTING_READ(reg);
 601
 602         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 603         intel_hdmi_set_spd_infoframe(encoder);
 604         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 605 }
 606
 607 static void hsw_set_infoframes(struct drm_encoder *encoder,
 608                                bool enable,
 609                                struct drm_display_mode *adjusted_mode)
 610 {
 611         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 612         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 613         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 614         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 615         u32 val = I915_READ(reg);
 616
 617         assert_hdmi_port_disabled(intel_hdmi);
 618
 619         if (!enable) {
 620                 I915_WRITE(reg, 0);
 621                 POSTING_READ(reg);
 622                 return;
 623         }
 624
 625         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 626                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 627
 628         I915_WRITE(reg, val);
 629         POSTING_READ(reg);
 630
 631         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 632         intel_hdmi_set_spd_infoframe(encoder);
 633         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 634 }
 635
 636 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 637 {
 638         struct drm_device *dev = encoder->base.dev;
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 641         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 642         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 643         u32 hdmi_val;
 644
 645         hdmi_val = SDVO_ENCODING_HDMI;
 646         if (!HAS_PCH_SPLIT(dev))
 647                 hdmi_val |= intel_hdmi->color_range;
 648         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 649                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 650         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 651                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 652
 653         if (crtc->config.pipe_bpp > 24)
 654                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 655         else
 656                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 657
 658         if (crtc->config.has_hdmi_sink)
 659                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 660
 661         if (crtc->config.has_audio) {
 662                 WARN_ON(!crtc->config.has_hdmi_sink);
 663                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 664                                  pipe_name(crtc->pipe));
 665                 hdmi_val |= SDVO_AUDIO_ENABLE;
 666                 intel_write_eld(&encoder->base, adjusted_mode);
 667         }
 668
 669         if (HAS_PCH_CPT(dev))
 670                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 671         else if (IS_CHERRYVIEW(dev))
 672                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 673         else
 674                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 675
 676         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 677         POSTING_READ(intel_hdmi->hdmi_reg);
 678 }
 679
 680 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 681                                     enum pipe *pipe)
 682 {
 683         struct drm_device *dev = encoder->base.dev;
 684         struct drm_i915_private *dev_priv = dev->dev_private;
 685         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 686         enum intel_display_power_domain power_domain;
 687         u32 tmp;
 688
 689         power_domain = intel_display_port_power_domain(encoder);
 690         if (!intel_display_power_enabled(dev_priv, power_domain))
 691                 return false;
 692
 693         tmp = I915_READ(intel_hdmi->hdmi_reg);
 694
 695         if (!(tmp & SDVO_ENABLE))
 696                 return false;
 697
 698         if (HAS_PCH_CPT(dev))
 699                 *pipe = PORT_TO_PIPE_CPT(tmp);
 700         else if (IS_CHERRYVIEW(dev))
 701                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 702         else
 703                 *pipe = PORT_TO_PIPE(tmp);
 704
 705         return true;
 706 }
 707
 708 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 709                                   struct intel_crtc_config *pipe_config)
 710 {
 711         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 712         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 713         u32 tmp, flags = 0;
 714         int dotclock;
 715
 716         tmp = I915_READ(intel_hdmi->hdmi_reg);
 717
 718         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 719                 flags |= DRM_MODE_FLAG_PHSYNC;
 720         else
 721                 flags |= DRM_MODE_FLAG_NHSYNC;
 722
 723         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 724                 flags |= DRM_MODE_FLAG_PVSYNC;
 725         else
 726                 flags |= DRM_MODE_FLAG_NVSYNC;
 727
 728         if (tmp & HDMI_MODE_SELECT_HDMI)
 729                 pipe_config->has_hdmi_sink = true;
 730
 731         if (tmp & HDMI_MODE_SELECT_HDMI)
 732                 pipe_config->has_audio = true;
 733
 734         pipe_config->adjusted_mode.flags |= flags;
 735
 736         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 737                 dotclock = pipe_config->port_clock * 2 / 3;
 738         else
 739                 dotclock = pipe_config->port_clock;
 740
 741         if (HAS_PCH_SPLIT(dev_priv->dev))
 742                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 743
 744         pipe_config->adjusted_mode.crtc_clock = dotclock;
 745 }
 746
 747 static void intel_enable_hdmi(struct intel_encoder *encoder)
 748 {
 749         struct drm_device *dev = encoder->base.dev;
 750         struct drm_i915_private *dev_priv = dev->dev_private;
 751         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 752         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 753         u32 temp;
 754         u32 enable_bits = SDVO_ENABLE;
 755
 756         if (intel_crtc->config.has_audio)
 757                 enable_bits |= SDVO_AUDIO_ENABLE;
 758
 759         temp = I915_READ(intel_hdmi->hdmi_reg);
 760
 761         /* HW workaround for IBX, we need to move the port to transcoder A
 762          * before disabling it, so restore the transcoder select bit here. */
 763         if (HAS_PCH_IBX(dev))
 764                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 765
 766         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 767          * we do this anyway which shows more stable in testing.
 768          */
 769         if (HAS_PCH_SPLIT(dev)) {
 770                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 771                 POSTING_READ(intel_hdmi->hdmi_reg);
 772         }
 773
 774         temp |= enable_bits;
 775
 776         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 777         POSTING_READ(intel_hdmi->hdmi_reg);
 778
 779         /* HW workaround, need to write this twice for issue that may result
 780          * in first write getting masked.
 781          */
 782         if (HAS_PCH_SPLIT(dev)) {
 783                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 784                 POSTING_READ(intel_hdmi->hdmi_reg);
 785         }
 786 }
 787
 788 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 789 {
 790 }
 791
 792 static void intel_disable_hdmi(struct intel_encoder *encoder)
 793 {
 794         struct drm_device *dev = encoder->base.dev;
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 797         u32 temp;
 798         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 799
 800         temp = I915_READ(intel_hdmi->hdmi_reg);
 801
 802         /* HW workaround for IBX, we need to move the port to transcoder A
 803          * before disabling it. */
 804         if (HAS_PCH_IBX(dev)) {
 805                 struct drm_crtc *crtc = encoder->base.crtc;
 806                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 807
 808                 if (temp & SDVO_PIPE_B_SELECT) {
 809                         temp &= ~SDVO_PIPE_B_SELECT;
 810                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 811                         POSTING_READ(intel_hdmi->hdmi_reg);
 812
 813                         /* Again we need to write this twice. */
 814                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 815                         POSTING_READ(intel_hdmi->hdmi_reg);
 816
 817                         /* Transcoder selection bits only update
 818                          * effectively on vblank. */
 819                         if (crtc)
 820                                 intel_wait_for_vblank(dev, pipe);
 821                         else
 822                                 msleep(50);
 823                 }
 824         }
 825
 826         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 827          * we do this anyway which shows more stable in testing.
 828          */
 829         if (HAS_PCH_SPLIT(dev)) {
 830                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 831                 POSTING_READ(intel_hdmi->hdmi_reg);
 832         }
 833
 834         temp &= ~enable_bits;
 835
 836         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 837         POSTING_READ(intel_hdmi->hdmi_reg);
 838
 839         /* HW workaround, need to write this twice for issue that may result
 840          * in first write getting masked.
 841          */
 842         if (HAS_PCH_SPLIT(dev)) {
 843                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 844                 POSTING_READ(intel_hdmi->hdmi_reg);
 845         }
 846 }
 847
 848 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 849 {
 850         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 851
 852         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 853                 return 165000;
 854         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 855                 return 300000;
 856         else
 857                 return 225000;
 858 }
 859
 860 static enum drm_mode_status
 861 intel_hdmi_mode_valid(struct drm_connector *connector,
 862                       struct drm_display_mode *mode)
 863 {
 864         if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 865                                                true))
 866                 return MODE_CLOCK_HIGH;
 867         if (mode->clock < 20000)
 868                 return MODE_CLOCK_LOW;
 869
 870         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 871                 return MODE_NO_DBLESCAN;
 872
 873         return MODE_OK;
 874 }
 875
 876 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
 877 {
 878         struct drm_device *dev = crtc->base.dev;
 879         struct intel_encoder *encoder;
 880         int count = 0, count_hdmi = 0;
 881
 882         if (!HAS_PCH_SPLIT(dev))
 883                 return false;
 884
 885         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 886                 if (encoder->new_crtc != crtc)
 887                         continue;
 888
 889                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 890                 count++;
 891         }
 892
 893         /*
 894          * HDMI 12bpc affects the clocks, so it's only possible
 895          * when not cloning with other encoder types.
 896          */
 897         return count_hdmi > 0 && count_hdmi == count;
 898 }
 899
 900 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 901                                struct intel_crtc_config *pipe_config)
 902 {
 903         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 904         struct drm_device *dev = encoder->base.dev;
 905         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 906         int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
 907         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
 908         int desired_bpp;
 909
 910         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
 911
 912         if (intel_hdmi->color_range_auto) {
 913                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 914                 if (pipe_config->has_hdmi_sink &&
 915                     drm_match_cea_mode(adjusted_mode) > 1)
 916                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 917                 else
 918                         intel_hdmi->color_range = 0;
 919         }
 920
 921         if (intel_hdmi->color_range)
 922                 pipe_config->limited_color_range = true;
 923
 924         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 925                 pipe_config->has_pch_encoder = true;
 926
 927         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
 928                 pipe_config->has_audio = true;
 929
 930         /*
 931          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 932          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
 933          * outputs. We also need to check that the higher clock still fits
 934          * within limits.
 935          */
 936         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
 937             clock_12bpc <= portclock_limit &&
 938             hdmi_12bpc_possible(encoder->new_crtc)) {
 939                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
 940                 desired_bpp = 12*3;
 941
 942                 /* Need to adjust the port link by 1.5x for 12bpc. */
 943                 pipe_config->port_clock = clock_12bpc;
 944         } else {
 945                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
 946                 desired_bpp = 8*3;
 947         }
 948
 949         if (!pipe_config->bw_constrained) {
 950                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
 951                 pipe_config->pipe_bpp = desired_bpp;
 952         }
 953
 954         if (adjusted_mode->crtc_clock > portclock_limit) {
 955                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
 956                 return false;
 957         }
 958
 959         return true;
 960 }
 961
 962 static enum drm_connector_status
 963 intel_hdmi_detect(struct drm_connector *connector, bool force)
 964 {
 965         struct drm_device *dev = connector->dev;
 966         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 967         struct intel_digital_port *intel_dig_port =
 968                 hdmi_to_dig_port(intel_hdmi);
 969         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         struct edid *edid;
 972         enum intel_display_power_domain power_domain;
 973         enum drm_connector_status status = connector_status_disconnected;
 974
 975         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 976                       connector->base.id, connector->name);
 977
 978         power_domain = intel_display_port_power_domain(intel_encoder);
 979         intel_display_power_get(dev_priv, power_domain);
 980
 981         intel_hdmi->has_hdmi_sink = false;
 982         intel_hdmi->has_audio = false;
 983         intel_hdmi->rgb_quant_range_selectable = false;
 984         edid = drm_get_edid(connector,
 985                             intel_gmbus_get_adapter(dev_priv,
 986                                                     intel_hdmi->ddc_bus));
 987
 988         if (edid) {
 989                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 990                         status = connector_status_connected;
 991                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 992                                 intel_hdmi->has_hdmi_sink =
 993                                                 drm_detect_hdmi_monitor(edid);
 994                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 995                         intel_hdmi->rgb_quant_range_selectable =
 996                                 drm_rgb_quant_range_selectable(edid);
 997                 }
 998                 kfree(edid);
 999         }
1000
1001         if (status == connector_status_connected) {
1002                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1003                         intel_hdmi->has_audio =
1004                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
1005                 intel_encoder->type = INTEL_OUTPUT_HDMI;
1006         }
1007
1008         intel_display_power_put(dev_priv, power_domain);
1009
1010         return status;
1011 }
1012
1013 static int intel_hdmi_get_modes(struct drm_connector *connector)
1014 {
1015         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1016         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1017         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1018         enum intel_display_power_domain power_domain;
1019         int ret;
1020
1021         /* We should parse the EDID data and find out if it's an HDMI sink so
1022          * we can send audio to it.
1023          */
1024
1025         power_domain = intel_display_port_power_domain(intel_encoder);
1026         intel_display_power_get(dev_priv, power_domain);
1027
1028         ret = intel_ddc_get_modes(connector,
1029                                    intel_gmbus_get_adapter(dev_priv,
1030                                                            intel_hdmi->ddc_bus));
1031
1032         intel_display_power_put(dev_priv, power_domain);
1033
1034         return ret;
1035 }
1036
1037 static bool
1038 intel_hdmi_detect_audio(struct drm_connector *connector)
1039 {
1040         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1041         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1042         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1043         enum intel_display_power_domain power_domain;
1044         struct edid *edid;
1045         bool has_audio = false;
1046
1047         power_domain = intel_display_port_power_domain(intel_encoder);
1048         intel_display_power_get(dev_priv, power_domain);
1049
1050         edid = drm_get_edid(connector,
1051                             intel_gmbus_get_adapter(dev_priv,
1052                                                     intel_hdmi->ddc_bus));
1053         if (edid) {
1054                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1055                         has_audio = drm_detect_monitor_audio(edid);
1056                 kfree(edid);
1057         }
1058
1059         intel_display_power_put(dev_priv, power_domain);
1060
1061         return has_audio;
1062 }
1063
1064 static int
1065 intel_hdmi_set_property(struct drm_connector *connector,
1066                         struct drm_property *property,
1067                         uint64_t val)
1068 {
1069         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1070         struct intel_digital_port *intel_dig_port =
1071                 hdmi_to_dig_port(intel_hdmi);
1072         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1073         int ret;
1074
1075         ret = drm_object_property_set_value(&connector->base, property, val);
1076         if (ret)
1077                 return ret;
1078
1079         if (property == dev_priv->force_audio_property) {
1080                 enum hdmi_force_audio i = val;
1081                 bool has_audio;
1082
1083                 if (i == intel_hdmi->force_audio)
1084                         return 0;
1085
1086                 intel_hdmi->force_audio = i;
1087
1088                 if (i == HDMI_AUDIO_AUTO)
1089                         has_audio = intel_hdmi_detect_audio(connector);
1090                 else
1091                         has_audio = (i == HDMI_AUDIO_ON);
1092
1093                 if (i == HDMI_AUDIO_OFF_DVI)
1094                         intel_hdmi->has_hdmi_sink = 0;
1095
1096                 intel_hdmi->has_audio = has_audio;
1097                 goto done;
1098         }
1099
1100         if (property == dev_priv->broadcast_rgb_property) {
1101                 bool old_auto = intel_hdmi->color_range_auto;
1102                 uint32_t old_range = intel_hdmi->color_range;
1103
1104                 switch (val) {
1105                 case INTEL_BROADCAST_RGB_AUTO:
1106                         intel_hdmi->color_range_auto = true;
1107                         break;
1108                 case INTEL_BROADCAST_RGB_FULL:
1109                         intel_hdmi->color_range_auto = false;
1110                         intel_hdmi->color_range = 0;
1111                         break;
1112                 case INTEL_BROADCAST_RGB_LIMITED:
1113                         intel_hdmi->color_range_auto = false;
1114                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1115                         break;
1116                 default:
1117                         return -EINVAL;
1118                 }
1119
1120                 if (old_auto == intel_hdmi->color_range_auto &&
1121                     old_range == intel_hdmi->color_range)
1122                         return 0;
1123
1124                 goto done;
1125         }
1126
1127         return -EINVAL;
1128
1129 done:
1130         if (intel_dig_port->base.base.crtc)
1131                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1132
1133         return 0;
1134 }
1135
1136 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1137 {
1138         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1139         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1140         struct drm_display_mode *adjusted_mode =
1141                 &intel_crtc->config.adjusted_mode;
1142
1143         intel_hdmi_prepare(encoder);
1144
1145         intel_hdmi->set_infoframes(&encoder->base,
1146                                    intel_crtc->config.has_hdmi_sink,
1147                                    adjusted_mode);
1148 }
1149
1150 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1151 {
1152         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1153         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1154         struct drm_device *dev = encoder->base.dev;
1155         struct drm_i915_private *dev_priv = dev->dev_private;
1156         struct intel_crtc *intel_crtc =
1157                 to_intel_crtc(encoder->base.crtc);
1158         struct drm_display_mode *adjusted_mode =
1159                 &intel_crtc->config.adjusted_mode;
1160         enum dpio_channel port = vlv_dport_to_channel(dport);
1161         int pipe = intel_crtc->pipe;
1162         u32 val;
1163
1164         /* Enable clock channels for this port */
1165         mutex_lock(&dev_priv->dpio_lock);
1166         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1167         val = 0;
1168         if (pipe)
1169                 val |= (1<<21);
1170         else
1171                 val &= ~(1<<21);
1172         val |= 0x001000c4;
1173         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1174
1175         /* HDMI 1.0V-2dB */
1176         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1177         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1178         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1179         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1180         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1181         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1182         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1183         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1184
1185         /* Program lane clock */
1186         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1187         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1188         mutex_unlock(&dev_priv->dpio_lock);
1189
1190         intel_hdmi->set_infoframes(&encoder->base,
1191                                    intel_crtc->config.has_hdmi_sink,
1192                                    adjusted_mode);
1193
1194         intel_enable_hdmi(encoder);
1195
1196         vlv_wait_port_ready(dev_priv, dport);
1197 }
1198
1199 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1200 {
1201         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1202         struct drm_device *dev = encoder->base.dev;
1203         struct drm_i915_private *dev_priv = dev->dev_private;
1204         struct intel_crtc *intel_crtc =
1205                 to_intel_crtc(encoder->base.crtc);
1206         enum dpio_channel port = vlv_dport_to_channel(dport);
1207         int pipe = intel_crtc->pipe;
1208
1209         intel_hdmi_prepare(encoder);
1210
1211         /* Program Tx lane resets to default */
1212         mutex_lock(&dev_priv->dpio_lock);
1213         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1214                          DPIO_PCS_TX_LANE2_RESET |
1215                          DPIO_PCS_TX_LANE1_RESET);
1216         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1217                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1218                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1219                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1220                          DPIO_PCS_CLK_SOFT_RESET);
1221
1222         /* Fix up inter-pair skew failure */
1223         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1224         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1225         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1226
1227         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1228         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1229         mutex_unlock(&dev_priv->dpio_lock);
1230 }
1231
1232 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1233 {
1234         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1235         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1236         struct intel_crtc *intel_crtc =
1237                 to_intel_crtc(encoder->base.crtc);
1238         enum dpio_channel port = vlv_dport_to_channel(dport);
1239         int pipe = intel_crtc->pipe;
1240
1241         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1242         mutex_lock(&dev_priv->dpio_lock);
1243         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1244         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1245         mutex_unlock(&dev_priv->dpio_lock);
1246 }
1247
1248 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1249 {
1250         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1251         struct drm_device *dev = encoder->base.dev;
1252         struct drm_i915_private *dev_priv = dev->dev_private;
1253         struct intel_crtc *intel_crtc =
1254                 to_intel_crtc(encoder->base.crtc);
1255         enum dpio_channel ch = vlv_dport_to_channel(dport);
1256         enum pipe pipe = intel_crtc->pipe;
1257         u32 val;
1258
1259         mutex_lock(&dev_priv->dpio_lock);
1260
1261         /* Propagate soft reset to data lane reset */
1262         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1263         val |= CHV_PCS_REQ_SOFTRESET_EN;
1264         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1265
1266         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1267         val |= CHV_PCS_REQ_SOFTRESET_EN;
1268         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1269
1270         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1271         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1272         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1273
1274         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1275         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1276         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1277
1278         mutex_unlock(&dev_priv->dpio_lock);
1279 }
1280
1281 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1282 {
1283         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1284         struct drm_device *dev = encoder->base.dev;
1285         struct drm_i915_private *dev_priv = dev->dev_private;
1286         struct intel_crtc *intel_crtc =
1287                 to_intel_crtc(encoder->base.crtc);
1288         enum dpio_channel ch = vlv_dport_to_channel(dport);
1289         int pipe = intel_crtc->pipe;
1290         int data, i;
1291         u32 val;
1292
1293         mutex_lock(&dev_priv->dpio_lock);
1294
1295         /* Deassert soft data lane reset*/
1296         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1297         val |= CHV_PCS_REQ_SOFTRESET_EN;
1298         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1299
1300         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1301         val |= CHV_PCS_REQ_SOFTRESET_EN;
1302         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1303
1304         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1305         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1306         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1307
1308         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1309         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1310         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1311
1312         /* Program Tx latency optimal setting */
1313         for (i = 0; i < 4; i++) {
1314                 /* Set the latency optimal bit */
1315                 data = (i == 1) ? 0x0 : 0x6;
1316                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1317                                 data << DPIO_FRC_LATENCY_SHFIT);
1318
1319                 /* Set the upar bit */
1320                 data = (i == 1) ? 0x0 : 0x1;
1321                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1322                                 data << DPIO_UPAR_SHIFT);
1323         }
1324
1325         /* Data lane stagger programming */
1326         /* FIXME: Fix up value only after power analysis */
1327
1328         /* Clear calc init */
1329         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1330         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1331         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1332
1333         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1334         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1335         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1336
1337         /* FIXME: Program the support xxx V-dB */
1338         /* Use 800mV-0dB */
1339         for (i = 0; i < 4; i++) {
1340                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1341                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1342                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1343                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1344         }
1345
1346         for (i = 0; i < 4; i++) {
1347                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1348                 val &= ~DPIO_SWING_MARGIN_MASK;
1349                 val |= 102 << DPIO_SWING_MARGIN_SHIFT;
1350                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1351         }
1352
1353         /* Disable unique transition scale */
1354         for (i = 0; i < 4; i++) {
1355                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1356                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1357                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1358         }
1359
1360         /* Additional steps for 1200mV-0dB */
1361 #if 0
1362         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1363         if (ch)
1364                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1365         else
1366                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1367         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1368
1369         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1370                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1371                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1372 #endif
1373         /* Start swing calculation */
1374         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1375         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1376         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1377
1378         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1379         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1380         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1381
1382         /* LRC Bypass */
1383         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1384         val |= DPIO_LRC_BYPASS;
1385         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1386
1387         mutex_unlock(&dev_priv->dpio_lock);
1388
1389         intel_enable_hdmi(encoder);
1390
1391         vlv_wait_port_ready(dev_priv, dport);
1392 }
1393
1394 static void intel_hdmi_destroy(struct drm_connector *connector)
1395 {
1396         drm_connector_cleanup(connector);
1397         kfree(connector);
1398 }
1399
1400 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1401         .dpms = intel_connector_dpms,
1402         .detect = intel_hdmi_detect,
1403         .fill_modes = drm_helper_probe_single_connector_modes,
1404         .set_property = intel_hdmi_set_property,
1405         .destroy = intel_hdmi_destroy,
1406 };
1407
1408 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1409         .get_modes = intel_hdmi_get_modes,
1410         .mode_valid = intel_hdmi_mode_valid,
1411         .best_encoder = intel_best_encoder,
1412 };
1413
1414 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1415         .destroy = intel_encoder_destroy,
1416 };
1417
1418 static void
1419 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1420 {
1421         intel_attach_force_audio_property(connector);
1422         intel_attach_broadcast_rgb_property(connector);
1423         intel_hdmi->color_range_auto = true;
1424 }
1425
1426 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1427                                struct intel_connector *intel_connector)
1428 {
1429         struct drm_connector *connector = &intel_connector->base;
1430         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1431         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1432         struct drm_device *dev = intel_encoder->base.dev;
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         enum port port = intel_dig_port->port;
1435
1436         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1437                            DRM_MODE_CONNECTOR_HDMIA);
1438         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1439
1440         connector->interlace_allowed = 1;
1441         connector->doublescan_allowed = 0;
1442         connector->stereo_allowed = 1;
1443
1444         switch (port) {
1445         case PORT_B:
1446                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1447                 intel_encoder->hpd_pin = HPD_PORT_B;
1448                 break;
1449         case PORT_C:
1450                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1451                 intel_encoder->hpd_pin = HPD_PORT_C;
1452                 break;
1453         case PORT_D:
1454                 if (IS_CHERRYVIEW(dev))
1455                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1456                 else
1457                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1458                 intel_encoder->hpd_pin = HPD_PORT_D;
1459                 break;
1460         case PORT_A:
1461                 intel_encoder->hpd_pin = HPD_PORT_A;
1462                 /* Internal port only for eDP. */
1463         default:
1464                 BUG();
1465         }
1466
1467         if (IS_VALLEYVIEW(dev)) {
1468                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1469                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1470         } else if (!HAS_PCH_SPLIT(dev)) {
1471                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1472                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1473         } else if (HAS_DDI(dev)) {
1474                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1475                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1476         } else if (HAS_PCH_IBX(dev)) {
1477                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1478                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1479         } else {
1480                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1481                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1482         }
1483
1484         if (HAS_DDI(dev))
1485                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1486         else
1487                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1488         intel_connector->unregister = intel_connector_unregister;
1489
1490         intel_hdmi_add_properties(intel_hdmi, connector);
1491
1492         intel_connector_attach_encoder(intel_connector, intel_encoder);
1493         drm_connector_register(connector);
1494
1495         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1496          * 0xd.  Failure to do so will result in spurious interrupts being
1497          * generated on the port when a cable is not attached.
1498          */
1499         if (IS_G4X(dev) && !IS_GM45(dev)) {
1500                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1501                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1502         }
1503 }
1504
1505 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1506 {
1507         struct intel_digital_port *intel_dig_port;
1508         struct intel_encoder *intel_encoder;
1509         struct intel_connector *intel_connector;
1510
1511         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1512         if (!intel_dig_port)
1513                 return;
1514
1515         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1516         if (!intel_connector) {
1517                 kfree(intel_dig_port);
1518                 return;
1519         }
1520
1521         intel_encoder = &intel_dig_port->base;
1522
1523         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1524                          DRM_MODE_ENCODER_TMDS);
1525
1526         intel_encoder->compute_config = intel_hdmi_compute_config;
1527         intel_encoder->disable = intel_disable_hdmi;
1528         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1529         intel_encoder->get_config = intel_hdmi_get_config;
1530         if (IS_CHERRYVIEW(dev)) {
1531                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1532                 intel_encoder->enable = vlv_enable_hdmi;
1533                 intel_encoder->post_disable = chv_hdmi_post_disable;
1534         } else if (IS_VALLEYVIEW(dev)) {
1535                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1536                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1537                 intel_encoder->enable = vlv_enable_hdmi;
1538                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1539         } else {
1540                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1541                 intel_encoder->enable = intel_enable_hdmi;
1542         }
1543
1544         intel_encoder->type = INTEL_OUTPUT_HDMI;
1545         if (IS_CHERRYVIEW(dev)) {
1546                 if (port == PORT_D)
1547                         intel_encoder->crtc_mask = 1 << 2;
1548                 else
1549                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1550         } else {
1551                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1552         }
1553         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1554         /*
1555          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1556          * to work on real hardware. And since g4x can send infoframes to
1557          * only one port anyway, nothing is lost by allowing it.
1558          */
1559         if (IS_G4X(dev))
1560                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1561
1562         intel_dig_port->port = port;
1563         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1564         intel_dig_port->dp.output_reg = 0;
1565
1566         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1567 }