2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
41 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
45 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
47 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
48 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
49 uint32_t enabled_bits
;
51 enabled_bits
= HAS_DDI(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
53 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
54 "HDMI port enabled, expecting disabled\n");
57 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
59 struct intel_digital_port
*intel_dig_port
=
60 container_of(encoder
, struct intel_digital_port
, base
.base
);
61 return &intel_dig_port
->hdmi
;
64 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
66 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
69 void intel_dip_infoframe_csum(struct dip_infoframe
*frame
)
71 uint8_t *data
= (uint8_t *)frame
;
78 for (i
= 0; i
< frame
->len
+ DIP_HEADER_SIZE
; i
++)
81 frame
->checksum
= 0x100 - sum
;
84 static u32
g4x_infoframe_index(struct dip_infoframe
*frame
)
86 switch (frame
->type
) {
88 return VIDEO_DIP_SELECT_AVI
;
90 return VIDEO_DIP_SELECT_SPD
;
92 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
97 static u32
g4x_infoframe_enable(struct dip_infoframe
*frame
)
99 switch (frame
->type
) {
101 return VIDEO_DIP_ENABLE_AVI
;
103 return VIDEO_DIP_ENABLE_SPD
;
105 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
110 static u32
hsw_infoframe_enable(struct dip_infoframe
*frame
)
112 switch (frame
->type
) {
114 return VIDEO_DIP_ENABLE_AVI_HSW
;
116 return VIDEO_DIP_ENABLE_SPD_HSW
;
118 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
123 static u32
hsw_infoframe_data_reg(struct dip_infoframe
*frame
,
124 enum transcoder cpu_transcoder
)
126 switch (frame
->type
) {
128 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
);
130 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
);
132 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
137 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
138 struct dip_infoframe
*frame
)
140 uint32_t *data
= (uint32_t *)frame
;
141 struct drm_device
*dev
= encoder
->dev
;
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 u32 val
= I915_READ(VIDEO_DIP_CTL
);
144 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
146 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
148 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
149 val
|= g4x_infoframe_index(frame
);
151 val
&= ~g4x_infoframe_enable(frame
);
153 I915_WRITE(VIDEO_DIP_CTL
, val
);
156 for (i
= 0; i
< len
; i
+= 4) {
157 I915_WRITE(VIDEO_DIP_DATA
, *data
);
160 /* Write every possible data byte to force correct ECC calculation. */
161 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
162 I915_WRITE(VIDEO_DIP_DATA
, 0);
165 val
|= g4x_infoframe_enable(frame
);
166 val
&= ~VIDEO_DIP_FREQ_MASK
;
167 val
|= VIDEO_DIP_FREQ_VSYNC
;
169 I915_WRITE(VIDEO_DIP_CTL
, val
);
170 POSTING_READ(VIDEO_DIP_CTL
);
173 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
174 struct dip_infoframe
*frame
)
176 uint32_t *data
= (uint32_t *)frame
;
177 struct drm_device
*dev
= encoder
->dev
;
178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
179 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
180 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
181 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
182 u32 val
= I915_READ(reg
);
184 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
186 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
187 val
|= g4x_infoframe_index(frame
);
189 val
&= ~g4x_infoframe_enable(frame
);
191 I915_WRITE(reg
, val
);
194 for (i
= 0; i
< len
; i
+= 4) {
195 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
198 /* Write every possible data byte to force correct ECC calculation. */
199 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
200 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
203 val
|= g4x_infoframe_enable(frame
);
204 val
&= ~VIDEO_DIP_FREQ_MASK
;
205 val
|= VIDEO_DIP_FREQ_VSYNC
;
207 I915_WRITE(reg
, val
);
211 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
212 struct dip_infoframe
*frame
)
214 uint32_t *data
= (uint32_t *)frame
;
215 struct drm_device
*dev
= encoder
->dev
;
216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
217 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
218 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
219 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
220 u32 val
= I915_READ(reg
);
222 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
224 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
225 val
|= g4x_infoframe_index(frame
);
227 /* The DIP control register spec says that we need to update the AVI
228 * infoframe without clearing its enable bit */
229 if (frame
->type
!= DIP_TYPE_AVI
)
230 val
&= ~g4x_infoframe_enable(frame
);
232 I915_WRITE(reg
, val
);
235 for (i
= 0; i
< len
; i
+= 4) {
236 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
239 /* Write every possible data byte to force correct ECC calculation. */
240 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
241 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
244 val
|= g4x_infoframe_enable(frame
);
245 val
&= ~VIDEO_DIP_FREQ_MASK
;
246 val
|= VIDEO_DIP_FREQ_VSYNC
;
248 I915_WRITE(reg
, val
);
252 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
253 struct dip_infoframe
*frame
)
255 uint32_t *data
= (uint32_t *)frame
;
256 struct drm_device
*dev
= encoder
->dev
;
257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
258 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
259 int reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
260 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
261 u32 val
= I915_READ(reg
);
263 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
265 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
266 val
|= g4x_infoframe_index(frame
);
268 val
&= ~g4x_infoframe_enable(frame
);
270 I915_WRITE(reg
, val
);
273 for (i
= 0; i
< len
; i
+= 4) {
274 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
279 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
282 val
|= g4x_infoframe_enable(frame
);
283 val
&= ~VIDEO_DIP_FREQ_MASK
;
284 val
|= VIDEO_DIP_FREQ_VSYNC
;
286 I915_WRITE(reg
, val
);
290 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
291 struct dip_infoframe
*frame
)
293 uint32_t *data
= (uint32_t *)frame
;
294 struct drm_device
*dev
= encoder
->dev
;
295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
296 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
297 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
298 u32 data_reg
= hsw_infoframe_data_reg(frame
, intel_crtc
->config
.cpu_transcoder
);
299 unsigned int i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
300 u32 val
= I915_READ(ctl_reg
);
305 val
&= ~hsw_infoframe_enable(frame
);
306 I915_WRITE(ctl_reg
, val
);
309 for (i
= 0; i
< len
; i
+= 4) {
310 I915_WRITE(data_reg
+ i
, *data
);
313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
315 I915_WRITE(data_reg
+ i
, 0);
318 val
|= hsw_infoframe_enable(frame
);
319 I915_WRITE(ctl_reg
, val
);
320 POSTING_READ(ctl_reg
);
323 static void intel_set_infoframe(struct drm_encoder
*encoder
,
324 struct dip_infoframe
*frame
)
326 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
328 intel_dip_infoframe_csum(frame
);
329 intel_hdmi
->write_infoframe(encoder
, frame
);
332 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
333 struct drm_display_mode
*adjusted_mode
)
335 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
336 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
337 struct dip_infoframe avi_if
= {
338 .type
= DIP_TYPE_AVI
,
339 .ver
= DIP_VERSION_AVI
,
343 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
344 avi_if
.body
.avi
.YQ_CN_PR
|= DIP_AVI_PR_2
;
346 if (intel_hdmi
->rgb_quant_range_selectable
) {
347 if (intel_crtc
->config
.limited_color_range
)
348 avi_if
.body
.avi
.ITC_EC_Q_SC
|= DIP_AVI_RGB_QUANT_RANGE_LIMITED
;
350 avi_if
.body
.avi
.ITC_EC_Q_SC
|= DIP_AVI_RGB_QUANT_RANGE_FULL
;
353 avi_if
.body
.avi
.VIC
= drm_match_cea_mode(adjusted_mode
);
355 intel_set_infoframe(encoder
, &avi_if
);
358 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
360 struct dip_infoframe spd_if
;
362 memset(&spd_if
, 0, sizeof(spd_if
));
363 spd_if
.type
= DIP_TYPE_SPD
;
364 spd_if
.ver
= DIP_VERSION_SPD
;
365 spd_if
.len
= DIP_LEN_SPD
;
366 strcpy(spd_if
.body
.spd
.vn
, "Intel");
367 strcpy(spd_if
.body
.spd
.pd
, "Integrated gfx");
368 spd_if
.body
.spd
.sdi
= DIP_SPD_PC
;
370 intel_set_infoframe(encoder
, &spd_if
);
373 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
374 struct drm_display_mode
*adjusted_mode
)
376 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
377 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
378 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
379 u32 reg
= VIDEO_DIP_CTL
;
380 u32 val
= I915_READ(reg
);
383 assert_hdmi_port_disabled(intel_hdmi
);
385 /* If the registers were not initialized yet, they might be zeroes,
386 * which means we're selecting the AVI DIP and we're setting its
387 * frequency to once. This seems to really confuse the HW and make
388 * things stop working (the register spec says the AVI always needs to
389 * be sent every VSync). So here we avoid writing to the register more
390 * than we need and also explicitly select the AVI DIP and explicitly
391 * set its frequency to every VSync. Avoiding to write it twice seems to
392 * be enough to solve the problem, but being defensive shouldn't hurt us
394 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
396 if (!intel_hdmi
->has_hdmi_sink
) {
397 if (!(val
& VIDEO_DIP_ENABLE
))
399 val
&= ~VIDEO_DIP_ENABLE
;
400 I915_WRITE(reg
, val
);
405 switch (intel_dig_port
->port
) {
407 port
= VIDEO_DIP_PORT_B
;
410 port
= VIDEO_DIP_PORT_C
;
417 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
418 if (val
& VIDEO_DIP_ENABLE
) {
419 val
&= ~VIDEO_DIP_ENABLE
;
420 I915_WRITE(reg
, val
);
423 val
&= ~VIDEO_DIP_PORT_MASK
;
427 val
|= VIDEO_DIP_ENABLE
;
428 val
&= ~VIDEO_DIP_ENABLE_VENDOR
;
430 I915_WRITE(reg
, val
);
433 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
434 intel_hdmi_set_spd_infoframe(encoder
);
437 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
438 struct drm_display_mode
*adjusted_mode
)
440 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
441 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
442 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
443 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
444 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
445 u32 val
= I915_READ(reg
);
448 assert_hdmi_port_disabled(intel_hdmi
);
450 /* See the big comment in g4x_set_infoframes() */
451 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
453 if (!intel_hdmi
->has_hdmi_sink
) {
454 if (!(val
& VIDEO_DIP_ENABLE
))
456 val
&= ~VIDEO_DIP_ENABLE
;
457 I915_WRITE(reg
, val
);
462 switch (intel_dig_port
->port
) {
464 port
= VIDEO_DIP_PORT_B
;
467 port
= VIDEO_DIP_PORT_C
;
470 port
= VIDEO_DIP_PORT_D
;
477 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
478 if (val
& VIDEO_DIP_ENABLE
) {
479 val
&= ~VIDEO_DIP_ENABLE
;
480 I915_WRITE(reg
, val
);
483 val
&= ~VIDEO_DIP_PORT_MASK
;
487 val
|= VIDEO_DIP_ENABLE
;
488 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
489 VIDEO_DIP_ENABLE_GCP
);
491 I915_WRITE(reg
, val
);
494 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
495 intel_hdmi_set_spd_infoframe(encoder
);
498 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
499 struct drm_display_mode
*adjusted_mode
)
501 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
502 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
503 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
504 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
505 u32 val
= I915_READ(reg
);
507 assert_hdmi_port_disabled(intel_hdmi
);
509 /* See the big comment in g4x_set_infoframes() */
510 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
512 if (!intel_hdmi
->has_hdmi_sink
) {
513 if (!(val
& VIDEO_DIP_ENABLE
))
515 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
);
516 I915_WRITE(reg
, val
);
521 /* Set both together, unset both together: see the spec. */
522 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
523 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
524 VIDEO_DIP_ENABLE_GCP
);
526 I915_WRITE(reg
, val
);
529 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
530 intel_hdmi_set_spd_infoframe(encoder
);
533 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
534 struct drm_display_mode
*adjusted_mode
)
536 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
537 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
538 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
539 u32 reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
540 u32 val
= I915_READ(reg
);
542 assert_hdmi_port_disabled(intel_hdmi
);
544 /* See the big comment in g4x_set_infoframes() */
545 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
547 if (!intel_hdmi
->has_hdmi_sink
) {
548 if (!(val
& VIDEO_DIP_ENABLE
))
550 val
&= ~VIDEO_DIP_ENABLE
;
551 I915_WRITE(reg
, val
);
556 val
|= VIDEO_DIP_ENABLE
;
557 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
558 VIDEO_DIP_ENABLE_GCP
);
560 I915_WRITE(reg
, val
);
563 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
564 intel_hdmi_set_spd_infoframe(encoder
);
567 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
568 struct drm_display_mode
*adjusted_mode
)
570 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
571 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
572 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
573 u32 reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
574 u32 val
= I915_READ(reg
);
576 assert_hdmi_port_disabled(intel_hdmi
);
578 if (!intel_hdmi
->has_hdmi_sink
) {
584 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_GCP_HSW
|
585 VIDEO_DIP_ENABLE_VS_HSW
| VIDEO_DIP_ENABLE_GMP_HSW
);
587 I915_WRITE(reg
, val
);
590 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
591 intel_hdmi_set_spd_infoframe(encoder
);
594 static void intel_hdmi_mode_set(struct drm_encoder
*encoder
,
595 struct drm_display_mode
*mode
,
596 struct drm_display_mode
*adjusted_mode
)
598 struct drm_device
*dev
= encoder
->dev
;
599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
601 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
604 hdmi_val
= SDVO_ENCODING_HDMI
;
605 if (!HAS_PCH_SPLIT(dev
))
606 hdmi_val
|= intel_hdmi
->color_range
;
607 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
608 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
609 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
610 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
612 if (intel_crtc
->config
.pipe_bpp
> 24)
613 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
615 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
617 /* Required on CPT */
618 if (intel_hdmi
->has_hdmi_sink
&& HAS_PCH_CPT(dev
))
619 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
621 if (intel_hdmi
->has_audio
) {
622 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
623 pipe_name(intel_crtc
->pipe
));
624 hdmi_val
|= SDVO_AUDIO_ENABLE
;
625 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
626 intel_write_eld(encoder
, adjusted_mode
);
629 if (HAS_PCH_CPT(dev
))
630 hdmi_val
|= SDVO_PIPE_SEL_CPT(intel_crtc
->pipe
);
632 hdmi_val
|= SDVO_PIPE_SEL(intel_crtc
->pipe
);
634 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
635 POSTING_READ(intel_hdmi
->hdmi_reg
);
637 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
640 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
643 struct drm_device
*dev
= encoder
->base
.dev
;
644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
645 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
648 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
650 if (!(tmp
& SDVO_ENABLE
))
653 if (HAS_PCH_CPT(dev
))
654 *pipe
= PORT_TO_PIPE_CPT(tmp
);
656 *pipe
= PORT_TO_PIPE(tmp
);
661 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
662 struct intel_crtc_config
*pipe_config
)
664 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
665 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
668 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
670 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
671 flags
|= DRM_MODE_FLAG_PHSYNC
;
673 flags
|= DRM_MODE_FLAG_NHSYNC
;
675 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
676 flags
|= DRM_MODE_FLAG_PVSYNC
;
678 flags
|= DRM_MODE_FLAG_NVSYNC
;
680 pipe_config
->adjusted_mode
.flags
|= flags
;
683 static void intel_enable_hdmi(struct intel_encoder
*encoder
)
685 struct drm_device
*dev
= encoder
->base
.dev
;
686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
687 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
688 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
690 u32 enable_bits
= SDVO_ENABLE
;
692 if (intel_hdmi
->has_audio
)
693 enable_bits
|= SDVO_AUDIO_ENABLE
;
695 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
697 /* HW workaround for IBX, we need to move the port to transcoder A
698 * before disabling it, so restore the transcoder select bit here. */
699 if (HAS_PCH_IBX(dev
))
700 enable_bits
|= SDVO_PIPE_SEL(intel_crtc
->pipe
);
702 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
703 * we do this anyway which shows more stable in testing.
705 if (HAS_PCH_SPLIT(dev
)) {
706 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
707 POSTING_READ(intel_hdmi
->hdmi_reg
);
712 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
713 POSTING_READ(intel_hdmi
->hdmi_reg
);
715 /* HW workaround, need to write this twice for issue that may result
716 * in first write getting masked.
718 if (HAS_PCH_SPLIT(dev
)) {
719 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
720 POSTING_READ(intel_hdmi
->hdmi_reg
);
723 if (IS_VALLEYVIEW(dev
)) {
724 struct intel_digital_port
*dport
=
725 enc_to_dig_port(&encoder
->base
);
726 int channel
= vlv_dport_to_channel(dport
);
728 vlv_wait_port_ready(dev_priv
, channel
);
732 static void intel_disable_hdmi(struct intel_encoder
*encoder
)
734 struct drm_device
*dev
= encoder
->base
.dev
;
735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
736 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
738 u32 enable_bits
= SDVO_ENABLE
| SDVO_AUDIO_ENABLE
;
740 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
742 /* HW workaround for IBX, we need to move the port to transcoder A
743 * before disabling it. */
744 if (HAS_PCH_IBX(dev
)) {
745 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
746 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
748 if (temp
& SDVO_PIPE_B_SELECT
) {
749 temp
&= ~SDVO_PIPE_B_SELECT
;
750 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
751 POSTING_READ(intel_hdmi
->hdmi_reg
);
753 /* Again we need to write this twice. */
754 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
755 POSTING_READ(intel_hdmi
->hdmi_reg
);
757 /* Transcoder selection bits only update
758 * effectively on vblank. */
760 intel_wait_for_vblank(dev
, pipe
);
766 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
767 * we do this anyway which shows more stable in testing.
769 if (HAS_PCH_SPLIT(dev
)) {
770 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
771 POSTING_READ(intel_hdmi
->hdmi_reg
);
774 temp
&= ~enable_bits
;
776 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
777 POSTING_READ(intel_hdmi
->hdmi_reg
);
779 /* HW workaround, need to write this twice for issue that may result
780 * in first write getting masked.
782 if (HAS_PCH_SPLIT(dev
)) {
783 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
784 POSTING_READ(intel_hdmi
->hdmi_reg
);
788 static int hdmi_portclock_limit(struct intel_hdmi
*hdmi
)
790 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
794 else if (IS_HASWELL(dev
))
800 static int intel_hdmi_mode_valid(struct drm_connector
*connector
,
801 struct drm_display_mode
*mode
)
803 if (mode
->clock
> hdmi_portclock_limit(intel_attached_hdmi(connector
)))
804 return MODE_CLOCK_HIGH
;
805 if (mode
->clock
< 20000)
806 return MODE_CLOCK_LOW
;
808 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
809 return MODE_NO_DBLESCAN
;
814 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
815 struct intel_crtc_config
*pipe_config
)
817 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
818 struct drm_device
*dev
= encoder
->base
.dev
;
819 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
820 int clock_12bpc
= pipe_config
->requested_mode
.clock
* 3 / 2;
821 int portclock_limit
= hdmi_portclock_limit(intel_hdmi
);
824 if (intel_hdmi
->color_range_auto
) {
825 /* See CEA-861-E - 5.1 Default Encoding Parameters */
826 if (intel_hdmi
->has_hdmi_sink
&&
827 drm_match_cea_mode(adjusted_mode
) > 1)
828 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
830 intel_hdmi
->color_range
= 0;
833 if (intel_hdmi
->color_range
)
834 pipe_config
->limited_color_range
= true;
836 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
))
837 pipe_config
->has_pch_encoder
= true;
840 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
841 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
842 * outputs. We also need to check that the higher clock still fits
845 if (pipe_config
->pipe_bpp
> 8*3 && clock_12bpc
<= portclock_limit
846 && HAS_PCH_SPLIT(dev
)) {
847 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
850 /* Need to adjust the port link by 1.5x for 12bpc. */
851 pipe_config
->port_clock
= clock_12bpc
;
853 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
857 if (!pipe_config
->bw_constrained
) {
858 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp
);
859 pipe_config
->pipe_bpp
= desired_bpp
;
862 if (adjusted_mode
->clock
> portclock_limit
) {
863 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
870 static enum drm_connector_status
871 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
873 struct drm_device
*dev
= connector
->dev
;
874 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
875 struct intel_digital_port
*intel_dig_port
=
876 hdmi_to_dig_port(intel_hdmi
);
877 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
880 enum drm_connector_status status
= connector_status_disconnected
;
882 intel_hdmi
->has_hdmi_sink
= false;
883 intel_hdmi
->has_audio
= false;
884 intel_hdmi
->rgb_quant_range_selectable
= false;
885 edid
= drm_get_edid(connector
,
886 intel_gmbus_get_adapter(dev_priv
,
887 intel_hdmi
->ddc_bus
));
890 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
891 status
= connector_status_connected
;
892 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
893 intel_hdmi
->has_hdmi_sink
=
894 drm_detect_hdmi_monitor(edid
);
895 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
896 intel_hdmi
->rgb_quant_range_selectable
=
897 drm_rgb_quant_range_selectable(edid
);
902 if (status
== connector_status_connected
) {
903 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
904 intel_hdmi
->has_audio
=
905 (intel_hdmi
->force_audio
== HDMI_AUDIO_ON
);
906 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
912 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
914 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
915 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
917 /* We should parse the EDID data and find out if it's an HDMI sink so
918 * we can send audio to it.
921 return intel_ddc_get_modes(connector
,
922 intel_gmbus_get_adapter(dev_priv
,
923 intel_hdmi
->ddc_bus
));
927 intel_hdmi_detect_audio(struct drm_connector
*connector
)
929 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
930 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
932 bool has_audio
= false;
934 edid
= drm_get_edid(connector
,
935 intel_gmbus_get_adapter(dev_priv
,
936 intel_hdmi
->ddc_bus
));
938 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
)
939 has_audio
= drm_detect_monitor_audio(edid
);
947 intel_hdmi_set_property(struct drm_connector
*connector
,
948 struct drm_property
*property
,
951 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
952 struct intel_digital_port
*intel_dig_port
=
953 hdmi_to_dig_port(intel_hdmi
);
954 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
957 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
961 if (property
== dev_priv
->force_audio_property
) {
962 enum hdmi_force_audio i
= val
;
965 if (i
== intel_hdmi
->force_audio
)
968 intel_hdmi
->force_audio
= i
;
970 if (i
== HDMI_AUDIO_AUTO
)
971 has_audio
= intel_hdmi_detect_audio(connector
);
973 has_audio
= (i
== HDMI_AUDIO_ON
);
975 if (i
== HDMI_AUDIO_OFF_DVI
)
976 intel_hdmi
->has_hdmi_sink
= 0;
978 intel_hdmi
->has_audio
= has_audio
;
982 if (property
== dev_priv
->broadcast_rgb_property
) {
983 bool old_auto
= intel_hdmi
->color_range_auto
;
984 uint32_t old_range
= intel_hdmi
->color_range
;
987 case INTEL_BROADCAST_RGB_AUTO
:
988 intel_hdmi
->color_range_auto
= true;
990 case INTEL_BROADCAST_RGB_FULL
:
991 intel_hdmi
->color_range_auto
= false;
992 intel_hdmi
->color_range
= 0;
994 case INTEL_BROADCAST_RGB_LIMITED
:
995 intel_hdmi
->color_range_auto
= false;
996 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
1002 if (old_auto
== intel_hdmi
->color_range_auto
&&
1003 old_range
== intel_hdmi
->color_range
)
1012 if (intel_dig_port
->base
.base
.crtc
)
1013 intel_crtc_restore_mode(intel_dig_port
->base
.base
.crtc
);
1018 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
)
1020 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1021 struct drm_device
*dev
= encoder
->base
.dev
;
1022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1023 struct intel_crtc
*intel_crtc
=
1024 to_intel_crtc(encoder
->base
.crtc
);
1025 int port
= vlv_dport_to_channel(dport
);
1026 int pipe
= intel_crtc
->pipe
;
1029 if (!IS_VALLEYVIEW(dev
))
1032 /* Enable clock channels for this port */
1033 val
= vlv_dpio_read(dev_priv
, DPIO_DATA_LANE_A(port
));
1040 vlv_dpio_write(dev_priv
, DPIO_DATA_CHANNEL(port
), val
);
1043 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
), 0);
1044 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL4(port
),
1046 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL2(port
),
1048 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL3(port
),
1050 vlv_dpio_write(dev_priv
, DPIO_TX3_SWING_CTL4(port
),
1052 vlv_dpio_write(dev_priv
, DPIO_PCS_STAGGER0(port
), 0x00030000);
1053 vlv_dpio_write(dev_priv
, DPIO_PCS_CTL_OVER1(port
),
1055 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
),
1056 DPIO_TX_OCALINIT_EN
);
1058 /* Program lane clock */
1059 vlv_dpio_write(dev_priv
, DPIO_PCS_CLOCKBUF0(port
),
1061 vlv_dpio_write(dev_priv
, DPIO_PCS_CLOCKBUF8(port
),
1065 static void intel_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1067 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1068 struct drm_device
*dev
= encoder
->base
.dev
;
1069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1070 int port
= vlv_dport_to_channel(dport
);
1072 if (!IS_VALLEYVIEW(dev
))
1075 /* Program Tx lane resets to default */
1076 vlv_dpio_write(dev_priv
, DPIO_PCS_TX(port
),
1077 DPIO_PCS_TX_LANE2_RESET
|
1078 DPIO_PCS_TX_LANE1_RESET
);
1079 vlv_dpio_write(dev_priv
, DPIO_PCS_CLK(port
),
1080 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1081 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1082 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1083 DPIO_PCS_CLK_SOFT_RESET
);
1085 /* Fix up inter-pair skew failure */
1086 vlv_dpio_write(dev_priv
, DPIO_PCS_STAGGER1(port
), 0x00750f00);
1087 vlv_dpio_write(dev_priv
, DPIO_TX_CTL(port
), 0x00001500);
1088 vlv_dpio_write(dev_priv
, DPIO_TX_LANE(port
), 0x40400000);
1090 vlv_dpio_write(dev_priv
, DPIO_PCS_CTL_OVER1(port
),
1092 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
),
1093 DPIO_TX_OCALINIT_EN
);
1096 static void intel_hdmi_post_disable(struct intel_encoder
*encoder
)
1098 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1099 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1100 int port
= vlv_dport_to_channel(dport
);
1102 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1103 mutex_lock(&dev_priv
->dpio_lock
);
1104 vlv_dpio_write(dev_priv
, DPIO_PCS_TX(port
), 0x00000000);
1105 vlv_dpio_write(dev_priv
, DPIO_PCS_CLK(port
), 0x00e00060);
1106 mutex_unlock(&dev_priv
->dpio_lock
);
1109 static void intel_hdmi_destroy(struct drm_connector
*connector
)
1111 drm_sysfs_connector_remove(connector
);
1112 drm_connector_cleanup(connector
);
1116 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs
= {
1117 .mode_set
= intel_hdmi_mode_set
,
1120 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
1121 .dpms
= intel_connector_dpms
,
1122 .detect
= intel_hdmi_detect
,
1123 .fill_modes
= drm_helper_probe_single_connector_modes
,
1124 .set_property
= intel_hdmi_set_property
,
1125 .destroy
= intel_hdmi_destroy
,
1128 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
1129 .get_modes
= intel_hdmi_get_modes
,
1130 .mode_valid
= intel_hdmi_mode_valid
,
1131 .best_encoder
= intel_best_encoder
,
1134 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
1135 .destroy
= intel_encoder_destroy
,
1139 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
1141 intel_attach_force_audio_property(connector
);
1142 intel_attach_broadcast_rgb_property(connector
);
1143 intel_hdmi
->color_range_auto
= true;
1146 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1147 struct intel_connector
*intel_connector
)
1149 struct drm_connector
*connector
= &intel_connector
->base
;
1150 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
1151 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1152 struct drm_device
*dev
= intel_encoder
->base
.dev
;
1153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1154 enum port port
= intel_dig_port
->port
;
1156 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
1157 DRM_MODE_CONNECTOR_HDMIA
);
1158 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
1160 connector
->interlace_allowed
= 1;
1161 connector
->doublescan_allowed
= 0;
1165 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
1166 intel_encoder
->hpd_pin
= HPD_PORT_B
;
1169 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
1170 intel_encoder
->hpd_pin
= HPD_PORT_C
;
1173 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
1174 intel_encoder
->hpd_pin
= HPD_PORT_D
;
1177 intel_encoder
->hpd_pin
= HPD_PORT_A
;
1178 /* Internal port only for eDP. */
1183 if (IS_VALLEYVIEW(dev
)) {
1184 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
1185 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
1186 } else if (!HAS_PCH_SPLIT(dev
)) {
1187 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
1188 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
1189 } else if (HAS_DDI(dev
)) {
1190 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
1191 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
1192 } else if (HAS_PCH_IBX(dev
)) {
1193 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
1194 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
1196 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
1197 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
1201 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
1203 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1205 intel_hdmi_add_properties(intel_hdmi
, connector
);
1207 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1208 drm_sysfs_connector_add(connector
);
1210 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1211 * 0xd. Failure to do so will result in spurious interrupts being
1212 * generated on the port when a cable is not attached.
1214 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1215 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1216 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
1220 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
)
1222 struct intel_digital_port
*intel_dig_port
;
1223 struct intel_encoder
*intel_encoder
;
1224 struct drm_encoder
*encoder
;
1225 struct intel_connector
*intel_connector
;
1227 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1228 if (!intel_dig_port
)
1231 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1232 if (!intel_connector
) {
1233 kfree(intel_dig_port
);
1237 intel_encoder
= &intel_dig_port
->base
;
1238 encoder
= &intel_encoder
->base
;
1240 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
1241 DRM_MODE_ENCODER_TMDS
);
1242 drm_encoder_helper_add(&intel_encoder
->base
, &intel_hdmi_helper_funcs
);
1244 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
1245 intel_encoder
->enable
= intel_enable_hdmi
;
1246 intel_encoder
->disable
= intel_disable_hdmi
;
1247 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
1248 intel_encoder
->get_config
= intel_hdmi_get_config
;
1249 if (IS_VALLEYVIEW(dev
)) {
1250 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
1251 intel_encoder
->pre_pll_enable
= intel_hdmi_pre_pll_enable
;
1252 intel_encoder
->post_disable
= intel_hdmi_post_disable
;
1255 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
1256 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1257 intel_encoder
->cloneable
= false;
1259 intel_dig_port
->port
= port
;
1260 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
1261 intel_dig_port
->dp
.output_reg
= 0;
1263 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);