drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_crtc.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 struct intel_hdmi {
  41         struct intel_encoder base;
  42         u32 sdvox_reg;
  43         int ddc_bus;
  44         uint32_t color_range;
  45         bool has_hdmi_sink;
  46         bool has_audio;
  47         enum hdmi_force_audio force_audio;
  48         void (*write_infoframe)(struct drm_encoder *encoder,
  49                                 struct dip_infoframe *frame);
  50 };
  51
  52 static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  53 {
  54         return container_of(encoder, struct intel_hdmi, base.base);
  55 }
  56
  57 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  58 {
  59         return container_of(intel_attached_encoder(connector),
  60                             struct intel_hdmi, base);
  61 }
  62
  63 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  64 {
  65         uint8_t *data = (uint8_t *)frame;
  66         uint8_t sum = 0;
  67         unsigned i;
  68
  69         frame->checksum = 0;
  70         frame->ecc = 0;
  71
  72         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  73                 sum += data[i];
  74
  75         frame->checksum = 0x100 - sum;
  76 }
  77
  78 static u32 intel_infoframe_index(struct dip_infoframe *frame)
  79 {
  80         u32 flags = 0;
  81
  82         switch (frame->type) {
  83         case DIP_TYPE_AVI:
  84                 flags |= VIDEO_DIP_SELECT_AVI;
  85                 break;
  86         case DIP_TYPE_SPD:
  87                 flags |= VIDEO_DIP_SELECT_SPD;
  88                 break;
  89         default:
  90                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  91                 break;
  92         }
  93
  94         return flags;
  95 }
  96
  97 static u32 intel_infoframe_enable(struct dip_infoframe *frame)
  98 {
  99         u32 flags = 0;
 100
 101         switch (frame->type) {
 102         case DIP_TYPE_AVI:
 103                 flags |= VIDEO_DIP_ENABLE_AVI;
 104                 break;
 105         case DIP_TYPE_SPD:
 106                 flags |= VIDEO_DIP_ENABLE_SPD;
 107                 break;
 108         default:
 109                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 110                 break;
 111         }
 112
 113         return flags;
 114 }
 115
 116 static u32 intel_infoframe_frequency(struct dip_infoframe *frame)
 117 {
 118         u32 flags = 0;
 119
 120         switch (frame->type) {
 121         case DIP_TYPE_AVI:
 122         case DIP_TYPE_SPD:
 123                 flags |= VIDEO_DIP_FREQ_VSYNC;
 124                 break;
 125         default:
 126                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 127                 break;
 128         }
 129
 130         return flags;
 131 }
 132
 133 static void i9xx_write_infoframe(struct drm_encoder *encoder,
 134                                  struct dip_infoframe *frame)
 135 {
 136         uint32_t *data = (uint32_t *)frame;
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 140         u32 val = I915_READ(VIDEO_DIP_CTL);
 141         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 142
 143
 144         /* XXX first guess at handling video port, is this corrent? */
 145         val &= ~VIDEO_DIP_PORT_MASK;
 146         if (intel_hdmi->sdvox_reg == SDVOB)
 147                 val |= VIDEO_DIP_PORT_B;
 148         else if (intel_hdmi->sdvox_reg == SDVOC)
 149                 val |= VIDEO_DIP_PORT_C;
 150         else
 151                 return;
 152
 153         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 154         val |= intel_infoframe_index(frame);
 155
 156         val |= VIDEO_DIP_ENABLE;
 157
 158         I915_WRITE(VIDEO_DIP_CTL, val);
 159
 160         for (i = 0; i < len; i += 4) {
 161                 I915_WRITE(VIDEO_DIP_DATA, *data);
 162                 data++;
 163         }
 164
 165         val |= intel_infoframe_enable(frame);
 166         val |= intel_infoframe_frequency(frame);
 167
 168         I915_WRITE(VIDEO_DIP_CTL, val);
 169 }
 170
 171 static void ironlake_write_infoframe(struct drm_encoder *encoder,
 172                                      struct dip_infoframe *frame)
 173 {
 174         uint32_t *data = (uint32_t *)frame;
 175         struct drm_device *dev = encoder->dev;
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177         struct drm_crtc *crtc = encoder->crtc;
 178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 179         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 180         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 181         u32 val = I915_READ(reg);
 182
 183         intel_wait_for_vblank(dev, intel_crtc->pipe);
 184
 185         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 186         val |= intel_infoframe_index(frame);
 187
 188         val |= VIDEO_DIP_ENABLE;
 189
 190         I915_WRITE(reg, val);
 191
 192         for (i = 0; i < len; i += 4) {
 193                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 194                 data++;
 195         }
 196
 197         val |= intel_infoframe_enable(frame);
 198         val |= intel_infoframe_frequency(frame);
 199
 200         I915_WRITE(reg, val);
 201 }
 202
 203 static void vlv_write_infoframe(struct drm_encoder *encoder,
 204                                      struct dip_infoframe *frame)
 205 {
 206         uint32_t *data = (uint32_t *)frame;
 207         struct drm_device *dev = encoder->dev;
 208         struct drm_i915_private *dev_priv = dev->dev_private;
 209         struct drm_crtc *crtc = encoder->crtc;
 210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 211         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 212         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 213         u32 val = I915_READ(reg);
 214
 215         intel_wait_for_vblank(dev, intel_crtc->pipe);
 216
 217         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 218         val |= intel_infoframe_index(frame);
 219
 220         val |= VIDEO_DIP_ENABLE;
 221
 222         I915_WRITE(reg, val);
 223
 224         for (i = 0; i < len; i += 4) {
 225                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 226                 data++;
 227         }
 228
 229         val |= intel_infoframe_enable(frame);
 230         val |= intel_infoframe_frequency(frame);
 231
 232         I915_WRITE(reg, val);
 233 }
 234
 235 static void intel_set_infoframe(struct drm_encoder *encoder,
 236                                 struct dip_infoframe *frame)
 237 {
 238         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 239
 240         if (!intel_hdmi->has_hdmi_sink)
 241                 return;
 242
 243         intel_dip_infoframe_csum(frame);
 244         intel_hdmi->write_infoframe(encoder, frame);
 245 }
 246
 247 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 248                                          struct drm_display_mode *adjusted_mode)
 249 {
 250         struct dip_infoframe avi_if = {
 251                 .type = DIP_TYPE_AVI,
 252                 .ver = DIP_VERSION_AVI,
 253                 .len = DIP_LEN_AVI,
 254         };
 255
 256         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 257                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 258
 259         intel_set_infoframe(encoder, &avi_if);
 260 }
 261
 262 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 263 {
 264         struct dip_infoframe spd_if;
 265
 266         memset(&spd_if, 0, sizeof(spd_if));
 267         spd_if.type = DIP_TYPE_SPD;
 268         spd_if.ver = DIP_VERSION_SPD;
 269         spd_if.len = DIP_LEN_SPD;
 270         strcpy(spd_if.body.spd.vn, "Intel");
 271         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 272         spd_if.body.spd.sdi = DIP_SPD_PC;
 273
 274         intel_set_infoframe(encoder, &spd_if);
 275 }
 276
 277 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 278                                 struct drm_display_mode *mode,
 279                                 struct drm_display_mode *adjusted_mode)
 280 {
 281         struct drm_device *dev = encoder->dev;
 282         struct drm_i915_private *dev_priv = dev->dev_private;
 283         struct drm_crtc *crtc = encoder->crtc;
 284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 285         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 286         u32 sdvox;
 287
 288         sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
 289         if (!HAS_PCH_SPLIT(dev))
 290                 sdvox |= intel_hdmi->color_range;
 291         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 292                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 293         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 294                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 295
 296         if (intel_crtc->bpp > 24)
 297                 sdvox |= COLOR_FORMAT_12bpc;
 298         else
 299                 sdvox |= COLOR_FORMAT_8bpc;
 300
 301         /* Required on CPT */
 302         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 303                 sdvox |= HDMI_MODE_SELECT;
 304
 305         if (intel_hdmi->has_audio) {
 306                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 307                                  pipe_name(intel_crtc->pipe));
 308                 sdvox |= SDVO_AUDIO_ENABLE;
 309                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 310                 intel_write_eld(encoder, adjusted_mode);
 311         }
 312
 313         if (HAS_PCH_CPT(dev))
 314                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 315         else if (intel_crtc->pipe == 1)
 316                 sdvox |= SDVO_PIPE_B_SELECT;
 317
 318         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 319         POSTING_READ(intel_hdmi->sdvox_reg);
 320
 321         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 322         intel_hdmi_set_spd_infoframe(encoder);
 323 }
 324
 325 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
 326 {
 327         struct drm_device *dev = encoder->dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 330         u32 temp;
 331         u32 enable_bits = SDVO_ENABLE;
 332
 333         if (intel_hdmi->has_audio)
 334                 enable_bits |= SDVO_AUDIO_ENABLE;
 335
 336         temp = I915_READ(intel_hdmi->sdvox_reg);
 337
 338         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 339          * we do this anyway which shows more stable in testing.
 340          */
 341         if (HAS_PCH_SPLIT(dev)) {
 342                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 343                 POSTING_READ(intel_hdmi->sdvox_reg);
 344         }
 345
 346         if (mode != DRM_MODE_DPMS_ON) {
 347                 temp &= ~enable_bits;
 348         } else {
 349                 temp |= enable_bits;
 350         }
 351
 352         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 353         POSTING_READ(intel_hdmi->sdvox_reg);
 354
 355         /* HW workaround, need to write this twice for issue that may result
 356          * in first write getting masked.
 357          */
 358         if (HAS_PCH_SPLIT(dev)) {
 359                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 360                 POSTING_READ(intel_hdmi->sdvox_reg);
 361         }
 362 }
 363
 364 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 365                                  struct drm_display_mode *mode)
 366 {
 367         if (mode->clock > 165000)
 368                 return MODE_CLOCK_HIGH;
 369         if (mode->clock < 20000)
 370                 return MODE_CLOCK_LOW;
 371
 372         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 373                 return MODE_NO_DBLESCAN;
 374
 375         return MODE_OK;
 376 }
 377
 378 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 379                                   struct drm_display_mode *mode,
 380                                   struct drm_display_mode *adjusted_mode)
 381 {
 382         return true;
 383 }
 384
 385 static enum drm_connector_status
 386 intel_hdmi_detect(struct drm_connector *connector, bool force)
 387 {
 388         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 389         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 390         struct edid *edid;
 391         enum drm_connector_status status = connector_status_disconnected;
 392
 393         intel_hdmi->has_hdmi_sink = false;
 394         intel_hdmi->has_audio = false;
 395         edid = drm_get_edid(connector,
 396                             intel_gmbus_get_adapter(dev_priv,
 397                                                     intel_hdmi->ddc_bus));
 398
 399         if (edid) {
 400                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 401                         status = connector_status_connected;
 402                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 403                                 intel_hdmi->has_hdmi_sink =
 404                                                 drm_detect_hdmi_monitor(edid);
 405                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 406                 }
 407                 connector->display_info.raw_edid = NULL;
 408                 kfree(edid);
 409         }
 410
 411         if (status == connector_status_connected) {
 412                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 413                         intel_hdmi->has_audio =
 414                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 415         }
 416
 417         return status;
 418 }
 419
 420 static int intel_hdmi_get_modes(struct drm_connector *connector)
 421 {
 422         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 423         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 424
 425         /* We should parse the EDID data and find out if it's an HDMI sink so
 426          * we can send audio to it.
 427          */
 428
 429         return intel_ddc_get_modes(connector,
 430                                    intel_gmbus_get_adapter(dev_priv,
 431                                                            intel_hdmi->ddc_bus));
 432 }
 433
 434 static bool
 435 intel_hdmi_detect_audio(struct drm_connector *connector)
 436 {
 437         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 438         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 439         struct edid *edid;
 440         bool has_audio = false;
 441
 442         edid = drm_get_edid(connector,
 443                             intel_gmbus_get_adapter(dev_priv,
 444                                                     intel_hdmi->ddc_bus));
 445         if (edid) {
 446                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 447                         has_audio = drm_detect_monitor_audio(edid);
 448
 449                 connector->display_info.raw_edid = NULL;
 450                 kfree(edid);
 451         }
 452
 453         return has_audio;
 454 }
 455
 456 static int
 457 intel_hdmi_set_property(struct drm_connector *connector,
 458                       struct drm_property *property,
 459                       uint64_t val)
 460 {
 461         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 462         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 463         int ret;
 464
 465         ret = drm_connector_property_set_value(connector, property, val);
 466         if (ret)
 467                 return ret;
 468
 469         if (property == dev_priv->force_audio_property) {
 470                 enum hdmi_force_audio i = val;
 471                 bool has_audio;
 472
 473                 if (i == intel_hdmi->force_audio)
 474                         return 0;
 475
 476                 intel_hdmi->force_audio = i;
 477
 478                 if (i == HDMI_AUDIO_AUTO)
 479                         has_audio = intel_hdmi_detect_audio(connector);
 480                 else
 481                         has_audio = (i == HDMI_AUDIO_ON);
 482
 483                 if (i == HDMI_AUDIO_OFF_DVI)
 484                         intel_hdmi->has_hdmi_sink = 0;
 485
 486                 intel_hdmi->has_audio = has_audio;
 487                 goto done;
 488         }
 489
 490         if (property == dev_priv->broadcast_rgb_property) {
 491                 if (val == !!intel_hdmi->color_range)
 492                         return 0;
 493
 494                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 495                 goto done;
 496         }
 497
 498         return -EINVAL;
 499
 500 done:
 501         if (intel_hdmi->base.base.crtc) {
 502                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
 503                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
 504                                          crtc->x, crtc->y,
 505                                          crtc->fb);
 506         }
 507
 508         return 0;
 509 }
 510
 511 static void intel_hdmi_destroy(struct drm_connector *connector)
 512 {
 513         drm_sysfs_connector_remove(connector);
 514         drm_connector_cleanup(connector);
 515         kfree(connector);
 516 }
 517
 518 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 519         .dpms = intel_hdmi_dpms,
 520         .mode_fixup = intel_hdmi_mode_fixup,
 521         .prepare = intel_encoder_prepare,
 522         .mode_set = intel_hdmi_mode_set,
 523         .commit = intel_encoder_commit,
 524 };
 525
 526 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 527         .dpms = drm_helper_connector_dpms,
 528         .detect = intel_hdmi_detect,
 529         .fill_modes = drm_helper_probe_single_connector_modes,
 530         .set_property = intel_hdmi_set_property,
 531         .destroy = intel_hdmi_destroy,
 532 };
 533
 534 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 535         .get_modes = intel_hdmi_get_modes,
 536         .mode_valid = intel_hdmi_mode_valid,
 537         .best_encoder = intel_best_encoder,
 538 };
 539
 540 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 541         .destroy = intel_encoder_destroy,
 542 };
 543
 544 static void
 545 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 546 {
 547         intel_attach_force_audio_property(connector);
 548         intel_attach_broadcast_rgb_property(connector);
 549 }
 550
 551 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 552 {
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554         struct drm_connector *connector;
 555         struct intel_encoder *intel_encoder;
 556         struct intel_connector *intel_connector;
 557         struct intel_hdmi *intel_hdmi;
 558         int i;
 559
 560         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 561         if (!intel_hdmi)
 562                 return;
 563
 564         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 565         if (!intel_connector) {
 566                 kfree(intel_hdmi);
 567                 return;
 568         }
 569
 570         intel_encoder = &intel_hdmi->base;
 571         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
 572                          DRM_MODE_ENCODER_TMDS);
 573
 574         connector = &intel_connector->base;
 575         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 576                            DRM_MODE_CONNECTOR_HDMIA);
 577         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 578
 579         intel_encoder->type = INTEL_OUTPUT_HDMI;
 580
 581         connector->polled = DRM_CONNECTOR_POLL_HPD;
 582         connector->interlace_allowed = 1;
 583         connector->doublescan_allowed = 0;
 584         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 585
 586         /* Set up the DDC bus. */
 587         if (sdvox_reg == SDVOB) {
 588                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 589                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 590                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 591         } else if (sdvox_reg == SDVOC) {
 592                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 593                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 594                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 595         } else if (sdvox_reg == HDMIB) {
 596                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 597                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 598                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 599         } else if (sdvox_reg == HDMIC) {
 600                 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
 601                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 602                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 603         } else if (sdvox_reg == HDMID) {
 604                 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
 605                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 606                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 607         }
 608
 609         intel_hdmi->sdvox_reg = sdvox_reg;
 610
 611         if (!HAS_PCH_SPLIT(dev)) {
 612                 intel_hdmi->write_infoframe = i9xx_write_infoframe;
 613                 I915_WRITE(VIDEO_DIP_CTL, 0);
 614         } else if (IS_VALLEYVIEW(dev)) {
 615                 intel_hdmi->write_infoframe = vlv_write_infoframe;
 616                 for_each_pipe(i)
 617                         I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
 618         }  else {
 619                 intel_hdmi->write_infoframe = ironlake_write_infoframe;
 620                 for_each_pipe(i)
 621                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 622         }
 623
 624         drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
 625
 626         intel_hdmi_add_properties(intel_hdmi, connector);
 627
 628         intel_connector_attach_encoder(intel_connector, intel_encoder);
 629         drm_sysfs_connector_add(connector);
 630
 631         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
 632          * 0xd.  Failure to do so will result in spurious interrupts being
 633          * generated on the port when a cable is not attached.
 634          */
 635         if (IS_G4X(dev) && !IS_GM45(dev)) {
 636                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
 637                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
 638         }
 639 }