drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_crtc.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 struct intel_hdmi {
  41         struct intel_encoder base;
  42         u32 sdvox_reg;
  43         int ddc_bus;
  44         uint32_t color_range;
  45         bool has_hdmi_sink;
  46         bool has_audio;
  47         enum hdmi_force_audio force_audio;
  48         void (*write_infoframe)(struct drm_encoder *encoder,
  49                                 struct dip_infoframe *frame);
  50 };
  51
  52 static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  53 {
  54         return container_of(encoder, struct intel_hdmi, base.base);
  55 }
  56
  57 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  58 {
  59         return container_of(intel_attached_encoder(connector),
  60                             struct intel_hdmi, base);
  61 }
  62
  63 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  64 {
  65         uint8_t *data = (uint8_t *)frame;
  66         uint8_t sum = 0;
  67         unsigned i;
  68
  69         frame->checksum = 0;
  70         frame->ecc = 0;
  71
  72         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  73                 sum += data[i];
  74
  75         frame->checksum = 0x100 - sum;
  76 }
  77
  78 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  79 {
  80         u32 flags = 0;
  81
  82         switch (frame->type) {
  83         case DIP_TYPE_AVI:
  84                 flags |= VIDEO_DIP_SELECT_AVI;
  85                 break;
  86         case DIP_TYPE_SPD:
  87                 flags |= VIDEO_DIP_SELECT_SPD;
  88                 break;
  89         default:
  90                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  91                 break;
  92         }
  93
  94         return flags;
  95 }
  96
  97 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  98 {
  99         u32 flags = 0;
 100
 101         switch (frame->type) {
 102         case DIP_TYPE_AVI:
 103                 flags |= VIDEO_DIP_ENABLE_AVI;
 104                 break;
 105         case DIP_TYPE_SPD:
 106                 flags |= VIDEO_DIP_ENABLE_SPD;
 107                 break;
 108         default:
 109                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 110                 break;
 111         }
 112
 113         return flags;
 114 }
 115
 116 static void g4x_write_infoframe(struct drm_encoder *encoder,
 117                                 struct dip_infoframe *frame)
 118 {
 119         uint32_t *data = (uint32_t *)frame;
 120         struct drm_device *dev = encoder->dev;
 121         struct drm_i915_private *dev_priv = dev->dev_private;
 122         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 123         u32 val = I915_READ(VIDEO_DIP_CTL);
 124         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 125
 126
 127         /* XXX first guess at handling video port, is this corrent? */
 128         val &= ~VIDEO_DIP_PORT_MASK;
 129         if (intel_hdmi->sdvox_reg == SDVOB)
 130                 val |= VIDEO_DIP_PORT_B;
 131         else if (intel_hdmi->sdvox_reg == SDVOC)
 132                 val |= VIDEO_DIP_PORT_C;
 133         else
 134                 return;
 135
 136         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 137         val |= g4x_infoframe_index(frame);
 138
 139         val &= ~g4x_infoframe_enable(frame);
 140         val |= VIDEO_DIP_ENABLE;
 141
 142         I915_WRITE(VIDEO_DIP_CTL, val);
 143
 144         for (i = 0; i < len; i += 4) {
 145                 I915_WRITE(VIDEO_DIP_DATA, *data);
 146                 data++;
 147         }
 148
 149         val |= g4x_infoframe_enable(frame);
 150         val &= ~VIDEO_DIP_FREQ_MASK;
 151         val |= VIDEO_DIP_FREQ_VSYNC;
 152
 153         I915_WRITE(VIDEO_DIP_CTL, val);
 154 }
 155
 156 static void ibx_write_infoframe(struct drm_encoder *encoder,
 157                                 struct dip_infoframe *frame)
 158 {
 159         uint32_t *data = (uint32_t *)frame;
 160         struct drm_device *dev = encoder->dev;
 161         struct drm_i915_private *dev_priv = dev->dev_private;
 162         struct drm_crtc *crtc = encoder->crtc;
 163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 164         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 165         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 166         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 167         u32 val = I915_READ(reg);
 168
 169         val &= ~VIDEO_DIP_PORT_MASK;
 170         switch (intel_hdmi->sdvox_reg) {
 171         case HDMIB:
 172                 val |= VIDEO_DIP_PORT_B;
 173                 break;
 174         case HDMIC:
 175                 val |= VIDEO_DIP_PORT_C;
 176                 break;
 177         case HDMID:
 178                 val |= VIDEO_DIP_PORT_D;
 179                 break;
 180         default:
 181                 return;
 182         }
 183
 184         intel_wait_for_vblank(dev, intel_crtc->pipe);
 185
 186         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 187         val |= g4x_infoframe_index(frame);
 188
 189         val &= ~g4x_infoframe_enable(frame);
 190         val |= VIDEO_DIP_ENABLE;
 191
 192         I915_WRITE(reg, val);
 193
 194         for (i = 0; i < len; i += 4) {
 195                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 196                 data++;
 197         }
 198
 199         val |= g4x_infoframe_enable(frame);
 200         val &= ~VIDEO_DIP_FREQ_MASK;
 201         val |= VIDEO_DIP_FREQ_VSYNC;
 202
 203         I915_WRITE(reg, val);
 204 }
 205
 206 static void cpt_write_infoframe(struct drm_encoder *encoder,
 207                                 struct dip_infoframe *frame)
 208 {
 209         uint32_t *data = (uint32_t *)frame;
 210         struct drm_device *dev = encoder->dev;
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212         struct drm_crtc *crtc = encoder->crtc;
 213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 214         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 215         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 216         u32 val = I915_READ(reg);
 217
 218         intel_wait_for_vblank(dev, intel_crtc->pipe);
 219
 220         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 221         val |= g4x_infoframe_index(frame);
 222
 223         /* The DIP control register spec says that we need to update the AVI
 224          * infoframe without clearing its enable bit */
 225         if (frame->type == DIP_TYPE_AVI)
 226                 val |= VIDEO_DIP_ENABLE_AVI;
 227         else
 228                 val &= ~g4x_infoframe_enable(frame);
 229
 230         val |= VIDEO_DIP_ENABLE;
 231
 232         I915_WRITE(reg, val);
 233
 234         for (i = 0; i < len; i += 4) {
 235                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 236                 data++;
 237         }
 238
 239         val |= g4x_infoframe_enable(frame);
 240         val &= ~VIDEO_DIP_FREQ_MASK;
 241         val |= VIDEO_DIP_FREQ_VSYNC;
 242
 243         I915_WRITE(reg, val);
 244 }
 245
 246 static void vlv_write_infoframe(struct drm_encoder *encoder,
 247                                      struct dip_infoframe *frame)
 248 {
 249         uint32_t *data = (uint32_t *)frame;
 250         struct drm_device *dev = encoder->dev;
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         struct drm_crtc *crtc = encoder->crtc;
 253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 254         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 255         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 256         u32 val = I915_READ(reg);
 257
 258         intel_wait_for_vblank(dev, intel_crtc->pipe);
 259
 260         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 261         val |= g4x_infoframe_index(frame);
 262
 263         val &= ~g4x_infoframe_enable(frame);
 264         val |= VIDEO_DIP_ENABLE;
 265
 266         I915_WRITE(reg, val);
 267
 268         for (i = 0; i < len; i += 4) {
 269                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 270                 data++;
 271         }
 272
 273         val |= g4x_infoframe_enable(frame);
 274         val &= ~VIDEO_DIP_FREQ_MASK;
 275         val |= VIDEO_DIP_FREQ_VSYNC;
 276
 277         I915_WRITE(reg, val);
 278 }
 279
 280 static void hsw_write_infoframe(struct drm_encoder *encoder,
 281                                      struct dip_infoframe *frame)
 282 {
 283         /* Not implemented yet, so avoid doing anything at all.
 284          * This is the placeholder for Paulo Zanoni's infoframe writing patch
 285          */
 286         DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n");
 287
 288         return;
 289
 290 }
 291
 292 static void intel_set_infoframe(struct drm_encoder *encoder,
 293                                 struct dip_infoframe *frame)
 294 {
 295         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 296
 297         if (!intel_hdmi->has_hdmi_sink)
 298                 return;
 299
 300         intel_dip_infoframe_csum(frame);
 301         intel_hdmi->write_infoframe(encoder, frame);
 302 }
 303
 304 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 305                                          struct drm_display_mode *adjusted_mode)
 306 {
 307         struct dip_infoframe avi_if = {
 308                 .type = DIP_TYPE_AVI,
 309                 .ver = DIP_VERSION_AVI,
 310                 .len = DIP_LEN_AVI,
 311         };
 312
 313         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 314                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 315
 316         intel_set_infoframe(encoder, &avi_if);
 317 }
 318
 319 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 320 {
 321         struct dip_infoframe spd_if;
 322
 323         memset(&spd_if, 0, sizeof(spd_if));
 324         spd_if.type = DIP_TYPE_SPD;
 325         spd_if.ver = DIP_VERSION_SPD;
 326         spd_if.len = DIP_LEN_SPD;
 327         strcpy(spd_if.body.spd.vn, "Intel");
 328         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 329         spd_if.body.spd.sdi = DIP_SPD_PC;
 330
 331         intel_set_infoframe(encoder, &spd_if);
 332 }
 333
 334 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 335                                 struct drm_display_mode *mode,
 336                                 struct drm_display_mode *adjusted_mode)
 337 {
 338         struct drm_device *dev = encoder->dev;
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340         struct drm_crtc *crtc = encoder->crtc;
 341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 342         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 343         u32 sdvox;
 344
 345         sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
 346         if (!HAS_PCH_SPLIT(dev))
 347                 sdvox |= intel_hdmi->color_range;
 348         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 349                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 350         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 351                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 352
 353         if (intel_crtc->bpp > 24)
 354                 sdvox |= COLOR_FORMAT_12bpc;
 355         else
 356                 sdvox |= COLOR_FORMAT_8bpc;
 357
 358         /* Required on CPT */
 359         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 360                 sdvox |= HDMI_MODE_SELECT;
 361
 362         if (intel_hdmi->has_audio) {
 363                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 364                                  pipe_name(intel_crtc->pipe));
 365                 sdvox |= SDVO_AUDIO_ENABLE;
 366                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 367                 intel_write_eld(encoder, adjusted_mode);
 368         }
 369
 370         if (HAS_PCH_CPT(dev))
 371                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 372         else if (intel_crtc->pipe == 1)
 373                 sdvox |= SDVO_PIPE_B_SELECT;
 374
 375         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 376         POSTING_READ(intel_hdmi->sdvox_reg);
 377
 378         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 379         intel_hdmi_set_spd_infoframe(encoder);
 380 }
 381
 382 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
 383 {
 384         struct drm_device *dev = encoder->dev;
 385         struct drm_i915_private *dev_priv = dev->dev_private;
 386         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 387         u32 temp;
 388         u32 enable_bits = SDVO_ENABLE;
 389
 390         if (intel_hdmi->has_audio)
 391                 enable_bits |= SDVO_AUDIO_ENABLE;
 392
 393         temp = I915_READ(intel_hdmi->sdvox_reg);
 394
 395         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 396          * we do this anyway which shows more stable in testing.
 397          */
 398         if (HAS_PCH_SPLIT(dev)) {
 399                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 400                 POSTING_READ(intel_hdmi->sdvox_reg);
 401         }
 402
 403         if (mode != DRM_MODE_DPMS_ON) {
 404                 temp &= ~enable_bits;
 405         } else {
 406                 temp |= enable_bits;
 407         }
 408
 409         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 410         POSTING_READ(intel_hdmi->sdvox_reg);
 411
 412         /* HW workaround, need to write this twice for issue that may result
 413          * in first write getting masked.
 414          */
 415         if (HAS_PCH_SPLIT(dev)) {
 416                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 417                 POSTING_READ(intel_hdmi->sdvox_reg);
 418         }
 419 }
 420
 421 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 422                                  struct drm_display_mode *mode)
 423 {
 424         if (mode->clock > 165000)
 425                 return MODE_CLOCK_HIGH;
 426         if (mode->clock < 20000)
 427                 return MODE_CLOCK_LOW;
 428
 429         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 430                 return MODE_NO_DBLESCAN;
 431
 432         return MODE_OK;
 433 }
 434
 435 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 436                                   struct drm_display_mode *mode,
 437                                   struct drm_display_mode *adjusted_mode)
 438 {
 439         return true;
 440 }
 441
 442 static enum drm_connector_status
 443 intel_hdmi_detect(struct drm_connector *connector, bool force)
 444 {
 445         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 446         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 447         struct edid *edid;
 448         enum drm_connector_status status = connector_status_disconnected;
 449
 450         intel_hdmi->has_hdmi_sink = false;
 451         intel_hdmi->has_audio = false;
 452         edid = drm_get_edid(connector,
 453                             intel_gmbus_get_adapter(dev_priv,
 454                                                     intel_hdmi->ddc_bus));
 455
 456         if (edid) {
 457                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 458                         status = connector_status_connected;
 459                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 460                                 intel_hdmi->has_hdmi_sink =
 461                                                 drm_detect_hdmi_monitor(edid);
 462                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 463                 }
 464                 connector->display_info.raw_edid = NULL;
 465                 kfree(edid);
 466         }
 467
 468         if (status == connector_status_connected) {
 469                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 470                         intel_hdmi->has_audio =
 471                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 472         }
 473
 474         return status;
 475 }
 476
 477 static int intel_hdmi_get_modes(struct drm_connector *connector)
 478 {
 479         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 480         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 481
 482         /* We should parse the EDID data and find out if it's an HDMI sink so
 483          * we can send audio to it.
 484          */
 485
 486         return intel_ddc_get_modes(connector,
 487                                    intel_gmbus_get_adapter(dev_priv,
 488                                                            intel_hdmi->ddc_bus));
 489 }
 490
 491 static bool
 492 intel_hdmi_detect_audio(struct drm_connector *connector)
 493 {
 494         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 495         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 496         struct edid *edid;
 497         bool has_audio = false;
 498
 499         edid = drm_get_edid(connector,
 500                             intel_gmbus_get_adapter(dev_priv,
 501                                                     intel_hdmi->ddc_bus));
 502         if (edid) {
 503                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 504                         has_audio = drm_detect_monitor_audio(edid);
 505
 506                 connector->display_info.raw_edid = NULL;
 507                 kfree(edid);
 508         }
 509
 510         return has_audio;
 511 }
 512
 513 static int
 514 intel_hdmi_set_property(struct drm_connector *connector,
 515                       struct drm_property *property,
 516                       uint64_t val)
 517 {
 518         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 519         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 520         int ret;
 521
 522         ret = drm_connector_property_set_value(connector, property, val);
 523         if (ret)
 524                 return ret;
 525
 526         if (property == dev_priv->force_audio_property) {
 527                 enum hdmi_force_audio i = val;
 528                 bool has_audio;
 529
 530                 if (i == intel_hdmi->force_audio)
 531                         return 0;
 532
 533                 intel_hdmi->force_audio = i;
 534
 535                 if (i == HDMI_AUDIO_AUTO)
 536                         has_audio = intel_hdmi_detect_audio(connector);
 537                 else
 538                         has_audio = (i == HDMI_AUDIO_ON);
 539
 540                 if (i == HDMI_AUDIO_OFF_DVI)
 541                         intel_hdmi->has_hdmi_sink = 0;
 542
 543                 intel_hdmi->has_audio = has_audio;
 544                 goto done;
 545         }
 546
 547         if (property == dev_priv->broadcast_rgb_property) {
 548                 if (val == !!intel_hdmi->color_range)
 549                         return 0;
 550
 551                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 552                 goto done;
 553         }
 554
 555         return -EINVAL;
 556
 557 done:
 558         if (intel_hdmi->base.base.crtc) {
 559                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
 560                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
 561                                          crtc->x, crtc->y,
 562                                          crtc->fb);
 563         }
 564
 565         return 0;
 566 }
 567
 568 static void intel_hdmi_destroy(struct drm_connector *connector)
 569 {
 570         drm_sysfs_connector_remove(connector);
 571         drm_connector_cleanup(connector);
 572         kfree(connector);
 573 }
 574
 575 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 576         .dpms = intel_hdmi_dpms,
 577         .mode_fixup = intel_hdmi_mode_fixup,
 578         .prepare = intel_encoder_prepare,
 579         .mode_set = intel_hdmi_mode_set,
 580         .commit = intel_encoder_commit,
 581 };
 582
 583 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 584         .dpms = drm_helper_connector_dpms,
 585         .detect = intel_hdmi_detect,
 586         .fill_modes = drm_helper_probe_single_connector_modes,
 587         .set_property = intel_hdmi_set_property,
 588         .destroy = intel_hdmi_destroy,
 589 };
 590
 591 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 592         .get_modes = intel_hdmi_get_modes,
 593         .mode_valid = intel_hdmi_mode_valid,
 594         .best_encoder = intel_best_encoder,
 595 };
 596
 597 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 598         .destroy = intel_encoder_destroy,
 599 };
 600
 601 static void
 602 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 603 {
 604         intel_attach_force_audio_property(connector);
 605         intel_attach_broadcast_rgb_property(connector);
 606 }
 607
 608 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 609 {
 610         struct drm_i915_private *dev_priv = dev->dev_private;
 611         struct drm_connector *connector;
 612         struct intel_encoder *intel_encoder;
 613         struct intel_connector *intel_connector;
 614         struct intel_hdmi *intel_hdmi;
 615         int i;
 616
 617         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 618         if (!intel_hdmi)
 619                 return;
 620
 621         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 622         if (!intel_connector) {
 623                 kfree(intel_hdmi);
 624                 return;
 625         }
 626
 627         intel_encoder = &intel_hdmi->base;
 628         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
 629                          DRM_MODE_ENCODER_TMDS);
 630
 631         connector = &intel_connector->base;
 632         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 633                            DRM_MODE_CONNECTOR_HDMIA);
 634         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 635
 636         intel_encoder->type = INTEL_OUTPUT_HDMI;
 637
 638         connector->polled = DRM_CONNECTOR_POLL_HPD;
 639         connector->interlace_allowed = 1;
 640         connector->doublescan_allowed = 0;
 641         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 642
 643         /* Set up the DDC bus. */
 644         if (sdvox_reg == SDVOB) {
 645                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 646                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 647                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 648         } else if (sdvox_reg == SDVOC) {
 649                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 650                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 651                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 652         } else if (sdvox_reg == HDMIB) {
 653                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 654                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 655                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 656         } else if (sdvox_reg == HDMIC) {
 657                 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
 658                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 659                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 660         } else if (sdvox_reg == HDMID) {
 661                 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
 662                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 663                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 664         } else {
 665                 /* If we got an unknown sdvox_reg, things are pretty much broken
 666                  * in a way that we should let the kernel know about it */
 667                 BUG();
 668         }
 669
 670         intel_hdmi->sdvox_reg = sdvox_reg;
 671
 672         if (!HAS_PCH_SPLIT(dev)) {
 673                 intel_hdmi->write_infoframe = g4x_write_infoframe;
 674                 I915_WRITE(VIDEO_DIP_CTL, 0);
 675         } else if (IS_VALLEYVIEW(dev)) {
 676                 intel_hdmi->write_infoframe = vlv_write_infoframe;
 677                 for_each_pipe(i)
 678                         I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
 679         } else if (IS_HASWELL(dev)) {
 680                 /* FIXME: Haswell has a new set of DIP frame registers, but we are
 681                  * just doing the minimal required for HDMI to work at this stage.
 682                  */
 683                 intel_hdmi->write_infoframe = hsw_write_infoframe;
 684                 for_each_pipe(i)
 685                         I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
 686         } else if (HAS_PCH_IBX(dev)) {
 687                 intel_hdmi->write_infoframe = ibx_write_infoframe;
 688                 for_each_pipe(i)
 689                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 690         } else {
 691                 intel_hdmi->write_infoframe = cpt_write_infoframe;
 692                 for_each_pipe(i)
 693                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 694         }
 695
 696         drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
 697
 698         intel_hdmi_add_properties(intel_hdmi, connector);
 699
 700         intel_connector_attach_encoder(intel_connector, intel_encoder);
 701         drm_sysfs_connector_add(connector);
 702
 703         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
 704          * 0xd.  Failure to do so will result in spurious interrupts being
 705          * generated on the port when a cable is not attached.
 706          */
 707         if (IS_G4X(dev) && !IS_GM45(dev)) {
 708                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
 709                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
 710         }
 711 }