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drm/i915: Implement PHY lane power gating for CHV
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42 {
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
44 }
45
46 static void
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48 {
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
52
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
57 }
58
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
60 {
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
64 }
65
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67 {
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
69 }
70
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
72 {
73 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
80 default:
81 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
82 return 0;
83 }
84 }
85
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
87 {
88 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
95 default:
96 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
97 return 0;
98 }
99 }
100
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
102 {
103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
110 default:
111 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
112 return 0;
113 }
114 }
115
116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
117 enum transcoder cpu_transcoder,
118 struct drm_i915_private *dev_priv)
119 {
120 switch (type) {
121 case HDMI_INFOFRAME_TYPE_AVI:
122 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
123 case HDMI_INFOFRAME_TYPE_SPD:
124 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
125 case HDMI_INFOFRAME_TYPE_VENDOR:
126 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
127 default:
128 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
129 return 0;
130 }
131 }
132
133 static void g4x_write_infoframe(struct drm_encoder *encoder,
134 enum hdmi_infoframe_type type,
135 const void *frame, ssize_t len)
136 {
137 const uint32_t *data = frame;
138 struct drm_device *dev = encoder->dev;
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 u32 val = I915_READ(VIDEO_DIP_CTL);
141 int i;
142
143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
144
145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
146 val |= g4x_infoframe_index(type);
147
148 val &= ~g4x_infoframe_enable(type);
149
150 I915_WRITE(VIDEO_DIP_CTL, val);
151
152 mmiowb();
153 for (i = 0; i < len; i += 4) {
154 I915_WRITE(VIDEO_DIP_DATA, *data);
155 data++;
156 }
157 /* Write every possible data byte to force correct ECC calculation. */
158 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
159 I915_WRITE(VIDEO_DIP_DATA, 0);
160 mmiowb();
161
162 val |= g4x_infoframe_enable(type);
163 val &= ~VIDEO_DIP_FREQ_MASK;
164 val |= VIDEO_DIP_FREQ_VSYNC;
165
166 I915_WRITE(VIDEO_DIP_CTL, val);
167 POSTING_READ(VIDEO_DIP_CTL);
168 }
169
170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
171 {
172 struct drm_device *dev = encoder->dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
175 u32 val = I915_READ(VIDEO_DIP_CTL);
176
177 if ((val & VIDEO_DIP_ENABLE) == 0)
178 return false;
179
180 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
181 return false;
182
183 return val & (VIDEO_DIP_ENABLE_AVI |
184 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
185 }
186
187 static void ibx_write_infoframe(struct drm_encoder *encoder,
188 enum hdmi_infoframe_type type,
189 const void *frame, ssize_t len)
190 {
191 const uint32_t *data = frame;
192 struct drm_device *dev = encoder->dev;
193 struct drm_i915_private *dev_priv = dev->dev_private;
194 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
195 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
196 u32 val = I915_READ(reg);
197
198 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
199
200 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
201 val |= g4x_infoframe_index(type);
202
203 val &= ~g4x_infoframe_enable(type);
204
205 I915_WRITE(reg, val);
206
207 mmiowb();
208 for (i = 0; i < len; i += 4) {
209 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
210 data++;
211 }
212 /* Write every possible data byte to force correct ECC calculation. */
213 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
214 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
215 mmiowb();
216
217 val |= g4x_infoframe_enable(type);
218 val &= ~VIDEO_DIP_FREQ_MASK;
219 val |= VIDEO_DIP_FREQ_VSYNC;
220
221 I915_WRITE(reg, val);
222 POSTING_READ(reg);
223 }
224
225 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
226 {
227 struct drm_device *dev = encoder->dev;
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
230 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
231 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
232 u32 val = I915_READ(reg);
233
234 if ((val & VIDEO_DIP_ENABLE) == 0)
235 return false;
236
237 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
238 return false;
239
240 return val & (VIDEO_DIP_ENABLE_AVI |
241 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
242 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
243 }
244
245 static void cpt_write_infoframe(struct drm_encoder *encoder,
246 enum hdmi_infoframe_type type,
247 const void *frame, ssize_t len)
248 {
249 const uint32_t *data = frame;
250 struct drm_device *dev = encoder->dev;
251 struct drm_i915_private *dev_priv = dev->dev_private;
252 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
253 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
254 u32 val = I915_READ(reg);
255
256 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
257
258 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
259 val |= g4x_infoframe_index(type);
260
261 /* The DIP control register spec says that we need to update the AVI
262 * infoframe without clearing its enable bit */
263 if (type != HDMI_INFOFRAME_TYPE_AVI)
264 val &= ~g4x_infoframe_enable(type);
265
266 I915_WRITE(reg, val);
267
268 mmiowb();
269 for (i = 0; i < len; i += 4) {
270 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
271 data++;
272 }
273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
275 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
276 mmiowb();
277
278 val |= g4x_infoframe_enable(type);
279 val &= ~VIDEO_DIP_FREQ_MASK;
280 val |= VIDEO_DIP_FREQ_VSYNC;
281
282 I915_WRITE(reg, val);
283 POSTING_READ(reg);
284 }
285
286 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
287 {
288 struct drm_device *dev = encoder->dev;
289 struct drm_i915_private *dev_priv = dev->dev_private;
290 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
291 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
292 u32 val = I915_READ(reg);
293
294 if ((val & VIDEO_DIP_ENABLE) == 0)
295 return false;
296
297 return val & (VIDEO_DIP_ENABLE_AVI |
298 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
299 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
300 }
301
302 static void vlv_write_infoframe(struct drm_encoder *encoder,
303 enum hdmi_infoframe_type type,
304 const void *frame, ssize_t len)
305 {
306 const uint32_t *data = frame;
307 struct drm_device *dev = encoder->dev;
308 struct drm_i915_private *dev_priv = dev->dev_private;
309 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
310 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
311 u32 val = I915_READ(reg);
312
313 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
314
315 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
316 val |= g4x_infoframe_index(type);
317
318 val &= ~g4x_infoframe_enable(type);
319
320 I915_WRITE(reg, val);
321
322 mmiowb();
323 for (i = 0; i < len; i += 4) {
324 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
325 data++;
326 }
327 /* Write every possible data byte to force correct ECC calculation. */
328 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
329 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
330 mmiowb();
331
332 val |= g4x_infoframe_enable(type);
333 val &= ~VIDEO_DIP_FREQ_MASK;
334 val |= VIDEO_DIP_FREQ_VSYNC;
335
336 I915_WRITE(reg, val);
337 POSTING_READ(reg);
338 }
339
340 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
341 {
342 struct drm_device *dev = encoder->dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
344 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
345 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
346 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
347 u32 val = I915_READ(reg);
348
349 if ((val & VIDEO_DIP_ENABLE) == 0)
350 return false;
351
352 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
353 return false;
354
355 return val & (VIDEO_DIP_ENABLE_AVI |
356 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
357 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
358 }
359
360 static void hsw_write_infoframe(struct drm_encoder *encoder,
361 enum hdmi_infoframe_type type,
362 const void *frame, ssize_t len)
363 {
364 const uint32_t *data = frame;
365 struct drm_device *dev = encoder->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
368 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
369 u32 data_reg;
370 int i;
371 u32 val = I915_READ(ctl_reg);
372
373 data_reg = hsw_infoframe_data_reg(type,
374 intel_crtc->config->cpu_transcoder,
375 dev_priv);
376 if (data_reg == 0)
377 return;
378
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
381
382 mmiowb();
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(data_reg + i, *data);
385 data++;
386 }
387 /* Write every possible data byte to force correct ECC calculation. */
388 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
389 I915_WRITE(data_reg + i, 0);
390 mmiowb();
391
392 val |= hsw_infoframe_enable(type);
393 I915_WRITE(ctl_reg, val);
394 POSTING_READ(ctl_reg);
395 }
396
397 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
398 {
399 struct drm_device *dev = encoder->dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
402 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
403 u32 val = I915_READ(ctl_reg);
404
405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
408 }
409
410 /*
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
415 *
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
419 * DW3: ...
420 *
421 * (HB is Header Byte, DB is Data Byte)
422 *
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
425 * bytes by one.
426 */
427 static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
429 {
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
432 ssize_t len;
433
434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
436 if (len < 0)
437 return;
438
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
443 buffer[3] = 0;
444 len++;
445
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
447 }
448
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
450 struct drm_display_mode *adjusted_mode)
451 {
452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
454 union hdmi_infoframe frame;
455 int ret;
456
457 /* Set user selected PAR to incoming mode's member */
458 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
459
460 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
461 adjusted_mode);
462 if (ret < 0) {
463 DRM_ERROR("couldn't fill AVI infoframe\n");
464 return;
465 }
466
467 if (intel_hdmi->rgb_quant_range_selectable) {
468 if (intel_crtc->config->limited_color_range)
469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_LIMITED;
471 else
472 frame.avi.quantization_range =
473 HDMI_QUANTIZATION_RANGE_FULL;
474 }
475
476 intel_write_infoframe(encoder, &frame);
477 }
478
479 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
480 {
481 union hdmi_infoframe frame;
482 int ret;
483
484 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
485 if (ret < 0) {
486 DRM_ERROR("couldn't fill SPD infoframe\n");
487 return;
488 }
489
490 frame.spd.sdi = HDMI_SPD_SDI_PC;
491
492 intel_write_infoframe(encoder, &frame);
493 }
494
495 static void
496 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
497 struct drm_display_mode *adjusted_mode)
498 {
499 union hdmi_infoframe frame;
500 int ret;
501
502 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
503 adjusted_mode);
504 if (ret < 0)
505 return;
506
507 intel_write_infoframe(encoder, &frame);
508 }
509
510 static void g4x_set_infoframes(struct drm_encoder *encoder,
511 bool enable,
512 struct drm_display_mode *adjusted_mode)
513 {
514 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
515 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
516 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
517 u32 reg = VIDEO_DIP_CTL;
518 u32 val = I915_READ(reg);
519 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
520
521 assert_hdmi_port_disabled(intel_hdmi);
522
523 /* If the registers were not initialized yet, they might be zeroes,
524 * which means we're selecting the AVI DIP and we're setting its
525 * frequency to once. This seems to really confuse the HW and make
526 * things stop working (the register spec says the AVI always needs to
527 * be sent every VSync). So here we avoid writing to the register more
528 * than we need and also explicitly select the AVI DIP and explicitly
529 * set its frequency to every VSync. Avoiding to write it twice seems to
530 * be enough to solve the problem, but being defensive shouldn't hurt us
531 * either. */
532 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
533
534 if (!enable) {
535 if (!(val & VIDEO_DIP_ENABLE))
536 return;
537 if (port != (val & VIDEO_DIP_PORT_MASK)) {
538 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
539 (val & VIDEO_DIP_PORT_MASK) >> 29);
540 return;
541 }
542 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
543 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
544 I915_WRITE(reg, val);
545 POSTING_READ(reg);
546 return;
547 }
548
549 if (port != (val & VIDEO_DIP_PORT_MASK)) {
550 if (val & VIDEO_DIP_ENABLE) {
551 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
552 (val & VIDEO_DIP_PORT_MASK) >> 29);
553 return;
554 }
555 val &= ~VIDEO_DIP_PORT_MASK;
556 val |= port;
557 }
558
559 val |= VIDEO_DIP_ENABLE;
560 val &= ~(VIDEO_DIP_ENABLE_AVI |
561 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
562
563 I915_WRITE(reg, val);
564 POSTING_READ(reg);
565
566 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
567 intel_hdmi_set_spd_infoframe(encoder);
568 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
569 }
570
571 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
572 {
573 struct drm_device *dev = encoder->dev;
574 struct drm_connector *connector;
575
576 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
577
578 /*
579 * HDMI cloning is only supported on g4x which doesn't
580 * support deep color or GCP infoframes anyway so no
581 * need to worry about multiple HDMI sinks here.
582 */
583 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
584 if (connector->encoder == encoder)
585 return connector->display_info.bpc > 8;
586
587 return false;
588 }
589
590 /*
591 * Determine if default_phase=1 can be indicated in the GCP infoframe.
592 *
593 * From HDMI specification 1.4a:
594 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
595 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
596 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
597 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
598 * phase of 0
599 */
600 static bool gcp_default_phase_possible(int pipe_bpp,
601 const struct drm_display_mode *mode)
602 {
603 unsigned int pixels_per_group;
604
605 switch (pipe_bpp) {
606 case 30:
607 /* 4 pixels in 5 clocks */
608 pixels_per_group = 4;
609 break;
610 case 36:
611 /* 2 pixels in 3 clocks */
612 pixels_per_group = 2;
613 break;
614 case 48:
615 /* 1 pixel in 2 clocks */
616 pixels_per_group = 1;
617 break;
618 default:
619 /* phase information not relevant for 8bpc */
620 return false;
621 }
622
623 return mode->crtc_hdisplay % pixels_per_group == 0 &&
624 mode->crtc_htotal % pixels_per_group == 0 &&
625 mode->crtc_hblank_start % pixels_per_group == 0 &&
626 mode->crtc_hblank_end % pixels_per_group == 0 &&
627 mode->crtc_hsync_start % pixels_per_group == 0 &&
628 mode->crtc_hsync_end % pixels_per_group == 0 &&
629 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
630 mode->crtc_htotal/2 % pixels_per_group == 0);
631 }
632
633 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
634 {
635 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
636 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
637 u32 reg, val = 0;
638
639 if (HAS_DDI(dev_priv))
640 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
641 else if (IS_VALLEYVIEW(dev_priv))
642 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
643 else if (HAS_PCH_SPLIT(dev_priv->dev))
644 reg = TVIDEO_DIP_GCP(crtc->pipe);
645 else
646 return false;
647
648 /* Indicate color depth whenever the sink supports deep color */
649 if (hdmi_sink_is_deep_color(encoder))
650 val |= GCP_COLOR_INDICATION;
651
652 /* Enable default_phase whenever the display mode is suitably aligned */
653 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
654 &crtc->config->base.adjusted_mode))
655 val |= GCP_DEFAULT_PHASE_ENABLE;
656
657 I915_WRITE(reg, val);
658
659 return val != 0;
660 }
661
662 static void ibx_set_infoframes(struct drm_encoder *encoder,
663 bool enable,
664 struct drm_display_mode *adjusted_mode)
665 {
666 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
667 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
668 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
669 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
670 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
671 u32 val = I915_READ(reg);
672 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
673
674 assert_hdmi_port_disabled(intel_hdmi);
675
676 /* See the big comment in g4x_set_infoframes() */
677 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
678
679 if (!enable) {
680 if (!(val & VIDEO_DIP_ENABLE))
681 return;
682 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
683 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
684 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
685 I915_WRITE(reg, val);
686 POSTING_READ(reg);
687 return;
688 }
689
690 if (port != (val & VIDEO_DIP_PORT_MASK)) {
691 WARN(val & VIDEO_DIP_ENABLE,
692 "DIP already enabled on port %c\n",
693 (val & VIDEO_DIP_PORT_MASK) >> 29);
694 val &= ~VIDEO_DIP_PORT_MASK;
695 val |= port;
696 }
697
698 val |= VIDEO_DIP_ENABLE;
699 val &= ~(VIDEO_DIP_ENABLE_AVI |
700 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
701 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
702
703 if (intel_hdmi_set_gcp_infoframe(encoder))
704 val |= VIDEO_DIP_ENABLE_GCP;
705
706 I915_WRITE(reg, val);
707 POSTING_READ(reg);
708
709 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
710 intel_hdmi_set_spd_infoframe(encoder);
711 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
712 }
713
714 static void cpt_set_infoframes(struct drm_encoder *encoder,
715 bool enable,
716 struct drm_display_mode *adjusted_mode)
717 {
718 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
719 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
720 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
721 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
722 u32 val = I915_READ(reg);
723
724 assert_hdmi_port_disabled(intel_hdmi);
725
726 /* See the big comment in g4x_set_infoframes() */
727 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
728
729 if (!enable) {
730 if (!(val & VIDEO_DIP_ENABLE))
731 return;
732 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
733 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
734 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
735 I915_WRITE(reg, val);
736 POSTING_READ(reg);
737 return;
738 }
739
740 /* Set both together, unset both together: see the spec. */
741 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
742 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
743 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
744
745 if (intel_hdmi_set_gcp_infoframe(encoder))
746 val |= VIDEO_DIP_ENABLE_GCP;
747
748 I915_WRITE(reg, val);
749 POSTING_READ(reg);
750
751 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
752 intel_hdmi_set_spd_infoframe(encoder);
753 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
754 }
755
756 static void vlv_set_infoframes(struct drm_encoder *encoder,
757 bool enable,
758 struct drm_display_mode *adjusted_mode)
759 {
760 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
761 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
762 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
763 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
764 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
765 u32 val = I915_READ(reg);
766 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
767
768 assert_hdmi_port_disabled(intel_hdmi);
769
770 /* See the big comment in g4x_set_infoframes() */
771 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
772
773 if (!enable) {
774 if (!(val & VIDEO_DIP_ENABLE))
775 return;
776 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
777 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
778 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
779 I915_WRITE(reg, val);
780 POSTING_READ(reg);
781 return;
782 }
783
784 if (port != (val & VIDEO_DIP_PORT_MASK)) {
785 WARN(val & VIDEO_DIP_ENABLE,
786 "DIP already enabled on port %c\n",
787 (val & VIDEO_DIP_PORT_MASK) >> 29);
788 val &= ~VIDEO_DIP_PORT_MASK;
789 val |= port;
790 }
791
792 val |= VIDEO_DIP_ENABLE;
793 val &= ~(VIDEO_DIP_ENABLE_AVI |
794 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
795 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
796
797 if (intel_hdmi_set_gcp_infoframe(encoder))
798 val |= VIDEO_DIP_ENABLE_GCP;
799
800 I915_WRITE(reg, val);
801 POSTING_READ(reg);
802
803 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
804 intel_hdmi_set_spd_infoframe(encoder);
805 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
806 }
807
808 static void hsw_set_infoframes(struct drm_encoder *encoder,
809 bool enable,
810 struct drm_display_mode *adjusted_mode)
811 {
812 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
813 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
814 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
815 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
816 u32 val = I915_READ(reg);
817
818 assert_hdmi_port_disabled(intel_hdmi);
819
820 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
821 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
822 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
823
824 if (!enable) {
825 I915_WRITE(reg, val);
826 POSTING_READ(reg);
827 return;
828 }
829
830 if (intel_hdmi_set_gcp_infoframe(encoder))
831 val |= VIDEO_DIP_ENABLE_GCP_HSW;
832
833 I915_WRITE(reg, val);
834 POSTING_READ(reg);
835
836 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
837 intel_hdmi_set_spd_infoframe(encoder);
838 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
839 }
840
841 static void intel_hdmi_prepare(struct intel_encoder *encoder)
842 {
843 struct drm_device *dev = encoder->base.dev;
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
846 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
847 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
848 u32 hdmi_val;
849
850 hdmi_val = SDVO_ENCODING_HDMI;
851 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
852 hdmi_val |= HDMI_COLOR_RANGE_16_235;
853 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
854 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
855 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
856 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
857
858 if (crtc->config->pipe_bpp > 24)
859 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
860 else
861 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
862
863 if (crtc->config->has_hdmi_sink)
864 hdmi_val |= HDMI_MODE_SELECT_HDMI;
865
866 if (HAS_PCH_CPT(dev))
867 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
868 else if (IS_CHERRYVIEW(dev))
869 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
870 else
871 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
872
873 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
874 POSTING_READ(intel_hdmi->hdmi_reg);
875 }
876
877 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
878 enum pipe *pipe)
879 {
880 struct drm_device *dev = encoder->base.dev;
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
883 enum intel_display_power_domain power_domain;
884 u32 tmp;
885
886 power_domain = intel_display_port_power_domain(encoder);
887 if (!intel_display_power_is_enabled(dev_priv, power_domain))
888 return false;
889
890 tmp = I915_READ(intel_hdmi->hdmi_reg);
891
892 if (!(tmp & SDVO_ENABLE))
893 return false;
894
895 if (HAS_PCH_CPT(dev))
896 *pipe = PORT_TO_PIPE_CPT(tmp);
897 else if (IS_CHERRYVIEW(dev))
898 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
899 else
900 *pipe = PORT_TO_PIPE(tmp);
901
902 return true;
903 }
904
905 static void intel_hdmi_get_config(struct intel_encoder *encoder,
906 struct intel_crtc_state *pipe_config)
907 {
908 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
909 struct drm_device *dev = encoder->base.dev;
910 struct drm_i915_private *dev_priv = dev->dev_private;
911 u32 tmp, flags = 0;
912 int dotclock;
913
914 tmp = I915_READ(intel_hdmi->hdmi_reg);
915
916 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
917 flags |= DRM_MODE_FLAG_PHSYNC;
918 else
919 flags |= DRM_MODE_FLAG_NHSYNC;
920
921 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
922 flags |= DRM_MODE_FLAG_PVSYNC;
923 else
924 flags |= DRM_MODE_FLAG_NVSYNC;
925
926 if (tmp & HDMI_MODE_SELECT_HDMI)
927 pipe_config->has_hdmi_sink = true;
928
929 if (intel_hdmi->infoframe_enabled(&encoder->base))
930 pipe_config->has_infoframe = true;
931
932 if (tmp & SDVO_AUDIO_ENABLE)
933 pipe_config->has_audio = true;
934
935 if (!HAS_PCH_SPLIT(dev) &&
936 tmp & HDMI_COLOR_RANGE_16_235)
937 pipe_config->limited_color_range = true;
938
939 pipe_config->base.adjusted_mode.flags |= flags;
940
941 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
942 dotclock = pipe_config->port_clock * 2 / 3;
943 else
944 dotclock = pipe_config->port_clock;
945
946 if (pipe_config->pixel_multiplier)
947 dotclock /= pipe_config->pixel_multiplier;
948
949 if (HAS_PCH_SPLIT(dev_priv->dev))
950 ironlake_check_encoder_dotclock(pipe_config, dotclock);
951
952 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
953 }
954
955 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
956 {
957 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
958
959 WARN_ON(!crtc->config->has_hdmi_sink);
960 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
961 pipe_name(crtc->pipe));
962 intel_audio_codec_enable(encoder);
963 }
964
965 static void g4x_enable_hdmi(struct intel_encoder *encoder)
966 {
967 struct drm_device *dev = encoder->base.dev;
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
970 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
971 u32 temp;
972
973 temp = I915_READ(intel_hdmi->hdmi_reg);
974
975 temp |= SDVO_ENABLE;
976 if (crtc->config->has_audio)
977 temp |= SDVO_AUDIO_ENABLE;
978
979 I915_WRITE(intel_hdmi->hdmi_reg, temp);
980 POSTING_READ(intel_hdmi->hdmi_reg);
981
982 if (crtc->config->has_audio)
983 intel_enable_hdmi_audio(encoder);
984 }
985
986 static void ibx_enable_hdmi(struct intel_encoder *encoder)
987 {
988 struct drm_device *dev = encoder->base.dev;
989 struct drm_i915_private *dev_priv = dev->dev_private;
990 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
991 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
992 u32 temp;
993
994 temp = I915_READ(intel_hdmi->hdmi_reg);
995
996 temp |= SDVO_ENABLE;
997 if (crtc->config->has_audio)
998 temp |= SDVO_AUDIO_ENABLE;
999
1000 /*
1001 * HW workaround, need to write this twice for issue
1002 * that may result in first write getting masked.
1003 */
1004 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1005 POSTING_READ(intel_hdmi->hdmi_reg);
1006 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1007 POSTING_READ(intel_hdmi->hdmi_reg);
1008
1009 /*
1010 * HW workaround, need to toggle enable bit off and on
1011 * for 12bpc with pixel repeat.
1012 *
1013 * FIXME: BSpec says this should be done at the end of
1014 * of the modeset sequence, so not sure if this isn't too soon.
1015 */
1016 if (crtc->config->pipe_bpp > 24 &&
1017 crtc->config->pixel_multiplier > 1) {
1018 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1019 POSTING_READ(intel_hdmi->hdmi_reg);
1020
1021 /*
1022 * HW workaround, need to write this twice for issue
1023 * that may result in first write getting masked.
1024 */
1025 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1026 POSTING_READ(intel_hdmi->hdmi_reg);
1027 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028 POSTING_READ(intel_hdmi->hdmi_reg);
1029 }
1030
1031 if (crtc->config->has_audio)
1032 intel_enable_hdmi_audio(encoder);
1033 }
1034
1035 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1036 {
1037 struct drm_device *dev = encoder->base.dev;
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1040 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1041 enum pipe pipe = crtc->pipe;
1042 u32 temp;
1043
1044 temp = I915_READ(intel_hdmi->hdmi_reg);
1045
1046 temp |= SDVO_ENABLE;
1047 if (crtc->config->has_audio)
1048 temp |= SDVO_AUDIO_ENABLE;
1049
1050 /*
1051 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1052 *
1053 * The procedure for 12bpc is as follows:
1054 * 1. disable HDMI clock gating
1055 * 2. enable HDMI with 8bpc
1056 * 3. enable HDMI with 12bpc
1057 * 4. enable HDMI clock gating
1058 */
1059
1060 if (crtc->config->pipe_bpp > 24) {
1061 I915_WRITE(TRANS_CHICKEN1(pipe),
1062 I915_READ(TRANS_CHICKEN1(pipe)) |
1063 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1064
1065 temp &= ~SDVO_COLOR_FORMAT_MASK;
1066 temp |= SDVO_COLOR_FORMAT_8bpc;
1067 }
1068
1069 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1070 POSTING_READ(intel_hdmi->hdmi_reg);
1071
1072 if (crtc->config->pipe_bpp > 24) {
1073 temp &= ~SDVO_COLOR_FORMAT_MASK;
1074 temp |= HDMI_COLOR_FORMAT_12bpc;
1075
1076 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1077 POSTING_READ(intel_hdmi->hdmi_reg);
1078
1079 I915_WRITE(TRANS_CHICKEN1(pipe),
1080 I915_READ(TRANS_CHICKEN1(pipe)) &
1081 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1082 }
1083
1084 if (crtc->config->has_audio)
1085 intel_enable_hdmi_audio(encoder);
1086 }
1087
1088 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1089 {
1090 }
1091
1092 static void intel_disable_hdmi(struct intel_encoder *encoder)
1093 {
1094 struct drm_device *dev = encoder->base.dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1097 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1098 u32 temp;
1099
1100 temp = I915_READ(intel_hdmi->hdmi_reg);
1101
1102 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1103 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1104 POSTING_READ(intel_hdmi->hdmi_reg);
1105
1106 /*
1107 * HW workaround for IBX, we need to move the port
1108 * to transcoder A after disabling it to allow the
1109 * matching DP port to be enabled on transcoder A.
1110 */
1111 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1112 temp &= ~SDVO_PIPE_B_SELECT;
1113 temp |= SDVO_ENABLE;
1114 /*
1115 * HW workaround, need to write this twice for issue
1116 * that may result in first write getting masked.
1117 */
1118 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1119 POSTING_READ(intel_hdmi->hdmi_reg);
1120 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1121 POSTING_READ(intel_hdmi->hdmi_reg);
1122
1123 temp &= ~SDVO_ENABLE;
1124 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1125 POSTING_READ(intel_hdmi->hdmi_reg);
1126 }
1127
1128 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1129 }
1130
1131 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1132 {
1133 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1134
1135 if (crtc->config->has_audio)
1136 intel_audio_codec_disable(encoder);
1137
1138 intel_disable_hdmi(encoder);
1139 }
1140
1141 static void pch_disable_hdmi(struct intel_encoder *encoder)
1142 {
1143 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1144
1145 if (crtc->config->has_audio)
1146 intel_audio_codec_disable(encoder);
1147 }
1148
1149 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1150 {
1151 intel_disable_hdmi(encoder);
1152 }
1153
1154 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1155 {
1156 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1157
1158 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1159 return 165000;
1160 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1161 return 300000;
1162 else
1163 return 225000;
1164 }
1165
1166 static enum drm_mode_status
1167 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1168 int clock, bool respect_dvi_limit)
1169 {
1170 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1171
1172 if (clock < 25000)
1173 return MODE_CLOCK_LOW;
1174 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1175 return MODE_CLOCK_HIGH;
1176
1177 /* BXT DPLL can't generate 223-240 MHz */
1178 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1179 return MODE_CLOCK_RANGE;
1180
1181 /* CHV DPLL can't generate 216-240 MHz */
1182 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1183 return MODE_CLOCK_RANGE;
1184
1185 return MODE_OK;
1186 }
1187
1188 static enum drm_mode_status
1189 intel_hdmi_mode_valid(struct drm_connector *connector,
1190 struct drm_display_mode *mode)
1191 {
1192 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1193 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1194 enum drm_mode_status status;
1195 int clock;
1196
1197 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1198 return MODE_NO_DBLESCAN;
1199
1200 clock = mode->clock;
1201 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1202 clock *= 2;
1203
1204 /* check if we can do 8bpc */
1205 status = hdmi_port_clock_valid(hdmi, clock, true);
1206
1207 /* if we can't do 8bpc we may still be able to do 12bpc */
1208 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1209 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1210
1211 return status;
1212 }
1213
1214 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1215 {
1216 struct drm_device *dev = crtc_state->base.crtc->dev;
1217 struct drm_atomic_state *state;
1218 struct intel_encoder *encoder;
1219 struct drm_connector *connector;
1220 struct drm_connector_state *connector_state;
1221 int count = 0, count_hdmi = 0;
1222 int i;
1223
1224 if (HAS_GMCH_DISPLAY(dev))
1225 return false;
1226
1227 state = crtc_state->base.state;
1228
1229 for_each_connector_in_state(state, connector, connector_state, i) {
1230 if (connector_state->crtc != crtc_state->base.crtc)
1231 continue;
1232
1233 encoder = to_intel_encoder(connector_state->best_encoder);
1234
1235 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1236 count++;
1237 }
1238
1239 /*
1240 * HDMI 12bpc affects the clocks, so it's only possible
1241 * when not cloning with other encoder types.
1242 */
1243 return count_hdmi > 0 && count_hdmi == count;
1244 }
1245
1246 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1247 struct intel_crtc_state *pipe_config)
1248 {
1249 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1250 struct drm_device *dev = encoder->base.dev;
1251 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1252 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1253 int clock_12bpc = clock_8bpc * 3 / 2;
1254 int desired_bpp;
1255
1256 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1257
1258 if (pipe_config->has_hdmi_sink)
1259 pipe_config->has_infoframe = true;
1260
1261 if (intel_hdmi->color_range_auto) {
1262 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1263 pipe_config->limited_color_range =
1264 pipe_config->has_hdmi_sink &&
1265 drm_match_cea_mode(adjusted_mode) > 1;
1266 } else {
1267 pipe_config->limited_color_range =
1268 intel_hdmi->limited_color_range;
1269 }
1270
1271 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1272 pipe_config->pixel_multiplier = 2;
1273 clock_8bpc *= 2;
1274 clock_12bpc *= 2;
1275 }
1276
1277 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1278 pipe_config->has_pch_encoder = true;
1279
1280 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1281 pipe_config->has_audio = true;
1282
1283 /*
1284 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1285 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1286 * outputs. We also need to check that the higher clock still fits
1287 * within limits.
1288 */
1289 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1290 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1291 hdmi_12bpc_possible(pipe_config)) {
1292 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1293 desired_bpp = 12*3;
1294
1295 /* Need to adjust the port link by 1.5x for 12bpc. */
1296 pipe_config->port_clock = clock_12bpc;
1297 } else {
1298 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1299 desired_bpp = 8*3;
1300
1301 pipe_config->port_clock = clock_8bpc;
1302 }
1303
1304 if (!pipe_config->bw_constrained) {
1305 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1306 pipe_config->pipe_bpp = desired_bpp;
1307 }
1308
1309 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1310 false) != MODE_OK) {
1311 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1312 return false;
1313 }
1314
1315 return true;
1316 }
1317
1318 static void
1319 intel_hdmi_unset_edid(struct drm_connector *connector)
1320 {
1321 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1322
1323 intel_hdmi->has_hdmi_sink = false;
1324 intel_hdmi->has_audio = false;
1325 intel_hdmi->rgb_quant_range_selectable = false;
1326
1327 kfree(to_intel_connector(connector)->detect_edid);
1328 to_intel_connector(connector)->detect_edid = NULL;
1329 }
1330
1331 static bool
1332 intel_hdmi_set_edid(struct drm_connector *connector)
1333 {
1334 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1335 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1336 struct intel_encoder *intel_encoder =
1337 &hdmi_to_dig_port(intel_hdmi)->base;
1338 enum intel_display_power_domain power_domain;
1339 struct edid *edid;
1340 bool connected = false;
1341
1342 power_domain = intel_display_port_power_domain(intel_encoder);
1343 intel_display_power_get(dev_priv, power_domain);
1344
1345 edid = drm_get_edid(connector,
1346 intel_gmbus_get_adapter(dev_priv,
1347 intel_hdmi->ddc_bus));
1348
1349 intel_display_power_put(dev_priv, power_domain);
1350
1351 to_intel_connector(connector)->detect_edid = edid;
1352 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1353 intel_hdmi->rgb_quant_range_selectable =
1354 drm_rgb_quant_range_selectable(edid);
1355
1356 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1357 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1358 intel_hdmi->has_audio =
1359 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1360
1361 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1362 intel_hdmi->has_hdmi_sink =
1363 drm_detect_hdmi_monitor(edid);
1364
1365 connected = true;
1366 }
1367
1368 return connected;
1369 }
1370
1371 static enum drm_connector_status
1372 intel_hdmi_detect(struct drm_connector *connector, bool force)
1373 {
1374 enum drm_connector_status status;
1375
1376 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1377 connector->base.id, connector->name);
1378
1379 intel_hdmi_unset_edid(connector);
1380
1381 if (intel_hdmi_set_edid(connector)) {
1382 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1383
1384 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1385 status = connector_status_connected;
1386 } else
1387 status = connector_status_disconnected;
1388
1389 return status;
1390 }
1391
1392 static void
1393 intel_hdmi_force(struct drm_connector *connector)
1394 {
1395 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1396
1397 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1398 connector->base.id, connector->name);
1399
1400 intel_hdmi_unset_edid(connector);
1401
1402 if (connector->status != connector_status_connected)
1403 return;
1404
1405 intel_hdmi_set_edid(connector);
1406 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1407 }
1408
1409 static int intel_hdmi_get_modes(struct drm_connector *connector)
1410 {
1411 struct edid *edid;
1412
1413 edid = to_intel_connector(connector)->detect_edid;
1414 if (edid == NULL)
1415 return 0;
1416
1417 return intel_connector_update_modes(connector, edid);
1418 }
1419
1420 static bool
1421 intel_hdmi_detect_audio(struct drm_connector *connector)
1422 {
1423 bool has_audio = false;
1424 struct edid *edid;
1425
1426 edid = to_intel_connector(connector)->detect_edid;
1427 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1428 has_audio = drm_detect_monitor_audio(edid);
1429
1430 return has_audio;
1431 }
1432
1433 static int
1434 intel_hdmi_set_property(struct drm_connector *connector,
1435 struct drm_property *property,
1436 uint64_t val)
1437 {
1438 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1439 struct intel_digital_port *intel_dig_port =
1440 hdmi_to_dig_port(intel_hdmi);
1441 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1442 int ret;
1443
1444 ret = drm_object_property_set_value(&connector->base, property, val);
1445 if (ret)
1446 return ret;
1447
1448 if (property == dev_priv->force_audio_property) {
1449 enum hdmi_force_audio i = val;
1450 bool has_audio;
1451
1452 if (i == intel_hdmi->force_audio)
1453 return 0;
1454
1455 intel_hdmi->force_audio = i;
1456
1457 if (i == HDMI_AUDIO_AUTO)
1458 has_audio = intel_hdmi_detect_audio(connector);
1459 else
1460 has_audio = (i == HDMI_AUDIO_ON);
1461
1462 if (i == HDMI_AUDIO_OFF_DVI)
1463 intel_hdmi->has_hdmi_sink = 0;
1464
1465 intel_hdmi->has_audio = has_audio;
1466 goto done;
1467 }
1468
1469 if (property == dev_priv->broadcast_rgb_property) {
1470 bool old_auto = intel_hdmi->color_range_auto;
1471 bool old_range = intel_hdmi->limited_color_range;
1472
1473 switch (val) {
1474 case INTEL_BROADCAST_RGB_AUTO:
1475 intel_hdmi->color_range_auto = true;
1476 break;
1477 case INTEL_BROADCAST_RGB_FULL:
1478 intel_hdmi->color_range_auto = false;
1479 intel_hdmi->limited_color_range = false;
1480 break;
1481 case INTEL_BROADCAST_RGB_LIMITED:
1482 intel_hdmi->color_range_auto = false;
1483 intel_hdmi->limited_color_range = true;
1484 break;
1485 default:
1486 return -EINVAL;
1487 }
1488
1489 if (old_auto == intel_hdmi->color_range_auto &&
1490 old_range == intel_hdmi->limited_color_range)
1491 return 0;
1492
1493 goto done;
1494 }
1495
1496 if (property == connector->dev->mode_config.aspect_ratio_property) {
1497 switch (val) {
1498 case DRM_MODE_PICTURE_ASPECT_NONE:
1499 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1500 break;
1501 case DRM_MODE_PICTURE_ASPECT_4_3:
1502 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1503 break;
1504 case DRM_MODE_PICTURE_ASPECT_16_9:
1505 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1506 break;
1507 default:
1508 return -EINVAL;
1509 }
1510 goto done;
1511 }
1512
1513 return -EINVAL;
1514
1515 done:
1516 if (intel_dig_port->base.base.crtc)
1517 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1518
1519 return 0;
1520 }
1521
1522 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1523 {
1524 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1525 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1526 struct drm_display_mode *adjusted_mode =
1527 &intel_crtc->config->base.adjusted_mode;
1528
1529 intel_hdmi_prepare(encoder);
1530
1531 intel_hdmi->set_infoframes(&encoder->base,
1532 intel_crtc->config->has_hdmi_sink,
1533 adjusted_mode);
1534 }
1535
1536 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1537 {
1538 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1539 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1540 struct drm_device *dev = encoder->base.dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct intel_crtc *intel_crtc =
1543 to_intel_crtc(encoder->base.crtc);
1544 struct drm_display_mode *adjusted_mode =
1545 &intel_crtc->config->base.adjusted_mode;
1546 enum dpio_channel port = vlv_dport_to_channel(dport);
1547 int pipe = intel_crtc->pipe;
1548 u32 val;
1549
1550 /* Enable clock channels for this port */
1551 mutex_lock(&dev_priv->sb_lock);
1552 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1553 val = 0;
1554 if (pipe)
1555 val |= (1<<21);
1556 else
1557 val &= ~(1<<21);
1558 val |= 0x001000c4;
1559 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1560
1561 /* HDMI 1.0V-2dB */
1562 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1563 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1564 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1565 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1566 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1567 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1568 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1569 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1570
1571 /* Program lane clock */
1572 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1573 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1574 mutex_unlock(&dev_priv->sb_lock);
1575
1576 intel_hdmi->set_infoframes(&encoder->base,
1577 intel_crtc->config->has_hdmi_sink,
1578 adjusted_mode);
1579
1580 g4x_enable_hdmi(encoder);
1581
1582 vlv_wait_port_ready(dev_priv, dport, 0x0);
1583 }
1584
1585 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1586 {
1587 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1588 struct drm_device *dev = encoder->base.dev;
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 struct intel_crtc *intel_crtc =
1591 to_intel_crtc(encoder->base.crtc);
1592 enum dpio_channel port = vlv_dport_to_channel(dport);
1593 int pipe = intel_crtc->pipe;
1594
1595 intel_hdmi_prepare(encoder);
1596
1597 /* Program Tx lane resets to default */
1598 mutex_lock(&dev_priv->sb_lock);
1599 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1600 DPIO_PCS_TX_LANE2_RESET |
1601 DPIO_PCS_TX_LANE1_RESET);
1602 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1603 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1604 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1605 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1606 DPIO_PCS_CLK_SOFT_RESET);
1607
1608 /* Fix up inter-pair skew failure */
1609 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1610 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1611 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1612
1613 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1614 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1615 mutex_unlock(&dev_priv->sb_lock);
1616 }
1617
1618 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1619 {
1620 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1621 struct drm_device *dev = encoder->base.dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623 struct intel_crtc *intel_crtc =
1624 to_intel_crtc(encoder->base.crtc);
1625 enum dpio_channel ch = vlv_dport_to_channel(dport);
1626 enum pipe pipe = intel_crtc->pipe;
1627 u32 val;
1628
1629 intel_hdmi_prepare(encoder);
1630
1631 chv_phy_powergate_lanes(encoder, true, 0x0);
1632
1633 mutex_lock(&dev_priv->sb_lock);
1634
1635 /* program left/right clock distribution */
1636 if (pipe != PIPE_B) {
1637 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1638 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1639 if (ch == DPIO_CH0)
1640 val |= CHV_BUFLEFTENA1_FORCE;
1641 if (ch == DPIO_CH1)
1642 val |= CHV_BUFRIGHTENA1_FORCE;
1643 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1644 } else {
1645 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1646 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1647 if (ch == DPIO_CH0)
1648 val |= CHV_BUFLEFTENA2_FORCE;
1649 if (ch == DPIO_CH1)
1650 val |= CHV_BUFRIGHTENA2_FORCE;
1651 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1652 }
1653
1654 /* program clock channel usage */
1655 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1656 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1657 if (pipe != PIPE_B)
1658 val &= ~CHV_PCS_USEDCLKCHANNEL;
1659 else
1660 val |= CHV_PCS_USEDCLKCHANNEL;
1661 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1662
1663 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1664 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1665 if (pipe != PIPE_B)
1666 val &= ~CHV_PCS_USEDCLKCHANNEL;
1667 else
1668 val |= CHV_PCS_USEDCLKCHANNEL;
1669 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1670
1671 /*
1672 * This a a bit weird since generally CL
1673 * matches the pipe, but here we need to
1674 * pick the CL based on the port.
1675 */
1676 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1677 if (pipe != PIPE_B)
1678 val &= ~CHV_CMN_USEDCLKCHANNEL;
1679 else
1680 val |= CHV_CMN_USEDCLKCHANNEL;
1681 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1682
1683 mutex_unlock(&dev_priv->sb_lock);
1684 }
1685
1686 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1687 {
1688 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1689 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1690 u32 val;
1691
1692 mutex_lock(&dev_priv->sb_lock);
1693
1694 /* disable left/right clock distribution */
1695 if (pipe != PIPE_B) {
1696 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1697 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1698 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1699 } else {
1700 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1701 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1702 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1703 }
1704
1705 mutex_unlock(&dev_priv->sb_lock);
1706
1707 chv_phy_powergate_lanes(encoder, false, 0x0);
1708 }
1709
1710 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1711 {
1712 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1713 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1714 struct intel_crtc *intel_crtc =
1715 to_intel_crtc(encoder->base.crtc);
1716 enum dpio_channel port = vlv_dport_to_channel(dport);
1717 int pipe = intel_crtc->pipe;
1718
1719 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1720 mutex_lock(&dev_priv->sb_lock);
1721 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1722 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1723 mutex_unlock(&dev_priv->sb_lock);
1724 }
1725
1726 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1727 {
1728 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1729 struct drm_device *dev = encoder->base.dev;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731 struct intel_crtc *intel_crtc =
1732 to_intel_crtc(encoder->base.crtc);
1733 enum dpio_channel ch = vlv_dport_to_channel(dport);
1734 enum pipe pipe = intel_crtc->pipe;
1735 u32 val;
1736
1737 mutex_lock(&dev_priv->sb_lock);
1738
1739 /* Propagate soft reset to data lane reset */
1740 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1741 val |= CHV_PCS_REQ_SOFTRESET_EN;
1742 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1743
1744 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1745 val |= CHV_PCS_REQ_SOFTRESET_EN;
1746 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1747
1748 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1749 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1750 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1751
1752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1753 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1754 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1755
1756 mutex_unlock(&dev_priv->sb_lock);
1757 }
1758
1759 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1760 {
1761 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1762 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1763 struct drm_device *dev = encoder->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 struct intel_crtc *intel_crtc =
1766 to_intel_crtc(encoder->base.crtc);
1767 struct drm_display_mode *adjusted_mode =
1768 &intel_crtc->config->base.adjusted_mode;
1769 enum dpio_channel ch = vlv_dport_to_channel(dport);
1770 int pipe = intel_crtc->pipe;
1771 int data, i, stagger;
1772 u32 val;
1773
1774 mutex_lock(&dev_priv->sb_lock);
1775
1776 /* allow hardware to manage TX FIFO reset source */
1777 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1778 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1779 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1780
1781 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1782 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1783 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1784
1785 /* Deassert soft data lane reset*/
1786 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1787 val |= CHV_PCS_REQ_SOFTRESET_EN;
1788 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1789
1790 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1791 val |= CHV_PCS_REQ_SOFTRESET_EN;
1792 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1793
1794 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1795 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1796 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1797
1798 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1799 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1800 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1801
1802 /* Program Tx latency optimal setting */
1803 for (i = 0; i < 4; i++) {
1804 /* Set the upar bit */
1805 data = (i == 1) ? 0x0 : 0x1;
1806 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1807 data << DPIO_UPAR_SHIFT);
1808 }
1809
1810 /* Data lane stagger programming */
1811 if (intel_crtc->config->port_clock > 270000)
1812 stagger = 0x18;
1813 else if (intel_crtc->config->port_clock > 135000)
1814 stagger = 0xd;
1815 else if (intel_crtc->config->port_clock > 67500)
1816 stagger = 0x7;
1817 else if (intel_crtc->config->port_clock > 33750)
1818 stagger = 0x4;
1819 else
1820 stagger = 0x2;
1821
1822 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1823 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1824 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1825
1826 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1827 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1828 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1829
1830 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1831 DPIO_LANESTAGGER_STRAP(stagger) |
1832 DPIO_LANESTAGGER_STRAP_OVRD |
1833 DPIO_TX1_STAGGER_MASK(0x1f) |
1834 DPIO_TX1_STAGGER_MULT(6) |
1835 DPIO_TX2_STAGGER_MULT(0));
1836
1837 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1838 DPIO_LANESTAGGER_STRAP(stagger) |
1839 DPIO_LANESTAGGER_STRAP_OVRD |
1840 DPIO_TX1_STAGGER_MASK(0x1f) |
1841 DPIO_TX1_STAGGER_MULT(7) |
1842 DPIO_TX2_STAGGER_MULT(5));
1843
1844 /* Clear calc init */
1845 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1846 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1847 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1848 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1849 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1850
1851 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1852 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1853 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1854 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1855 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1856
1857 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1858 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1859 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1860 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1861
1862 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1863 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1864 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1865 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1866
1867 /* FIXME: Program the support xxx V-dB */
1868 /* Use 800mV-0dB */
1869 for (i = 0; i < 4; i++) {
1870 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1871 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1872 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1873 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1874 }
1875
1876 for (i = 0; i < 4; i++) {
1877 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1878
1879 val &= ~DPIO_SWING_MARGIN000_MASK;
1880 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1881
1882 /*
1883 * Supposedly this value shouldn't matter when unique transition
1884 * scale is disabled, but in fact it does matter. Let's just
1885 * always program the same value and hope it's OK.
1886 */
1887 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1888 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1889
1890 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1891 }
1892
1893 /*
1894 * The document said it needs to set bit 27 for ch0 and bit 26
1895 * for ch1. Might be a typo in the doc.
1896 * For now, for this unique transition scale selection, set bit
1897 * 27 for ch0 and ch1.
1898 */
1899 for (i = 0; i < 4; i++) {
1900 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1901 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1902 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1903 }
1904
1905 /* Start swing calculation */
1906 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1907 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1908 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1909
1910 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1911 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1912 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1913
1914 /* LRC Bypass */
1915 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1916 val |= DPIO_LRC_BYPASS;
1917 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1918
1919 mutex_unlock(&dev_priv->sb_lock);
1920
1921 intel_hdmi->set_infoframes(&encoder->base,
1922 intel_crtc->config->has_hdmi_sink,
1923 adjusted_mode);
1924
1925 g4x_enable_hdmi(encoder);
1926
1927 vlv_wait_port_ready(dev_priv, dport, 0x0);
1928 }
1929
1930 static void intel_hdmi_destroy(struct drm_connector *connector)
1931 {
1932 kfree(to_intel_connector(connector)->detect_edid);
1933 drm_connector_cleanup(connector);
1934 kfree(connector);
1935 }
1936
1937 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1938 .dpms = drm_atomic_helper_connector_dpms,
1939 .detect = intel_hdmi_detect,
1940 .force = intel_hdmi_force,
1941 .fill_modes = drm_helper_probe_single_connector_modes,
1942 .set_property = intel_hdmi_set_property,
1943 .atomic_get_property = intel_connector_atomic_get_property,
1944 .destroy = intel_hdmi_destroy,
1945 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1946 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1947 };
1948
1949 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1950 .get_modes = intel_hdmi_get_modes,
1951 .mode_valid = intel_hdmi_mode_valid,
1952 .best_encoder = intel_best_encoder,
1953 };
1954
1955 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1956 .destroy = intel_encoder_destroy,
1957 };
1958
1959 static void
1960 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1961 {
1962 if (!drm_mode_create_aspect_ratio_property(connector->dev))
1963 drm_object_attach_property(&connector->base,
1964 connector->dev->mode_config.aspect_ratio_property,
1965 DRM_MODE_PICTURE_ASPECT_NONE);
1966 }
1967
1968 static void
1969 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1970 {
1971 intel_attach_force_audio_property(connector);
1972 intel_attach_broadcast_rgb_property(connector);
1973 intel_hdmi->color_range_auto = true;
1974 intel_attach_aspect_ratio_property(connector);
1975 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1976 }
1977
1978 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1979 struct intel_connector *intel_connector)
1980 {
1981 struct drm_connector *connector = &intel_connector->base;
1982 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1983 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1984 struct drm_device *dev = intel_encoder->base.dev;
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986 enum port port = intel_dig_port->port;
1987
1988 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1989 DRM_MODE_CONNECTOR_HDMIA);
1990 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1991
1992 connector->interlace_allowed = 1;
1993 connector->doublescan_allowed = 0;
1994 connector->stereo_allowed = 1;
1995
1996 switch (port) {
1997 case PORT_B:
1998 if (IS_BROXTON(dev_priv))
1999 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2000 else
2001 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2002 /*
2003 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2004 * interrupts to check the external panel connection.
2005 */
2006 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
2007 intel_encoder->hpd_pin = HPD_PORT_A;
2008 else
2009 intel_encoder->hpd_pin = HPD_PORT_B;
2010 break;
2011 case PORT_C:
2012 if (IS_BROXTON(dev_priv))
2013 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2014 else
2015 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2016 intel_encoder->hpd_pin = HPD_PORT_C;
2017 break;
2018 case PORT_D:
2019 if (WARN_ON(IS_BROXTON(dev_priv)))
2020 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2021 else if (IS_CHERRYVIEW(dev_priv))
2022 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2023 else
2024 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2025 intel_encoder->hpd_pin = HPD_PORT_D;
2026 break;
2027 case PORT_A:
2028 intel_encoder->hpd_pin = HPD_PORT_A;
2029 /* Internal port only for eDP. */
2030 default:
2031 BUG();
2032 }
2033
2034 if (IS_VALLEYVIEW(dev)) {
2035 intel_hdmi->write_infoframe = vlv_write_infoframe;
2036 intel_hdmi->set_infoframes = vlv_set_infoframes;
2037 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2038 } else if (IS_G4X(dev)) {
2039 intel_hdmi->write_infoframe = g4x_write_infoframe;
2040 intel_hdmi->set_infoframes = g4x_set_infoframes;
2041 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2042 } else if (HAS_DDI(dev)) {
2043 intel_hdmi->write_infoframe = hsw_write_infoframe;
2044 intel_hdmi->set_infoframes = hsw_set_infoframes;
2045 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2046 } else if (HAS_PCH_IBX(dev)) {
2047 intel_hdmi->write_infoframe = ibx_write_infoframe;
2048 intel_hdmi->set_infoframes = ibx_set_infoframes;
2049 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2050 } else {
2051 intel_hdmi->write_infoframe = cpt_write_infoframe;
2052 intel_hdmi->set_infoframes = cpt_set_infoframes;
2053 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2054 }
2055
2056 if (HAS_DDI(dev))
2057 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2058 else
2059 intel_connector->get_hw_state = intel_connector_get_hw_state;
2060 intel_connector->unregister = intel_connector_unregister;
2061
2062 intel_hdmi_add_properties(intel_hdmi, connector);
2063
2064 intel_connector_attach_encoder(intel_connector, intel_encoder);
2065 drm_connector_register(connector);
2066
2067 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2068 * 0xd. Failure to do so will result in spurious interrupts being
2069 * generated on the port when a cable is not attached.
2070 */
2071 if (IS_G4X(dev) && !IS_GM45(dev)) {
2072 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2073 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2074 }
2075 }
2076
2077 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
2078 {
2079 struct intel_digital_port *intel_dig_port;
2080 struct intel_encoder *intel_encoder;
2081 struct intel_connector *intel_connector;
2082
2083 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2084 if (!intel_dig_port)
2085 return;
2086
2087 intel_connector = intel_connector_alloc();
2088 if (!intel_connector) {
2089 kfree(intel_dig_port);
2090 return;
2091 }
2092
2093 intel_encoder = &intel_dig_port->base;
2094
2095 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2096 DRM_MODE_ENCODER_TMDS);
2097
2098 intel_encoder->compute_config = intel_hdmi_compute_config;
2099 if (HAS_PCH_SPLIT(dev)) {
2100 intel_encoder->disable = pch_disable_hdmi;
2101 intel_encoder->post_disable = pch_post_disable_hdmi;
2102 } else {
2103 intel_encoder->disable = g4x_disable_hdmi;
2104 }
2105 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2106 intel_encoder->get_config = intel_hdmi_get_config;
2107 if (IS_CHERRYVIEW(dev)) {
2108 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2109 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2110 intel_encoder->enable = vlv_enable_hdmi;
2111 intel_encoder->post_disable = chv_hdmi_post_disable;
2112 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2113 } else if (IS_VALLEYVIEW(dev)) {
2114 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2115 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2116 intel_encoder->enable = vlv_enable_hdmi;
2117 intel_encoder->post_disable = vlv_hdmi_post_disable;
2118 } else {
2119 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2120 if (HAS_PCH_CPT(dev))
2121 intel_encoder->enable = cpt_enable_hdmi;
2122 else if (HAS_PCH_IBX(dev))
2123 intel_encoder->enable = ibx_enable_hdmi;
2124 else
2125 intel_encoder->enable = g4x_enable_hdmi;
2126 }
2127
2128 intel_encoder->type = INTEL_OUTPUT_HDMI;
2129 if (IS_CHERRYVIEW(dev)) {
2130 if (port == PORT_D)
2131 intel_encoder->crtc_mask = 1 << 2;
2132 else
2133 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2134 } else {
2135 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2136 }
2137 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2138 /*
2139 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2140 * to work on real hardware. And since g4x can send infoframes to
2141 * only one port anyway, nothing is lost by allowing it.
2142 */
2143 if (IS_G4X(dev))
2144 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2145
2146 intel_dig_port->port = port;
2147 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2148 intel_dig_port->dp.output_reg = 0;
2149
2150 intel_hdmi_init_connector(intel_dig_port, intel_connector);
2151 }
Linux kernel - Deliverables
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