drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41 {
  42         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43 }
  44
  45 static void
  46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47 {
  48         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         uint32_t enabled_bits;
  51
  52         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53
  54         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55              "HDMI port enabled, expecting disabled\n");
  56 }
  57
  58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59 {
  60         struct intel_digital_port *intel_dig_port =
  61                 container_of(encoder, struct intel_digital_port, base.base);
  62         return &intel_dig_port->hdmi;
  63 }
  64
  65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66 {
  67         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68 }
  69
  70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71 {
  72         switch (type) {
  73         case HDMI_INFOFRAME_TYPE_AVI:
  74                 return VIDEO_DIP_SELECT_AVI;
  75         case HDMI_INFOFRAME_TYPE_SPD:
  76                 return VIDEO_DIP_SELECT_SPD;
  77         case HDMI_INFOFRAME_TYPE_VENDOR:
  78                 return VIDEO_DIP_SELECT_VENDOR;
  79         default:
  80                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  81                 return 0;
  82         }
  83 }
  84
  85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  86 {
  87         switch (type) {
  88         case HDMI_INFOFRAME_TYPE_AVI:
  89                 return VIDEO_DIP_ENABLE_AVI;
  90         case HDMI_INFOFRAME_TYPE_SPD:
  91                 return VIDEO_DIP_ENABLE_SPD;
  92         case HDMI_INFOFRAME_TYPE_VENDOR:
  93                 return VIDEO_DIP_ENABLE_VENDOR;
  94         default:
  95                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  96                 return 0;
  97         }
  98 }
  99
 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 101 {
 102         switch (type) {
 103         case HDMI_INFOFRAME_TYPE_AVI:
 104                 return VIDEO_DIP_ENABLE_AVI_HSW;
 105         case HDMI_INFOFRAME_TYPE_SPD:
 106                 return VIDEO_DIP_ENABLE_SPD_HSW;
 107         case HDMI_INFOFRAME_TYPE_VENDOR:
 108                 return VIDEO_DIP_ENABLE_VS_HSW;
 109         default:
 110                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 111                 return 0;
 112         }
 113 }
 114
 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 116                                   enum transcoder cpu_transcoder,
 117                                   struct drm_i915_private *dev_priv)
 118 {
 119         switch (type) {
 120         case HDMI_INFOFRAME_TYPE_AVI:
 121                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 122         case HDMI_INFOFRAME_TYPE_SPD:
 123                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 124         case HDMI_INFOFRAME_TYPE_VENDOR:
 125                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 126         default:
 127                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 128                 return 0;
 129         }
 130 }
 131
 132 static void g4x_write_infoframe(struct drm_encoder *encoder,
 133                                 enum hdmi_infoframe_type type,
 134                                 const void *frame, ssize_t len)
 135 {
 136         const uint32_t *data = frame;
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         u32 val = I915_READ(VIDEO_DIP_CTL);
 140         int i;
 141
 142         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 143
 144         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 145         val |= g4x_infoframe_index(type);
 146
 147         val &= ~g4x_infoframe_enable(type);
 148
 149         I915_WRITE(VIDEO_DIP_CTL, val);
 150
 151         mmiowb();
 152         for (i = 0; i < len; i += 4) {
 153                 I915_WRITE(VIDEO_DIP_DATA, *data);
 154                 data++;
 155         }
 156         /* Write every possible data byte to force correct ECC calculation. */
 157         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 158                 I915_WRITE(VIDEO_DIP_DATA, 0);
 159         mmiowb();
 160
 161         val |= g4x_infoframe_enable(type);
 162         val &= ~VIDEO_DIP_FREQ_MASK;
 163         val |= VIDEO_DIP_FREQ_VSYNC;
 164
 165         I915_WRITE(VIDEO_DIP_CTL, val);
 166         POSTING_READ(VIDEO_DIP_CTL);
 167 }
 168
 169 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
 170 {
 171         struct drm_device *dev = encoder->dev;
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         u32 val = I915_READ(VIDEO_DIP_CTL);
 174
 175         return val & VIDEO_DIP_ENABLE;
 176 }
 177
 178 static void ibx_write_infoframe(struct drm_encoder *encoder,
 179                                 enum hdmi_infoframe_type type,
 180                                 const void *frame, ssize_t len)
 181 {
 182         const uint32_t *data = frame;
 183         struct drm_device *dev = encoder->dev;
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 186         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 187         u32 val = I915_READ(reg);
 188
 189         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 190
 191         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 192         val |= g4x_infoframe_index(type);
 193
 194         val &= ~g4x_infoframe_enable(type);
 195
 196         I915_WRITE(reg, val);
 197
 198         mmiowb();
 199         for (i = 0; i < len; i += 4) {
 200                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 201                 data++;
 202         }
 203         /* Write every possible data byte to force correct ECC calculation. */
 204         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 205                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 206         mmiowb();
 207
 208         val |= g4x_infoframe_enable(type);
 209         val &= ~VIDEO_DIP_FREQ_MASK;
 210         val |= VIDEO_DIP_FREQ_VSYNC;
 211
 212         I915_WRITE(reg, val);
 213         POSTING_READ(reg);
 214 }
 215
 216 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 221         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 222         u32 val = I915_READ(reg);
 223
 224         return val & VIDEO_DIP_ENABLE;
 225 }
 226
 227 static void cpt_write_infoframe(struct drm_encoder *encoder,
 228                                 enum hdmi_infoframe_type type,
 229                                 const void *frame, ssize_t len)
 230 {
 231         const uint32_t *data = frame;
 232         struct drm_device *dev = encoder->dev;
 233         struct drm_i915_private *dev_priv = dev->dev_private;
 234         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 235         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 236         u32 val = I915_READ(reg);
 237
 238         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 239
 240         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 241         val |= g4x_infoframe_index(type);
 242
 243         /* The DIP control register spec says that we need to update the AVI
 244          * infoframe without clearing its enable bit */
 245         if (type != HDMI_INFOFRAME_TYPE_AVI)
 246                 val &= ~g4x_infoframe_enable(type);
 247
 248         I915_WRITE(reg, val);
 249
 250         mmiowb();
 251         for (i = 0; i < len; i += 4) {
 252                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 253                 data++;
 254         }
 255         /* Write every possible data byte to force correct ECC calculation. */
 256         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 257                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 258         mmiowb();
 259
 260         val |= g4x_infoframe_enable(type);
 261         val &= ~VIDEO_DIP_FREQ_MASK;
 262         val |= VIDEO_DIP_FREQ_VSYNC;
 263
 264         I915_WRITE(reg, val);
 265         POSTING_READ(reg);
 266 }
 267
 268 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 269 {
 270         struct drm_device *dev = encoder->dev;
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 273         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 274         u32 val = I915_READ(reg);
 275
 276         return val & VIDEO_DIP_ENABLE;
 277 }
 278
 279 static void vlv_write_infoframe(struct drm_encoder *encoder,
 280                                 enum hdmi_infoframe_type type,
 281                                 const void *frame, ssize_t len)
 282 {
 283         const uint32_t *data = frame;
 284         struct drm_device *dev = encoder->dev;
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 287         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 288         u32 val = I915_READ(reg);
 289
 290         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 291
 292         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 293         val |= g4x_infoframe_index(type);
 294
 295         val &= ~g4x_infoframe_enable(type);
 296
 297         I915_WRITE(reg, val);
 298
 299         mmiowb();
 300         for (i = 0; i < len; i += 4) {
 301                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 302                 data++;
 303         }
 304         /* Write every possible data byte to force correct ECC calculation. */
 305         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 306                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 307         mmiowb();
 308
 309         val |= g4x_infoframe_enable(type);
 310         val &= ~VIDEO_DIP_FREQ_MASK;
 311         val |= VIDEO_DIP_FREQ_VSYNC;
 312
 313         I915_WRITE(reg, val);
 314         POSTING_READ(reg);
 315 }
 316
 317 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 318 {
 319         struct drm_device *dev = encoder->dev;
 320         struct drm_i915_private *dev_priv = dev->dev_private;
 321         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 322         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 323         u32 val = I915_READ(reg);
 324
 325         return val & VIDEO_DIP_ENABLE;
 326 }
 327
 328 static void hsw_write_infoframe(struct drm_encoder *encoder,
 329                                 enum hdmi_infoframe_type type,
 330                                 const void *frame, ssize_t len)
 331 {
 332         const uint32_t *data = frame;
 333         struct drm_device *dev = encoder->dev;
 334         struct drm_i915_private *dev_priv = dev->dev_private;
 335         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 336         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 337         u32 data_reg;
 338         int i;
 339         u32 val = I915_READ(ctl_reg);
 340
 341         data_reg = hsw_infoframe_data_reg(type,
 342                                           intel_crtc->config.cpu_transcoder,
 343                                           dev_priv);
 344         if (data_reg == 0)
 345                 return;
 346
 347         val &= ~hsw_infoframe_enable(type);
 348         I915_WRITE(ctl_reg, val);
 349
 350         mmiowb();
 351         for (i = 0; i < len; i += 4) {
 352                 I915_WRITE(data_reg + i, *data);
 353                 data++;
 354         }
 355         /* Write every possible data byte to force correct ECC calculation. */
 356         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 357                 I915_WRITE(data_reg + i, 0);
 358         mmiowb();
 359
 360         val |= hsw_infoframe_enable(type);
 361         I915_WRITE(ctl_reg, val);
 362         POSTING_READ(ctl_reg);
 363 }
 364
 365 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 366 {
 367         struct drm_device *dev = encoder->dev;
 368         struct drm_i915_private *dev_priv = dev->dev_private;
 369         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 370         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 371         u32 val = I915_READ(ctl_reg);
 372
 373         return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
 374                       VIDEO_DIP_ENABLE_VS_HSW);
 375 }
 376
 377 /*
 378  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 379  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 380  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 381  * used for both technologies.
 382  *
 383  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 384  * DW1:       DB3       | DB2 | DB1 | DB0
 385  * DW2:       DB7       | DB6 | DB5 | DB4
 386  * DW3: ...
 387  *
 388  * (HB is Header Byte, DB is Data Byte)
 389  *
 390  * The hdmi pack() functions don't know about that hardware specific hole so we
 391  * trick them by giving an offset into the buffer and moving back the header
 392  * bytes by one.
 393  */
 394 static void intel_write_infoframe(struct drm_encoder *encoder,
 395                                   union hdmi_infoframe *frame)
 396 {
 397         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 398         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 399         ssize_t len;
 400
 401         /* see comment above for the reason for this offset */
 402         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 403         if (len < 0)
 404                 return;
 405
 406         /* Insert the 'hole' (see big comment above) at position 3 */
 407         buffer[0] = buffer[1];
 408         buffer[1] = buffer[2];
 409         buffer[2] = buffer[3];
 410         buffer[3] = 0;
 411         len++;
 412
 413         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 414 }
 415
 416 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 417                                          struct drm_display_mode *adjusted_mode)
 418 {
 419         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 420         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 421         union hdmi_infoframe frame;
 422         int ret;
 423
 424         /* Set user selected PAR to incoming mode's member */
 425         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 426
 427         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 428                                                        adjusted_mode);
 429         if (ret < 0) {
 430                 DRM_ERROR("couldn't fill AVI infoframe\n");
 431                 return;
 432         }
 433
 434         if (intel_hdmi->rgb_quant_range_selectable) {
 435                 if (intel_crtc->config.limited_color_range)
 436                         frame.avi.quantization_range =
 437                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 438                 else
 439                         frame.avi.quantization_range =
 440                                 HDMI_QUANTIZATION_RANGE_FULL;
 441         }
 442
 443         intel_write_infoframe(encoder, &frame);
 444 }
 445
 446 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 447 {
 448         union hdmi_infoframe frame;
 449         int ret;
 450
 451         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 452         if (ret < 0) {
 453                 DRM_ERROR("couldn't fill SPD infoframe\n");
 454                 return;
 455         }
 456
 457         frame.spd.sdi = HDMI_SPD_SDI_PC;
 458
 459         intel_write_infoframe(encoder, &frame);
 460 }
 461
 462 static void
 463 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 464                               struct drm_display_mode *adjusted_mode)
 465 {
 466         union hdmi_infoframe frame;
 467         int ret;
 468
 469         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 470                                                           adjusted_mode);
 471         if (ret < 0)
 472                 return;
 473
 474         intel_write_infoframe(encoder, &frame);
 475 }
 476
 477 static void g4x_set_infoframes(struct drm_encoder *encoder,
 478                                bool enable,
 479                                struct drm_display_mode *adjusted_mode)
 480 {
 481         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 482         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 483         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 484         u32 reg = VIDEO_DIP_CTL;
 485         u32 val = I915_READ(reg);
 486         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 487
 488         assert_hdmi_port_disabled(intel_hdmi);
 489
 490         /* If the registers were not initialized yet, they might be zeroes,
 491          * which means we're selecting the AVI DIP and we're setting its
 492          * frequency to once. This seems to really confuse the HW and make
 493          * things stop working (the register spec says the AVI always needs to
 494          * be sent every VSync). So here we avoid writing to the register more
 495          * than we need and also explicitly select the AVI DIP and explicitly
 496          * set its frequency to every VSync. Avoiding to write it twice seems to
 497          * be enough to solve the problem, but being defensive shouldn't hurt us
 498          * either. */
 499         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 500
 501         if (!enable) {
 502                 if (!(val & VIDEO_DIP_ENABLE))
 503                         return;
 504                 val &= ~VIDEO_DIP_ENABLE;
 505                 I915_WRITE(reg, val);
 506                 POSTING_READ(reg);
 507                 return;
 508         }
 509
 510         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 511                 if (val & VIDEO_DIP_ENABLE) {
 512                         val &= ~VIDEO_DIP_ENABLE;
 513                         I915_WRITE(reg, val);
 514                         POSTING_READ(reg);
 515                 }
 516                 val &= ~VIDEO_DIP_PORT_MASK;
 517                 val |= port;
 518         }
 519
 520         val |= VIDEO_DIP_ENABLE;
 521         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 522
 523         I915_WRITE(reg, val);
 524         POSTING_READ(reg);
 525
 526         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 527         intel_hdmi_set_spd_infoframe(encoder);
 528         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 529 }
 530
 531 static void ibx_set_infoframes(struct drm_encoder *encoder,
 532                                bool enable,
 533                                struct drm_display_mode *adjusted_mode)
 534 {
 535         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 536         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 537         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 538         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 539         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 540         u32 val = I915_READ(reg);
 541         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 542
 543         assert_hdmi_port_disabled(intel_hdmi);
 544
 545         /* See the big comment in g4x_set_infoframes() */
 546         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 547
 548         if (!enable) {
 549                 if (!(val & VIDEO_DIP_ENABLE))
 550                         return;
 551                 val &= ~VIDEO_DIP_ENABLE;
 552                 I915_WRITE(reg, val);
 553                 POSTING_READ(reg);
 554                 return;
 555         }
 556
 557         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 558                 if (val & VIDEO_DIP_ENABLE) {
 559                         val &= ~VIDEO_DIP_ENABLE;
 560                         I915_WRITE(reg, val);
 561                         POSTING_READ(reg);
 562                 }
 563                 val &= ~VIDEO_DIP_PORT_MASK;
 564                 val |= port;
 565         }
 566
 567         val |= VIDEO_DIP_ENABLE;
 568         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 569                  VIDEO_DIP_ENABLE_GCP);
 570
 571         I915_WRITE(reg, val);
 572         POSTING_READ(reg);
 573
 574         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 575         intel_hdmi_set_spd_infoframe(encoder);
 576         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 577 }
 578
 579 static void cpt_set_infoframes(struct drm_encoder *encoder,
 580                                bool enable,
 581                                struct drm_display_mode *adjusted_mode)
 582 {
 583         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 584         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 585         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 586         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 587         u32 val = I915_READ(reg);
 588
 589         assert_hdmi_port_disabled(intel_hdmi);
 590
 591         /* See the big comment in g4x_set_infoframes() */
 592         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 593
 594         if (!enable) {
 595                 if (!(val & VIDEO_DIP_ENABLE))
 596                         return;
 597                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 598                 I915_WRITE(reg, val);
 599                 POSTING_READ(reg);
 600                 return;
 601         }
 602
 603         /* Set both together, unset both together: see the spec. */
 604         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 605         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 606                  VIDEO_DIP_ENABLE_GCP);
 607
 608         I915_WRITE(reg, val);
 609         POSTING_READ(reg);
 610
 611         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 612         intel_hdmi_set_spd_infoframe(encoder);
 613         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 614 }
 615
 616 static void vlv_set_infoframes(struct drm_encoder *encoder,
 617                                bool enable,
 618                                struct drm_display_mode *adjusted_mode)
 619 {
 620         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 621         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 622         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 623         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 624         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 625         u32 val = I915_READ(reg);
 626         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 627
 628         assert_hdmi_port_disabled(intel_hdmi);
 629
 630         /* See the big comment in g4x_set_infoframes() */
 631         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 632
 633         if (!enable) {
 634                 if (!(val & VIDEO_DIP_ENABLE))
 635                         return;
 636                 val &= ~VIDEO_DIP_ENABLE;
 637                 I915_WRITE(reg, val);
 638                 POSTING_READ(reg);
 639                 return;
 640         }
 641
 642         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 643                 if (val & VIDEO_DIP_ENABLE) {
 644                         val &= ~VIDEO_DIP_ENABLE;
 645                         I915_WRITE(reg, val);
 646                         POSTING_READ(reg);
 647                 }
 648                 val &= ~VIDEO_DIP_PORT_MASK;
 649                 val |= port;
 650         }
 651
 652         val |= VIDEO_DIP_ENABLE;
 653         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 654                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 655
 656         I915_WRITE(reg, val);
 657         POSTING_READ(reg);
 658
 659         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 660         intel_hdmi_set_spd_infoframe(encoder);
 661         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 662 }
 663
 664 static void hsw_set_infoframes(struct drm_encoder *encoder,
 665                                bool enable,
 666                                struct drm_display_mode *adjusted_mode)
 667 {
 668         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 669         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 670         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 671         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 672         u32 val = I915_READ(reg);
 673
 674         assert_hdmi_port_disabled(intel_hdmi);
 675
 676         if (!enable) {
 677                 I915_WRITE(reg, 0);
 678                 POSTING_READ(reg);
 679                 return;
 680         }
 681
 682         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 683                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 684
 685         I915_WRITE(reg, val);
 686         POSTING_READ(reg);
 687
 688         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 689         intel_hdmi_set_spd_infoframe(encoder);
 690         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 691 }
 692
 693 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 694 {
 695         struct drm_device *dev = encoder->base.dev;
 696         struct drm_i915_private *dev_priv = dev->dev_private;
 697         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 698         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 699         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 700         u32 hdmi_val;
 701
 702         hdmi_val = SDVO_ENCODING_HDMI;
 703         if (!HAS_PCH_SPLIT(dev))
 704                 hdmi_val |= intel_hdmi->color_range;
 705         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 706                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 707         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 708                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 709
 710         if (crtc->config.pipe_bpp > 24)
 711                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 712         else
 713                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 714
 715         if (crtc->config.has_hdmi_sink)
 716                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 717
 718         if (HAS_PCH_CPT(dev))
 719                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 720         else if (IS_CHERRYVIEW(dev))
 721                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 722         else
 723                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 724
 725         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 726         POSTING_READ(intel_hdmi->hdmi_reg);
 727 }
 728
 729 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 730                                     enum pipe *pipe)
 731 {
 732         struct drm_device *dev = encoder->base.dev;
 733         struct drm_i915_private *dev_priv = dev->dev_private;
 734         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 735         enum intel_display_power_domain power_domain;
 736         u32 tmp;
 737
 738         power_domain = intel_display_port_power_domain(encoder);
 739         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 740                 return false;
 741
 742         tmp = I915_READ(intel_hdmi->hdmi_reg);
 743
 744         if (!(tmp & SDVO_ENABLE))
 745                 return false;
 746
 747         if (HAS_PCH_CPT(dev))
 748                 *pipe = PORT_TO_PIPE_CPT(tmp);
 749         else if (IS_CHERRYVIEW(dev))
 750                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 751         else
 752                 *pipe = PORT_TO_PIPE(tmp);
 753
 754         return true;
 755 }
 756
 757 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 758                                   struct intel_crtc_config *pipe_config)
 759 {
 760         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 761         struct drm_device *dev = encoder->base.dev;
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 tmp, flags = 0;
 764         int dotclock;
 765
 766         tmp = I915_READ(intel_hdmi->hdmi_reg);
 767
 768         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 769                 flags |= DRM_MODE_FLAG_PHSYNC;
 770         else
 771                 flags |= DRM_MODE_FLAG_NHSYNC;
 772
 773         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 774                 flags |= DRM_MODE_FLAG_PVSYNC;
 775         else
 776                 flags |= DRM_MODE_FLAG_NVSYNC;
 777
 778         if (tmp & HDMI_MODE_SELECT_HDMI)
 779                 pipe_config->has_hdmi_sink = true;
 780
 781         if (intel_hdmi->infoframe_enabled(&encoder->base))
 782                 pipe_config->has_infoframe = true;
 783
 784         if (tmp & SDVO_AUDIO_ENABLE)
 785                 pipe_config->has_audio = true;
 786
 787         if (!HAS_PCH_SPLIT(dev) &&
 788             tmp & HDMI_COLOR_RANGE_16_235)
 789                 pipe_config->limited_color_range = true;
 790
 791         pipe_config->adjusted_mode.flags |= flags;
 792
 793         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 794                 dotclock = pipe_config->port_clock * 2 / 3;
 795         else
 796                 dotclock = pipe_config->port_clock;
 797
 798         if (HAS_PCH_SPLIT(dev_priv->dev))
 799                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 800
 801         pipe_config->adjusted_mode.crtc_clock = dotclock;
 802 }
 803
 804 static void intel_enable_hdmi(struct intel_encoder *encoder)
 805 {
 806         struct drm_device *dev = encoder->base.dev;
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 809         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 810         u32 temp;
 811         u32 enable_bits = SDVO_ENABLE;
 812
 813         if (intel_crtc->config.has_audio)
 814                 enable_bits |= SDVO_AUDIO_ENABLE;
 815
 816         temp = I915_READ(intel_hdmi->hdmi_reg);
 817
 818         /* HW workaround for IBX, we need to move the port to transcoder A
 819          * before disabling it, so restore the transcoder select bit here. */
 820         if (HAS_PCH_IBX(dev))
 821                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 822
 823         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 824          * we do this anyway which shows more stable in testing.
 825          */
 826         if (HAS_PCH_SPLIT(dev)) {
 827                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 828                 POSTING_READ(intel_hdmi->hdmi_reg);
 829         }
 830
 831         temp |= enable_bits;
 832
 833         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 834         POSTING_READ(intel_hdmi->hdmi_reg);
 835
 836         /* HW workaround, need to write this twice for issue that may result
 837          * in first write getting masked.
 838          */
 839         if (HAS_PCH_SPLIT(dev)) {
 840                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 841                 POSTING_READ(intel_hdmi->hdmi_reg);
 842         }
 843
 844         if (intel_crtc->config.has_audio) {
 845                 WARN_ON(!intel_crtc->config.has_hdmi_sink);
 846                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 847                                  pipe_name(intel_crtc->pipe));
 848                 intel_audio_codec_enable(encoder);
 849         }
 850 }
 851
 852 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 853 {
 854 }
 855
 856 static void intel_disable_hdmi(struct intel_encoder *encoder)
 857 {
 858         struct drm_device *dev = encoder->base.dev;
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 861         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 862         u32 temp;
 863         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 864
 865         if (crtc->config.has_audio)
 866                 intel_audio_codec_disable(encoder);
 867
 868         temp = I915_READ(intel_hdmi->hdmi_reg);
 869
 870         /* HW workaround for IBX, we need to move the port to transcoder A
 871          * before disabling it. */
 872         if (HAS_PCH_IBX(dev)) {
 873                 struct drm_crtc *crtc = encoder->base.crtc;
 874                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 875
 876                 if (temp & SDVO_PIPE_B_SELECT) {
 877                         temp &= ~SDVO_PIPE_B_SELECT;
 878                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 879                         POSTING_READ(intel_hdmi->hdmi_reg);
 880
 881                         /* Again we need to write this twice. */
 882                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 883                         POSTING_READ(intel_hdmi->hdmi_reg);
 884
 885                         /* Transcoder selection bits only update
 886                          * effectively on vblank. */
 887                         if (crtc)
 888                                 intel_wait_for_vblank(dev, pipe);
 889                         else
 890                                 msleep(50);
 891                 }
 892         }
 893
 894         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 895          * we do this anyway which shows more stable in testing.
 896          */
 897         if (HAS_PCH_SPLIT(dev)) {
 898                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 899                 POSTING_READ(intel_hdmi->hdmi_reg);
 900         }
 901
 902         temp &= ~enable_bits;
 903
 904         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 905         POSTING_READ(intel_hdmi->hdmi_reg);
 906
 907         /* HW workaround, need to write this twice for issue that may result
 908          * in first write getting masked.
 909          */
 910         if (HAS_PCH_SPLIT(dev)) {
 911                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 912                 POSTING_READ(intel_hdmi->hdmi_reg);
 913         }
 914 }
 915
 916 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 917 {
 918         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 919
 920         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 921                 return 165000;
 922         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 923                 return 300000;
 924         else
 925                 return 225000;
 926 }
 927
 928 static enum drm_mode_status
 929 intel_hdmi_mode_valid(struct drm_connector *connector,
 930                       struct drm_display_mode *mode)
 931 {
 932         int clock = mode->clock;
 933
 934         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 935                 clock *= 2;
 936
 937         if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 938                                          true))
 939                 return MODE_CLOCK_HIGH;
 940         if (clock < 20000)
 941                 return MODE_CLOCK_LOW;
 942
 943         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 944                 return MODE_NO_DBLESCAN;
 945
 946         return MODE_OK;
 947 }
 948
 949 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
 950 {
 951         struct drm_device *dev = crtc->base.dev;
 952         struct intel_encoder *encoder;
 953         int count = 0, count_hdmi = 0;
 954
 955         if (HAS_GMCH_DISPLAY(dev))
 956                 return false;
 957
 958         for_each_intel_encoder(dev, encoder) {
 959                 if (encoder->new_crtc != crtc)
 960                         continue;
 961
 962                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 963                 count++;
 964         }
 965
 966         /*
 967          * HDMI 12bpc affects the clocks, so it's only possible
 968          * when not cloning with other encoder types.
 969          */
 970         return count_hdmi > 0 && count_hdmi == count;
 971 }
 972
 973 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 974                                struct intel_crtc_config *pipe_config)
 975 {
 976         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 977         struct drm_device *dev = encoder->base.dev;
 978         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 979         int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
 980         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
 981         int desired_bpp;
 982
 983         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
 984
 985         if (pipe_config->has_hdmi_sink)
 986                 pipe_config->has_infoframe = true;
 987
 988         if (intel_hdmi->color_range_auto) {
 989                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 990                 if (pipe_config->has_hdmi_sink &&
 991                     drm_match_cea_mode(adjusted_mode) > 1)
 992                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 993                 else
 994                         intel_hdmi->color_range = 0;
 995         }
 996
 997         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
 998                 pipe_config->pixel_multiplier = 2;
 999         }
1000
1001         if (intel_hdmi->color_range)
1002                 pipe_config->limited_color_range = true;
1003
1004         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1005                 pipe_config->has_pch_encoder = true;
1006
1007         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1008                 pipe_config->has_audio = true;
1009
1010         /*
1011          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1012          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1013          * outputs. We also need to check that the higher clock still fits
1014          * within limits.
1015          */
1016         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1017             clock_12bpc <= portclock_limit &&
1018             hdmi_12bpc_possible(encoder->new_crtc)) {
1019                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1020                 desired_bpp = 12*3;
1021
1022                 /* Need to adjust the port link by 1.5x for 12bpc. */
1023                 pipe_config->port_clock = clock_12bpc;
1024         } else {
1025                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1026                 desired_bpp = 8*3;
1027         }
1028
1029         if (!pipe_config->bw_constrained) {
1030                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1031                 pipe_config->pipe_bpp = desired_bpp;
1032         }
1033
1034         if (adjusted_mode->crtc_clock > portclock_limit) {
1035                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1036                 return false;
1037         }
1038
1039         return true;
1040 }
1041
1042 static void
1043 intel_hdmi_unset_edid(struct drm_connector *connector)
1044 {
1045         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1046
1047         intel_hdmi->has_hdmi_sink = false;
1048         intel_hdmi->has_audio = false;
1049         intel_hdmi->rgb_quant_range_selectable = false;
1050
1051         kfree(to_intel_connector(connector)->detect_edid);
1052         to_intel_connector(connector)->detect_edid = NULL;
1053 }
1054
1055 static bool
1056 intel_hdmi_set_edid(struct drm_connector *connector)
1057 {
1058         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1059         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1060         struct intel_encoder *intel_encoder =
1061                 &hdmi_to_dig_port(intel_hdmi)->base;
1062         enum intel_display_power_domain power_domain;
1063         struct edid *edid;
1064         bool connected = false;
1065
1066         power_domain = intel_display_port_power_domain(intel_encoder);
1067         intel_display_power_get(dev_priv, power_domain);
1068
1069         edid = drm_get_edid(connector,
1070                             intel_gmbus_get_adapter(dev_priv,
1071                                                     intel_hdmi->ddc_bus));
1072
1073         intel_display_power_put(dev_priv, power_domain);
1074
1075         to_intel_connector(connector)->detect_edid = edid;
1076         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1077                 intel_hdmi->rgb_quant_range_selectable =
1078                         drm_rgb_quant_range_selectable(edid);
1079
1080                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1081                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1082                         intel_hdmi->has_audio =
1083                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1084
1085                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1086                         intel_hdmi->has_hdmi_sink =
1087                                 drm_detect_hdmi_monitor(edid);
1088
1089                 connected = true;
1090         }
1091
1092         return connected;
1093 }
1094
1095 static enum drm_connector_status
1096 intel_hdmi_detect(struct drm_connector *connector, bool force)
1097 {
1098         enum drm_connector_status status;
1099
1100         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1101                       connector->base.id, connector->name);
1102
1103         intel_hdmi_unset_edid(connector);
1104
1105         if (intel_hdmi_set_edid(connector)) {
1106                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1107
1108                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1109                 status = connector_status_connected;
1110         } else
1111                 status = connector_status_disconnected;
1112
1113         return status;
1114 }
1115
1116 static void
1117 intel_hdmi_force(struct drm_connector *connector)
1118 {
1119         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1120
1121         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1122                       connector->base.id, connector->name);
1123
1124         intel_hdmi_unset_edid(connector);
1125
1126         if (connector->status != connector_status_connected)
1127                 return;
1128
1129         intel_hdmi_set_edid(connector);
1130         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1131 }
1132
1133 static int intel_hdmi_get_modes(struct drm_connector *connector)
1134 {
1135         struct edid *edid;
1136
1137         edid = to_intel_connector(connector)->detect_edid;
1138         if (edid == NULL)
1139                 return 0;
1140
1141         return intel_connector_update_modes(connector, edid);
1142 }
1143
1144 static bool
1145 intel_hdmi_detect_audio(struct drm_connector *connector)
1146 {
1147         bool has_audio = false;
1148         struct edid *edid;
1149
1150         edid = to_intel_connector(connector)->detect_edid;
1151         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1152                 has_audio = drm_detect_monitor_audio(edid);
1153
1154         return has_audio;
1155 }
1156
1157 static int
1158 intel_hdmi_set_property(struct drm_connector *connector,
1159                         struct drm_property *property,
1160                         uint64_t val)
1161 {
1162         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1163         struct intel_digital_port *intel_dig_port =
1164                 hdmi_to_dig_port(intel_hdmi);
1165         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1166         int ret;
1167
1168         ret = drm_object_property_set_value(&connector->base, property, val);
1169         if (ret)
1170                 return ret;
1171
1172         if (property == dev_priv->force_audio_property) {
1173                 enum hdmi_force_audio i = val;
1174                 bool has_audio;
1175
1176                 if (i == intel_hdmi->force_audio)
1177                         return 0;
1178
1179                 intel_hdmi->force_audio = i;
1180
1181                 if (i == HDMI_AUDIO_AUTO)
1182                         has_audio = intel_hdmi_detect_audio(connector);
1183                 else
1184                         has_audio = (i == HDMI_AUDIO_ON);
1185
1186                 if (i == HDMI_AUDIO_OFF_DVI)
1187                         intel_hdmi->has_hdmi_sink = 0;
1188
1189                 intel_hdmi->has_audio = has_audio;
1190                 goto done;
1191         }
1192
1193         if (property == dev_priv->broadcast_rgb_property) {
1194                 bool old_auto = intel_hdmi->color_range_auto;
1195                 uint32_t old_range = intel_hdmi->color_range;
1196
1197                 switch (val) {
1198                 case INTEL_BROADCAST_RGB_AUTO:
1199                         intel_hdmi->color_range_auto = true;
1200                         break;
1201                 case INTEL_BROADCAST_RGB_FULL:
1202                         intel_hdmi->color_range_auto = false;
1203                         intel_hdmi->color_range = 0;
1204                         break;
1205                 case INTEL_BROADCAST_RGB_LIMITED:
1206                         intel_hdmi->color_range_auto = false;
1207                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1208                         break;
1209                 default:
1210                         return -EINVAL;
1211                 }
1212
1213                 if (old_auto == intel_hdmi->color_range_auto &&
1214                     old_range == intel_hdmi->color_range)
1215                         return 0;
1216
1217                 goto done;
1218         }
1219
1220         if (property == connector->dev->mode_config.aspect_ratio_property) {
1221                 switch (val) {
1222                 case DRM_MODE_PICTURE_ASPECT_NONE:
1223                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1224                         break;
1225                 case DRM_MODE_PICTURE_ASPECT_4_3:
1226                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1227                         break;
1228                 case DRM_MODE_PICTURE_ASPECT_16_9:
1229                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1230                         break;
1231                 default:
1232                         return -EINVAL;
1233                 }
1234                 goto done;
1235         }
1236
1237         return -EINVAL;
1238
1239 done:
1240         if (intel_dig_port->base.base.crtc)
1241                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1242
1243         return 0;
1244 }
1245
1246 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1247 {
1248         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1249         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1250         struct drm_display_mode *adjusted_mode =
1251                 &intel_crtc->config.adjusted_mode;
1252
1253         intel_hdmi_prepare(encoder);
1254
1255         intel_hdmi->set_infoframes(&encoder->base,
1256                                    intel_crtc->config.has_hdmi_sink,
1257                                    adjusted_mode);
1258 }
1259
1260 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1261 {
1262         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1263         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1264         struct drm_device *dev = encoder->base.dev;
1265         struct drm_i915_private *dev_priv = dev->dev_private;
1266         struct intel_crtc *intel_crtc =
1267                 to_intel_crtc(encoder->base.crtc);
1268         struct drm_display_mode *adjusted_mode =
1269                 &intel_crtc->config.adjusted_mode;
1270         enum dpio_channel port = vlv_dport_to_channel(dport);
1271         int pipe = intel_crtc->pipe;
1272         u32 val;
1273
1274         /* Enable clock channels for this port */
1275         mutex_lock(&dev_priv->dpio_lock);
1276         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1277         val = 0;
1278         if (pipe)
1279                 val |= (1<<21);
1280         else
1281                 val &= ~(1<<21);
1282         val |= 0x001000c4;
1283         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1284
1285         /* HDMI 1.0V-2dB */
1286         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1287         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1288         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1289         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1290         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1291         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1292         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1293         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1294
1295         /* Program lane clock */
1296         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1297         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1298         mutex_unlock(&dev_priv->dpio_lock);
1299
1300         intel_hdmi->set_infoframes(&encoder->base,
1301                                    intel_crtc->config.has_hdmi_sink,
1302                                    adjusted_mode);
1303
1304         intel_enable_hdmi(encoder);
1305
1306         vlv_wait_port_ready(dev_priv, dport);
1307 }
1308
1309 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1310 {
1311         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1312         struct drm_device *dev = encoder->base.dev;
1313         struct drm_i915_private *dev_priv = dev->dev_private;
1314         struct intel_crtc *intel_crtc =
1315                 to_intel_crtc(encoder->base.crtc);
1316         enum dpio_channel port = vlv_dport_to_channel(dport);
1317         int pipe = intel_crtc->pipe;
1318
1319         intel_hdmi_prepare(encoder);
1320
1321         /* Program Tx lane resets to default */
1322         mutex_lock(&dev_priv->dpio_lock);
1323         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1324                          DPIO_PCS_TX_LANE2_RESET |
1325                          DPIO_PCS_TX_LANE1_RESET);
1326         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1327                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1328                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1329                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1330                          DPIO_PCS_CLK_SOFT_RESET);
1331
1332         /* Fix up inter-pair skew failure */
1333         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1334         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1335         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1336
1337         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1338         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1339         mutex_unlock(&dev_priv->dpio_lock);
1340 }
1341
1342 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1343 {
1344         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1345         struct drm_device *dev = encoder->base.dev;
1346         struct drm_i915_private *dev_priv = dev->dev_private;
1347         struct intel_crtc *intel_crtc =
1348                 to_intel_crtc(encoder->base.crtc);
1349         enum dpio_channel ch = vlv_dport_to_channel(dport);
1350         enum pipe pipe = intel_crtc->pipe;
1351         u32 val;
1352
1353         intel_hdmi_prepare(encoder);
1354
1355         mutex_lock(&dev_priv->dpio_lock);
1356
1357         /* program left/right clock distribution */
1358         if (pipe != PIPE_B) {
1359                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1360                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1361                 if (ch == DPIO_CH0)
1362                         val |= CHV_BUFLEFTENA1_FORCE;
1363                 if (ch == DPIO_CH1)
1364                         val |= CHV_BUFRIGHTENA1_FORCE;
1365                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1366         } else {
1367                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1368                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1369                 if (ch == DPIO_CH0)
1370                         val |= CHV_BUFLEFTENA2_FORCE;
1371                 if (ch == DPIO_CH1)
1372                         val |= CHV_BUFRIGHTENA2_FORCE;
1373                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1374         }
1375
1376         /* program clock channel usage */
1377         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1378         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1379         if (pipe != PIPE_B)
1380                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1381         else
1382                 val |= CHV_PCS_USEDCLKCHANNEL;
1383         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1384
1385         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1386         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1387         if (pipe != PIPE_B)
1388                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1389         else
1390                 val |= CHV_PCS_USEDCLKCHANNEL;
1391         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1392
1393         /*
1394          * This a a bit weird since generally CL
1395          * matches the pipe, but here we need to
1396          * pick the CL based on the port.
1397          */
1398         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1399         if (pipe != PIPE_B)
1400                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1401         else
1402                 val |= CHV_CMN_USEDCLKCHANNEL;
1403         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1404
1405         mutex_unlock(&dev_priv->dpio_lock);
1406 }
1407
1408 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1409 {
1410         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1411         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1412         struct intel_crtc *intel_crtc =
1413                 to_intel_crtc(encoder->base.crtc);
1414         enum dpio_channel port = vlv_dport_to_channel(dport);
1415         int pipe = intel_crtc->pipe;
1416
1417         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1418         mutex_lock(&dev_priv->dpio_lock);
1419         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1420         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1421         mutex_unlock(&dev_priv->dpio_lock);
1422 }
1423
1424 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1425 {
1426         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1427         struct drm_device *dev = encoder->base.dev;
1428         struct drm_i915_private *dev_priv = dev->dev_private;
1429         struct intel_crtc *intel_crtc =
1430                 to_intel_crtc(encoder->base.crtc);
1431         enum dpio_channel ch = vlv_dport_to_channel(dport);
1432         enum pipe pipe = intel_crtc->pipe;
1433         u32 val;
1434
1435         mutex_lock(&dev_priv->dpio_lock);
1436
1437         /* Propagate soft reset to data lane reset */
1438         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1439         val |= CHV_PCS_REQ_SOFTRESET_EN;
1440         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1441
1442         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1443         val |= CHV_PCS_REQ_SOFTRESET_EN;
1444         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1445
1446         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1447         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1448         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1449
1450         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1451         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1452         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1453
1454         mutex_unlock(&dev_priv->dpio_lock);
1455 }
1456
1457 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1458 {
1459         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1460         struct drm_device *dev = encoder->base.dev;
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         struct intel_crtc *intel_crtc =
1463                 to_intel_crtc(encoder->base.crtc);
1464         enum dpio_channel ch = vlv_dport_to_channel(dport);
1465         int pipe = intel_crtc->pipe;
1466         int data, i;
1467         u32 val;
1468
1469         mutex_lock(&dev_priv->dpio_lock);
1470
1471         /* allow hardware to manage TX FIFO reset source */
1472         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1473         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1474         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1475
1476         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1477         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1478         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1479
1480         /* Deassert soft data lane reset*/
1481         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1482         val |= CHV_PCS_REQ_SOFTRESET_EN;
1483         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1484
1485         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1486         val |= CHV_PCS_REQ_SOFTRESET_EN;
1487         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1488
1489         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1490         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1491         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1492
1493         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1494         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1495         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1496
1497         /* Program Tx latency optimal setting */
1498         for (i = 0; i < 4; i++) {
1499                 /* Set the latency optimal bit */
1500                 data = (i == 1) ? 0x0 : 0x6;
1501                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1502                                 data << DPIO_FRC_LATENCY_SHFIT);
1503
1504                 /* Set the upar bit */
1505                 data = (i == 1) ? 0x0 : 0x1;
1506                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1507                                 data << DPIO_UPAR_SHIFT);
1508         }
1509
1510         /* Data lane stagger programming */
1511         /* FIXME: Fix up value only after power analysis */
1512
1513         /* Clear calc init */
1514         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1515         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1516         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1517         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1518         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1519
1520         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1521         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1522         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1523         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1524         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1525
1526         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1527         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1528         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1529         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1530
1531         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1532         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1533         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1534         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1535
1536         /* FIXME: Program the support xxx V-dB */
1537         /* Use 800mV-0dB */
1538         for (i = 0; i < 4; i++) {
1539                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1540                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1541                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1542                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1543         }
1544
1545         for (i = 0; i < 4; i++) {
1546                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1547                 val &= ~DPIO_SWING_MARGIN000_MASK;
1548                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1549                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1550         }
1551
1552         /* Disable unique transition scale */
1553         for (i = 0; i < 4; i++) {
1554                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1555                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1556                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1557         }
1558
1559         /* Additional steps for 1200mV-0dB */
1560 #if 0
1561         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1562         if (ch)
1563                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1564         else
1565                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1566         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1567
1568         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1569                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1570                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1571 #endif
1572         /* Start swing calculation */
1573         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1574         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1575         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1576
1577         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1578         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1579         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1580
1581         /* LRC Bypass */
1582         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1583         val |= DPIO_LRC_BYPASS;
1584         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1585
1586         mutex_unlock(&dev_priv->dpio_lock);
1587
1588         intel_enable_hdmi(encoder);
1589
1590         vlv_wait_port_ready(dev_priv, dport);
1591 }
1592
1593 static void intel_hdmi_destroy(struct drm_connector *connector)
1594 {
1595         kfree(to_intel_connector(connector)->detect_edid);
1596         drm_connector_cleanup(connector);
1597         kfree(connector);
1598 }
1599
1600 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1601         .dpms = intel_connector_dpms,
1602         .detect = intel_hdmi_detect,
1603         .force = intel_hdmi_force,
1604         .fill_modes = drm_helper_probe_single_connector_modes,
1605         .set_property = intel_hdmi_set_property,
1606         .destroy = intel_hdmi_destroy,
1607 };
1608
1609 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1610         .get_modes = intel_hdmi_get_modes,
1611         .mode_valid = intel_hdmi_mode_valid,
1612         .best_encoder = intel_best_encoder,
1613 };
1614
1615 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1616         .destroy = intel_encoder_destroy,
1617 };
1618
1619 static void
1620 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1621 {
1622         if (!drm_mode_create_aspect_ratio_property(connector->dev))
1623                 drm_object_attach_property(&connector->base,
1624                         connector->dev->mode_config.aspect_ratio_property,
1625                         DRM_MODE_PICTURE_ASPECT_NONE);
1626 }
1627
1628 static void
1629 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1630 {
1631         intel_attach_force_audio_property(connector);
1632         intel_attach_broadcast_rgb_property(connector);
1633         intel_hdmi->color_range_auto = true;
1634         intel_attach_aspect_ratio_property(connector);
1635         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1636 }
1637
1638 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1639                                struct intel_connector *intel_connector)
1640 {
1641         struct drm_connector *connector = &intel_connector->base;
1642         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1643         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1644         struct drm_device *dev = intel_encoder->base.dev;
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646         enum port port = intel_dig_port->port;
1647
1648         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1649                            DRM_MODE_CONNECTOR_HDMIA);
1650         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1651
1652         connector->interlace_allowed = 1;
1653         connector->doublescan_allowed = 0;
1654         connector->stereo_allowed = 1;
1655
1656         switch (port) {
1657         case PORT_B:
1658                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1659                 intel_encoder->hpd_pin = HPD_PORT_B;
1660                 break;
1661         case PORT_C:
1662                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1663                 intel_encoder->hpd_pin = HPD_PORT_C;
1664                 break;
1665         case PORT_D:
1666                 if (IS_CHERRYVIEW(dev))
1667                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1668                 else
1669                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1670                 intel_encoder->hpd_pin = HPD_PORT_D;
1671                 break;
1672         case PORT_A:
1673                 intel_encoder->hpd_pin = HPD_PORT_A;
1674                 /* Internal port only for eDP. */
1675         default:
1676                 BUG();
1677         }
1678
1679         if (IS_VALLEYVIEW(dev)) {
1680                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1681                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1682                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1683         } else if (IS_G4X(dev)) {
1684                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1685                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1686                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1687         } else if (HAS_DDI(dev)) {
1688                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1689                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1690                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1691         } else if (HAS_PCH_IBX(dev)) {
1692                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1693                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1694                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1695         } else {
1696                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1697                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1698                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1699         }
1700
1701         if (HAS_DDI(dev))
1702                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1703         else
1704                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1705         intel_connector->unregister = intel_connector_unregister;
1706
1707         intel_hdmi_add_properties(intel_hdmi, connector);
1708
1709         intel_connector_attach_encoder(intel_connector, intel_encoder);
1710         drm_connector_register(connector);
1711
1712         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1713          * 0xd.  Failure to do so will result in spurious interrupts being
1714          * generated on the port when a cable is not attached.
1715          */
1716         if (IS_G4X(dev) && !IS_GM45(dev)) {
1717                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1718                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1719         }
1720 }
1721
1722 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1723 {
1724         struct intel_digital_port *intel_dig_port;
1725         struct intel_encoder *intel_encoder;
1726         struct intel_connector *intel_connector;
1727
1728         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1729         if (!intel_dig_port)
1730                 return;
1731
1732         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1733         if (!intel_connector) {
1734                 kfree(intel_dig_port);
1735                 return;
1736         }
1737
1738         intel_encoder = &intel_dig_port->base;
1739
1740         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1741                          DRM_MODE_ENCODER_TMDS);
1742
1743         intel_encoder->compute_config = intel_hdmi_compute_config;
1744         intel_encoder->disable = intel_disable_hdmi;
1745         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1746         intel_encoder->get_config = intel_hdmi_get_config;
1747         if (IS_CHERRYVIEW(dev)) {
1748                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1749                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1750                 intel_encoder->enable = vlv_enable_hdmi;
1751                 intel_encoder->post_disable = chv_hdmi_post_disable;
1752         } else if (IS_VALLEYVIEW(dev)) {
1753                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1754                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1755                 intel_encoder->enable = vlv_enable_hdmi;
1756                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1757         } else {
1758                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1759                 intel_encoder->enable = intel_enable_hdmi;
1760         }
1761
1762         intel_encoder->type = INTEL_OUTPUT_HDMI;
1763         if (IS_CHERRYVIEW(dev)) {
1764                 if (port == PORT_D)
1765                         intel_encoder->crtc_mask = 1 << 2;
1766                 else
1767                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1768         } else {
1769                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1770         }
1771         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1772         /*
1773          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1774          * to work on real hardware. And since g4x can send infoframes to
1775          * only one port anyway, nothing is lost by allowing it.
1776          */
1777         if (IS_G4X(dev))
1778                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1779
1780         intel_dig_port->port = port;
1781         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1782         intel_dig_port->dp.output_reg = 0;
1783
1784         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1785 }