drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_crtc.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 static void
  41 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  42 {
  43         struct drm_device *dev = intel_hdmi->base.base.dev;
  44         struct drm_i915_private *dev_priv = dev->dev_private;
  45         uint32_t enabled_bits;
  46
  47         enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  48
  49         WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
  50              "HDMI port enabled, expecting disabled\n");
  51 }
  52
  53 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  54 {
  55         return container_of(encoder, struct intel_hdmi, base.base);
  56 }
  57
  58 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  59 {
  60         return container_of(intel_attached_encoder(connector),
  61                             struct intel_hdmi, base);
  62 }
  63
  64 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  65 {
  66         uint8_t *data = (uint8_t *)frame;
  67         uint8_t sum = 0;
  68         unsigned i;
  69
  70         frame->checksum = 0;
  71         frame->ecc = 0;
  72
  73         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  74                 sum += data[i];
  75
  76         frame->checksum = 0x100 - sum;
  77 }
  78
  79 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  80 {
  81         switch (frame->type) {
  82         case DIP_TYPE_AVI:
  83                 return VIDEO_DIP_SELECT_AVI;
  84         case DIP_TYPE_SPD:
  85                 return VIDEO_DIP_SELECT_SPD;
  86         default:
  87                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  88                 return 0;
  89         }
  90 }
  91
  92 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  93 {
  94         switch (frame->type) {
  95         case DIP_TYPE_AVI:
  96                 return VIDEO_DIP_ENABLE_AVI;
  97         case DIP_TYPE_SPD:
  98                 return VIDEO_DIP_ENABLE_SPD;
  99         default:
 100                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 101                 return 0;
 102         }
 103 }
 104
 105 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
 106 {
 107         switch (frame->type) {
 108         case DIP_TYPE_AVI:
 109                 return VIDEO_DIP_ENABLE_AVI_HSW;
 110         case DIP_TYPE_SPD:
 111                 return VIDEO_DIP_ENABLE_SPD_HSW;
 112         default:
 113                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 114                 return 0;
 115         }
 116 }
 117
 118 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
 119 {
 120         switch (frame->type) {
 121         case DIP_TYPE_AVI:
 122                 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
 123         case DIP_TYPE_SPD:
 124                 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
 125         default:
 126                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 127                 return 0;
 128         }
 129 }
 130
 131 static void g4x_write_infoframe(struct drm_encoder *encoder,
 132                                 struct dip_infoframe *frame)
 133 {
 134         uint32_t *data = (uint32_t *)frame;
 135         struct drm_device *dev = encoder->dev;
 136         struct drm_i915_private *dev_priv = dev->dev_private;
 137         u32 val = I915_READ(VIDEO_DIP_CTL);
 138         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 139
 140         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 141
 142         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 143         val |= g4x_infoframe_index(frame);
 144
 145         val &= ~g4x_infoframe_enable(frame);
 146
 147         I915_WRITE(VIDEO_DIP_CTL, val);
 148
 149         mmiowb();
 150         for (i = 0; i < len; i += 4) {
 151                 I915_WRITE(VIDEO_DIP_DATA, *data);
 152                 data++;
 153         }
 154         mmiowb();
 155
 156         val |= g4x_infoframe_enable(frame);
 157         val &= ~VIDEO_DIP_FREQ_MASK;
 158         val |= VIDEO_DIP_FREQ_VSYNC;
 159
 160         I915_WRITE(VIDEO_DIP_CTL, val);
 161         POSTING_READ(VIDEO_DIP_CTL);
 162 }
 163
 164 static void ibx_write_infoframe(struct drm_encoder *encoder,
 165                                 struct dip_infoframe *frame)
 166 {
 167         uint32_t *data = (uint32_t *)frame;
 168         struct drm_device *dev = encoder->dev;
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 171         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 172         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 173         u32 val = I915_READ(reg);
 174
 175         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 176
 177         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 178         val |= g4x_infoframe_index(frame);
 179
 180         val &= ~g4x_infoframe_enable(frame);
 181
 182         I915_WRITE(reg, val);
 183
 184         mmiowb();
 185         for (i = 0; i < len; i += 4) {
 186                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 187                 data++;
 188         }
 189         mmiowb();
 190
 191         val |= g4x_infoframe_enable(frame);
 192         val &= ~VIDEO_DIP_FREQ_MASK;
 193         val |= VIDEO_DIP_FREQ_VSYNC;
 194
 195         I915_WRITE(reg, val);
 196         POSTING_READ(reg);
 197 }
 198
 199 static void cpt_write_infoframe(struct drm_encoder *encoder,
 200                                 struct dip_infoframe *frame)
 201 {
 202         uint32_t *data = (uint32_t *)frame;
 203         struct drm_device *dev = encoder->dev;
 204         struct drm_i915_private *dev_priv = dev->dev_private;
 205         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 206         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 207         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 208         u32 val = I915_READ(reg);
 209
 210         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 211
 212         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 213         val |= g4x_infoframe_index(frame);
 214
 215         /* The DIP control register spec says that we need to update the AVI
 216          * infoframe without clearing its enable bit */
 217         if (frame->type != DIP_TYPE_AVI)
 218                 val &= ~g4x_infoframe_enable(frame);
 219
 220         I915_WRITE(reg, val);
 221
 222         mmiowb();
 223         for (i = 0; i < len; i += 4) {
 224                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 225                 data++;
 226         }
 227         mmiowb();
 228
 229         val |= g4x_infoframe_enable(frame);
 230         val &= ~VIDEO_DIP_FREQ_MASK;
 231         val |= VIDEO_DIP_FREQ_VSYNC;
 232
 233         I915_WRITE(reg, val);
 234         POSTING_READ(reg);
 235 }
 236
 237 static void vlv_write_infoframe(struct drm_encoder *encoder,
 238                                      struct dip_infoframe *frame)
 239 {
 240         uint32_t *data = (uint32_t *)frame;
 241         struct drm_device *dev = encoder->dev;
 242         struct drm_i915_private *dev_priv = dev->dev_private;
 243         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 244         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 245         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 246         u32 val = I915_READ(reg);
 247
 248         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 249
 250         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 251         val |= g4x_infoframe_index(frame);
 252
 253         val &= ~g4x_infoframe_enable(frame);
 254
 255         I915_WRITE(reg, val);
 256
 257         mmiowb();
 258         for (i = 0; i < len; i += 4) {
 259                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 260                 data++;
 261         }
 262         mmiowb();
 263
 264         val |= g4x_infoframe_enable(frame);
 265         val &= ~VIDEO_DIP_FREQ_MASK;
 266         val |= VIDEO_DIP_FREQ_VSYNC;
 267
 268         I915_WRITE(reg, val);
 269         POSTING_READ(reg);
 270 }
 271
 272 static void hsw_write_infoframe(struct drm_encoder *encoder,
 273                                 struct dip_infoframe *frame)
 274 {
 275         uint32_t *data = (uint32_t *)frame;
 276         struct drm_device *dev = encoder->dev;
 277         struct drm_i915_private *dev_priv = dev->dev_private;
 278         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 279         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 280         u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
 281         unsigned int i, len = DIP_HEADER_SIZE + frame->len;
 282         u32 val = I915_READ(ctl_reg);
 283
 284         if (data_reg == 0)
 285                 return;
 286
 287         val &= ~hsw_infoframe_enable(frame);
 288         I915_WRITE(ctl_reg, val);
 289
 290         mmiowb();
 291         for (i = 0; i < len; i += 4) {
 292                 I915_WRITE(data_reg + i, *data);
 293                 data++;
 294         }
 295         mmiowb();
 296
 297         val |= hsw_infoframe_enable(frame);
 298         I915_WRITE(ctl_reg, val);
 299         POSTING_READ(ctl_reg);
 300 }
 301
 302 static void intel_set_infoframe(struct drm_encoder *encoder,
 303                                 struct dip_infoframe *frame)
 304 {
 305         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 306
 307         intel_dip_infoframe_csum(frame);
 308         intel_hdmi->write_infoframe(encoder, frame);
 309 }
 310
 311 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 312                                          struct drm_display_mode *adjusted_mode)
 313 {
 314         struct dip_infoframe avi_if = {
 315                 .type = DIP_TYPE_AVI,
 316                 .ver = DIP_VERSION_AVI,
 317                 .len = DIP_LEN_AVI,
 318         };
 319
 320         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 321                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 322
 323         intel_set_infoframe(encoder, &avi_if);
 324 }
 325
 326 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 327 {
 328         struct dip_infoframe spd_if;
 329
 330         memset(&spd_if, 0, sizeof(spd_if));
 331         spd_if.type = DIP_TYPE_SPD;
 332         spd_if.ver = DIP_VERSION_SPD;
 333         spd_if.len = DIP_LEN_SPD;
 334         strcpy(spd_if.body.spd.vn, "Intel");
 335         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 336         spd_if.body.spd.sdi = DIP_SPD_PC;
 337
 338         intel_set_infoframe(encoder, &spd_if);
 339 }
 340
 341 static void g4x_set_infoframes(struct drm_encoder *encoder,
 342                                struct drm_display_mode *adjusted_mode)
 343 {
 344         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 345         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 346         u32 reg = VIDEO_DIP_CTL;
 347         u32 val = I915_READ(reg);
 348         u32 port;
 349
 350         assert_hdmi_port_disabled(intel_hdmi);
 351
 352         /* If the registers were not initialized yet, they might be zeroes,
 353          * which means we're selecting the AVI DIP and we're setting its
 354          * frequency to once. This seems to really confuse the HW and make
 355          * things stop working (the register spec says the AVI always needs to
 356          * be sent every VSync). So here we avoid writing to the register more
 357          * than we need and also explicitly select the AVI DIP and explicitly
 358          * set its frequency to every VSync. Avoiding to write it twice seems to
 359          * be enough to solve the problem, but being defensive shouldn't hurt us
 360          * either. */
 361         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 362
 363         if (!intel_hdmi->has_hdmi_sink) {
 364                 if (!(val & VIDEO_DIP_ENABLE))
 365                         return;
 366                 val &= ~VIDEO_DIP_ENABLE;
 367                 I915_WRITE(reg, val);
 368                 POSTING_READ(reg);
 369                 return;
 370         }
 371
 372         switch (intel_hdmi->sdvox_reg) {
 373         case SDVOB:
 374                 port = VIDEO_DIP_PORT_B;
 375                 break;
 376         case SDVOC:
 377                 port = VIDEO_DIP_PORT_C;
 378                 break;
 379         default:
 380                 BUG();
 381                 return;
 382         }
 383
 384         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 385                 if (val & VIDEO_DIP_ENABLE) {
 386                         val &= ~VIDEO_DIP_ENABLE;
 387                         I915_WRITE(reg, val);
 388                         POSTING_READ(reg);
 389                 }
 390                 val &= ~VIDEO_DIP_PORT_MASK;
 391                 val |= port;
 392         }
 393
 394         val |= VIDEO_DIP_ENABLE;
 395         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 396
 397         I915_WRITE(reg, val);
 398         POSTING_READ(reg);
 399
 400         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 401         intel_hdmi_set_spd_infoframe(encoder);
 402 }
 403
 404 static void ibx_set_infoframes(struct drm_encoder *encoder,
 405                                struct drm_display_mode *adjusted_mode)
 406 {
 407         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 408         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 409         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 410         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 411         u32 val = I915_READ(reg);
 412         u32 port;
 413
 414         assert_hdmi_port_disabled(intel_hdmi);
 415
 416         /* See the big comment in g4x_set_infoframes() */
 417         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 418
 419         if (!intel_hdmi->has_hdmi_sink) {
 420                 if (!(val & VIDEO_DIP_ENABLE))
 421                         return;
 422                 val &= ~VIDEO_DIP_ENABLE;
 423                 I915_WRITE(reg, val);
 424                 POSTING_READ(reg);
 425                 return;
 426         }
 427
 428         switch (intel_hdmi->sdvox_reg) {
 429         case HDMIB:
 430                 port = VIDEO_DIP_PORT_B;
 431                 break;
 432         case HDMIC:
 433                 port = VIDEO_DIP_PORT_C;
 434                 break;
 435         case HDMID:
 436                 port = VIDEO_DIP_PORT_D;
 437                 break;
 438         default:
 439                 BUG();
 440                 return;
 441         }
 442
 443         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 444                 if (val & VIDEO_DIP_ENABLE) {
 445                         val &= ~VIDEO_DIP_ENABLE;
 446                         I915_WRITE(reg, val);
 447                         POSTING_READ(reg);
 448                 }
 449                 val &= ~VIDEO_DIP_PORT_MASK;
 450                 val |= port;
 451         }
 452
 453         val |= VIDEO_DIP_ENABLE;
 454         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 455                  VIDEO_DIP_ENABLE_GCP);
 456
 457         I915_WRITE(reg, val);
 458         POSTING_READ(reg);
 459
 460         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 461         intel_hdmi_set_spd_infoframe(encoder);
 462 }
 463
 464 static void cpt_set_infoframes(struct drm_encoder *encoder,
 465                                struct drm_display_mode *adjusted_mode)
 466 {
 467         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 468         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 469         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 470         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 471         u32 val = I915_READ(reg);
 472
 473         assert_hdmi_port_disabled(intel_hdmi);
 474
 475         /* See the big comment in g4x_set_infoframes() */
 476         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 477
 478         if (!intel_hdmi->has_hdmi_sink) {
 479                 if (!(val & VIDEO_DIP_ENABLE))
 480                         return;
 481                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 482                 I915_WRITE(reg, val);
 483                 POSTING_READ(reg);
 484                 return;
 485         }
 486
 487         /* Set both together, unset both together: see the spec. */
 488         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 489         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 490                  VIDEO_DIP_ENABLE_GCP);
 491
 492         I915_WRITE(reg, val);
 493         POSTING_READ(reg);
 494
 495         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 496         intel_hdmi_set_spd_infoframe(encoder);
 497 }
 498
 499 static void vlv_set_infoframes(struct drm_encoder *encoder,
 500                                struct drm_display_mode *adjusted_mode)
 501 {
 502         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 503         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 504         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 505         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 506         u32 val = I915_READ(reg);
 507
 508         assert_hdmi_port_disabled(intel_hdmi);
 509
 510         /* See the big comment in g4x_set_infoframes() */
 511         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 512
 513         if (!intel_hdmi->has_hdmi_sink) {
 514                 if (!(val & VIDEO_DIP_ENABLE))
 515                         return;
 516                 val &= ~VIDEO_DIP_ENABLE;
 517                 I915_WRITE(reg, val);
 518                 POSTING_READ(reg);
 519                 return;
 520         }
 521
 522         val |= VIDEO_DIP_ENABLE;
 523         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 524                  VIDEO_DIP_ENABLE_GCP);
 525
 526         I915_WRITE(reg, val);
 527         POSTING_READ(reg);
 528
 529         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 530         intel_hdmi_set_spd_infoframe(encoder);
 531 }
 532
 533 static void hsw_set_infoframes(struct drm_encoder *encoder,
 534                                struct drm_display_mode *adjusted_mode)
 535 {
 536         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 537         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 538         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 539         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 540         u32 val = I915_READ(reg);
 541
 542         assert_hdmi_port_disabled(intel_hdmi);
 543
 544         if (!intel_hdmi->has_hdmi_sink) {
 545                 I915_WRITE(reg, 0);
 546                 POSTING_READ(reg);
 547                 return;
 548         }
 549
 550         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 551                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 552
 553         I915_WRITE(reg, val);
 554         POSTING_READ(reg);
 555
 556         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 557         intel_hdmi_set_spd_infoframe(encoder);
 558 }
 559
 560 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 561                                 struct drm_display_mode *mode,
 562                                 struct drm_display_mode *adjusted_mode)
 563 {
 564         struct drm_device *dev = encoder->dev;
 565         struct drm_i915_private *dev_priv = dev->dev_private;
 566         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 567         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 568         u32 sdvox;
 569
 570         sdvox = SDVO_ENCODING_HDMI;
 571         if (!HAS_PCH_SPLIT(dev))
 572                 sdvox |= intel_hdmi->color_range;
 573         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 574                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 575         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 576                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 577
 578         if (intel_crtc->bpp > 24)
 579                 sdvox |= COLOR_FORMAT_12bpc;
 580         else
 581                 sdvox |= COLOR_FORMAT_8bpc;
 582
 583         /* Required on CPT */
 584         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 585                 sdvox |= HDMI_MODE_SELECT;
 586
 587         if (intel_hdmi->has_audio) {
 588                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 589                                  pipe_name(intel_crtc->pipe));
 590                 sdvox |= SDVO_AUDIO_ENABLE;
 591                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 592                 intel_write_eld(encoder, adjusted_mode);
 593         }
 594
 595         if (HAS_PCH_CPT(dev))
 596                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 597         else if (intel_crtc->pipe == PIPE_B)
 598                 sdvox |= SDVO_PIPE_B_SELECT;
 599
 600         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 601         POSTING_READ(intel_hdmi->sdvox_reg);
 602
 603         intel_hdmi->set_infoframes(encoder, adjusted_mode);
 604 }
 605
 606 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 607                                     enum pipe *pipe)
 608 {
 609         struct drm_device *dev = encoder->base.dev;
 610         struct drm_i915_private *dev_priv = dev->dev_private;
 611         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 612         u32 tmp;
 613
 614         tmp = I915_READ(intel_hdmi->sdvox_reg);
 615
 616         if (!(tmp & SDVO_ENABLE))
 617                 return false;
 618
 619         if (HAS_PCH_CPT(dev))
 620                 *pipe = PORT_TO_PIPE_CPT(tmp);
 621         else
 622                 *pipe = PORT_TO_PIPE(tmp);
 623
 624         return true;
 625 }
 626
 627 static void intel_enable_hdmi(struct intel_encoder *encoder)
 628 {
 629         struct drm_device *dev = encoder->base.dev;
 630         struct drm_i915_private *dev_priv = dev->dev_private;
 631         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 632         u32 temp;
 633         u32 enable_bits = SDVO_ENABLE;
 634
 635         if (intel_hdmi->has_audio)
 636                 enable_bits |= SDVO_AUDIO_ENABLE;
 637
 638         temp = I915_READ(intel_hdmi->sdvox_reg);
 639
 640         /* HW workaround for IBX, we need to move the port to transcoder A
 641          * before disabling it. */
 642         if (HAS_PCH_IBX(dev)) {
 643                 struct drm_crtc *crtc = encoder->base.crtc;
 644                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 645
 646                 /* Restore the transcoder select bit. */
 647                 if (pipe == PIPE_B)
 648                         enable_bits |= SDVO_PIPE_B_SELECT;
 649         }
 650
 651         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 652          * we do this anyway which shows more stable in testing.
 653          */
 654         if (HAS_PCH_SPLIT(dev)) {
 655                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 656                 POSTING_READ(intel_hdmi->sdvox_reg);
 657         }
 658
 659         temp |= enable_bits;
 660
 661         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 662         POSTING_READ(intel_hdmi->sdvox_reg);
 663
 664         /* HW workaround, need to write this twice for issue that may result
 665          * in first write getting masked.
 666          */
 667         if (HAS_PCH_SPLIT(dev)) {
 668                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 669                 POSTING_READ(intel_hdmi->sdvox_reg);
 670         }
 671 }
 672
 673 static void intel_disable_hdmi(struct intel_encoder *encoder)
 674 {
 675         struct drm_device *dev = encoder->base.dev;
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 678         u32 temp;
 679         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 680
 681         temp = I915_READ(intel_hdmi->sdvox_reg);
 682
 683         /* HW workaround for IBX, we need to move the port to transcoder A
 684          * before disabling it. */
 685         if (HAS_PCH_IBX(dev)) {
 686                 struct drm_crtc *crtc = encoder->base.crtc;
 687                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 688
 689                 if (temp & SDVO_PIPE_B_SELECT) {
 690                         temp &= ~SDVO_PIPE_B_SELECT;
 691                         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 692                         POSTING_READ(intel_hdmi->sdvox_reg);
 693
 694                         /* Again we need to write this twice. */
 695                         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 696                         POSTING_READ(intel_hdmi->sdvox_reg);
 697
 698                         /* Transcoder selection bits only update
 699                          * effectively on vblank. */
 700                         if (crtc)
 701                                 intel_wait_for_vblank(dev, pipe);
 702                         else
 703                                 msleep(50);
 704                 }
 705         }
 706
 707         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 708          * we do this anyway which shows more stable in testing.
 709          */
 710         if (HAS_PCH_SPLIT(dev)) {
 711                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 712                 POSTING_READ(intel_hdmi->sdvox_reg);
 713         }
 714
 715         temp &= ~enable_bits;
 716
 717         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 718         POSTING_READ(intel_hdmi->sdvox_reg);
 719
 720         /* HW workaround, need to write this twice for issue that may result
 721          * in first write getting masked.
 722          */
 723         if (HAS_PCH_SPLIT(dev)) {
 724                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 725                 POSTING_READ(intel_hdmi->sdvox_reg);
 726         }
 727 }
 728
 729 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 730                                  struct drm_display_mode *mode)
 731 {
 732         if (mode->clock > 165000)
 733                 return MODE_CLOCK_HIGH;
 734         if (mode->clock < 20000)
 735                 return MODE_CLOCK_LOW;
 736
 737         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 738                 return MODE_NO_DBLESCAN;
 739
 740         return MODE_OK;
 741 }
 742
 743 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 744                                   const struct drm_display_mode *mode,
 745                                   struct drm_display_mode *adjusted_mode)
 746 {
 747         return true;
 748 }
 749
 750 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
 751 {
 752         struct drm_device *dev = intel_hdmi->base.base.dev;
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         uint32_t bit;
 755
 756         switch (intel_hdmi->sdvox_reg) {
 757         case SDVOB:
 758                 bit = HDMIB_HOTPLUG_LIVE_STATUS;
 759                 break;
 760         case SDVOC:
 761                 bit = HDMIC_HOTPLUG_LIVE_STATUS;
 762                 break;
 763         default:
 764                 bit = 0;
 765                 break;
 766         }
 767
 768         return I915_READ(PORT_HOTPLUG_STAT) & bit;
 769 }
 770
 771 static enum drm_connector_status
 772 intel_hdmi_detect(struct drm_connector *connector, bool force)
 773 {
 774         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 775         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 776         struct edid *edid;
 777         enum drm_connector_status status = connector_status_disconnected;
 778
 779         if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
 780                 return status;
 781
 782         intel_hdmi->has_hdmi_sink = false;
 783         intel_hdmi->has_audio = false;
 784         edid = drm_get_edid(connector,
 785                             intel_gmbus_get_adapter(dev_priv,
 786                                                     intel_hdmi->ddc_bus));
 787
 788         if (edid) {
 789                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 790                         status = connector_status_connected;
 791                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 792                                 intel_hdmi->has_hdmi_sink =
 793                                                 drm_detect_hdmi_monitor(edid);
 794                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 795                 }
 796                 kfree(edid);
 797         }
 798
 799         if (status == connector_status_connected) {
 800                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 801                         intel_hdmi->has_audio =
 802                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 803         }
 804
 805         return status;
 806 }
 807
 808 static int intel_hdmi_get_modes(struct drm_connector *connector)
 809 {
 810         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 811         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 812
 813         /* We should parse the EDID data and find out if it's an HDMI sink so
 814          * we can send audio to it.
 815          */
 816
 817         return intel_ddc_get_modes(connector,
 818                                    intel_gmbus_get_adapter(dev_priv,
 819                                                            intel_hdmi->ddc_bus));
 820 }
 821
 822 static bool
 823 intel_hdmi_detect_audio(struct drm_connector *connector)
 824 {
 825         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 826         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 827         struct edid *edid;
 828         bool has_audio = false;
 829
 830         edid = drm_get_edid(connector,
 831                             intel_gmbus_get_adapter(dev_priv,
 832                                                     intel_hdmi->ddc_bus));
 833         if (edid) {
 834                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 835                         has_audio = drm_detect_monitor_audio(edid);
 836                 kfree(edid);
 837         }
 838
 839         return has_audio;
 840 }
 841
 842 static int
 843 intel_hdmi_set_property(struct drm_connector *connector,
 844                         struct drm_property *property,
 845                         uint64_t val)
 846 {
 847         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 848         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 849         int ret;
 850
 851         ret = drm_connector_property_set_value(connector, property, val);
 852         if (ret)
 853                 return ret;
 854
 855         if (property == dev_priv->force_audio_property) {
 856                 enum hdmi_force_audio i = val;
 857                 bool has_audio;
 858
 859                 if (i == intel_hdmi->force_audio)
 860                         return 0;
 861
 862                 intel_hdmi->force_audio = i;
 863
 864                 if (i == HDMI_AUDIO_AUTO)
 865                         has_audio = intel_hdmi_detect_audio(connector);
 866                 else
 867                         has_audio = (i == HDMI_AUDIO_ON);
 868
 869                 if (i == HDMI_AUDIO_OFF_DVI)
 870                         intel_hdmi->has_hdmi_sink = 0;
 871
 872                 intel_hdmi->has_audio = has_audio;
 873                 goto done;
 874         }
 875
 876         if (property == dev_priv->broadcast_rgb_property) {
 877                 if (val == !!intel_hdmi->color_range)
 878                         return 0;
 879
 880                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 881                 goto done;
 882         }
 883
 884         return -EINVAL;
 885
 886 done:
 887         if (intel_hdmi->base.base.crtc) {
 888                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
 889                 intel_set_mode(crtc, &crtc->mode,
 890                                crtc->x, crtc->y, crtc->fb);
 891         }
 892
 893         return 0;
 894 }
 895
 896 static void intel_hdmi_destroy(struct drm_connector *connector)
 897 {
 898         drm_sysfs_connector_remove(connector);
 899         drm_connector_cleanup(connector);
 900         kfree(connector);
 901 }
 902
 903 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
 904         .mode_fixup = intel_hdmi_mode_fixup,
 905         .mode_set = intel_ddi_mode_set,
 906         .disable = intel_encoder_noop,
 907 };
 908
 909 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 910         .mode_fixup = intel_hdmi_mode_fixup,
 911         .mode_set = intel_hdmi_mode_set,
 912         .disable = intel_encoder_noop,
 913 };
 914
 915 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 916         .dpms = intel_connector_dpms,
 917         .detect = intel_hdmi_detect,
 918         .fill_modes = drm_helper_probe_single_connector_modes,
 919         .set_property = intel_hdmi_set_property,
 920         .destroy = intel_hdmi_destroy,
 921 };
 922
 923 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 924         .get_modes = intel_hdmi_get_modes,
 925         .mode_valid = intel_hdmi_mode_valid,
 926         .best_encoder = intel_best_encoder,
 927 };
 928
 929 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 930         .destroy = intel_encoder_destroy,
 931 };
 932
 933 static void
 934 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 935 {
 936         intel_attach_force_audio_property(connector);
 937         intel_attach_broadcast_rgb_property(connector);
 938 }
 939
 940 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
 941 {
 942         struct drm_i915_private *dev_priv = dev->dev_private;
 943         struct drm_connector *connector;
 944         struct intel_encoder *intel_encoder;
 945         struct intel_connector *intel_connector;
 946         struct intel_hdmi *intel_hdmi;
 947
 948         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 949         if (!intel_hdmi)
 950                 return;
 951
 952         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 953         if (!intel_connector) {
 954                 kfree(intel_hdmi);
 955                 return;
 956         }
 957
 958         intel_encoder = &intel_hdmi->base;
 959         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
 960                          DRM_MODE_ENCODER_TMDS);
 961
 962         connector = &intel_connector->base;
 963         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 964                            DRM_MODE_CONNECTOR_HDMIA);
 965         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 966
 967         intel_encoder->type = INTEL_OUTPUT_HDMI;
 968
 969         connector->polled = DRM_CONNECTOR_POLL_HPD;
 970         connector->interlace_allowed = 1;
 971         connector->doublescan_allowed = 0;
 972         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 973
 974         intel_encoder->cloneable = false;
 975
 976         intel_hdmi->ddi_port = port;
 977         switch (port) {
 978         case PORT_B:
 979                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 980                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 981                 break;
 982         case PORT_C:
 983                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 984                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 985                 break;
 986         case PORT_D:
 987                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 988                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 989                 break;
 990         case PORT_A:
 991                 /* Internal port only for eDP. */
 992         default:
 993                 BUG();
 994         }
 995
 996         intel_hdmi->sdvox_reg = sdvox_reg;
 997
 998         if (!HAS_PCH_SPLIT(dev)) {
 999                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1000                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1001         } else if (IS_VALLEYVIEW(dev)) {
1002                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1003                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1004         } else if (IS_HASWELL(dev)) {
1005                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1006                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1007         } else if (HAS_PCH_IBX(dev)) {
1008                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1009                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1010         } else {
1011                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1012                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1013         }
1014
1015         if (IS_HASWELL(dev)) {
1016                 intel_encoder->enable = intel_enable_ddi;
1017                 intel_encoder->disable = intel_disable_ddi;
1018                 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1019                 drm_encoder_helper_add(&intel_encoder->base,
1020                                        &intel_hdmi_helper_funcs_hsw);
1021         } else {
1022                 intel_encoder->enable = intel_enable_hdmi;
1023                 intel_encoder->disable = intel_disable_hdmi;
1024                 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1025                 drm_encoder_helper_add(&intel_encoder->base,
1026                                        &intel_hdmi_helper_funcs);
1027         }
1028         intel_connector->get_hw_state = intel_connector_get_hw_state;
1029
1030
1031         intel_hdmi_add_properties(intel_hdmi, connector);
1032
1033         intel_connector_attach_encoder(intel_connector, intel_encoder);
1034         drm_sysfs_connector_add(connector);
1035
1036         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1037          * 0xd.  Failure to do so will result in spurious interrupts being
1038          * generated on the port when a cable is not attached.
1039          */
1040         if (IS_G4X(dev) && !IS_GM45(dev)) {
1041                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1042                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1043         }
1044 }