drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41 {
  42         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43 }
  44
  45 static void
  46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47 {
  48         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         uint32_t enabled_bits;
  51
  52         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53
  54         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55              "HDMI port enabled, expecting disabled\n");
  56 }
  57
  58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59 {
  60         struct intel_digital_port *intel_dig_port =
  61                 container_of(encoder, struct intel_digital_port, base.base);
  62         return &intel_dig_port->hdmi;
  63 }
  64
  65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66 {
  67         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68 }
  69
  70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71 {
  72         switch (type) {
  73         case HDMI_INFOFRAME_TYPE_AVI:
  74                 return VIDEO_DIP_SELECT_AVI;
  75         case HDMI_INFOFRAME_TYPE_SPD:
  76                 return VIDEO_DIP_SELECT_SPD;
  77         case HDMI_INFOFRAME_TYPE_VENDOR:
  78                 return VIDEO_DIP_SELECT_VENDOR;
  79         default:
  80                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  81                 return 0;
  82         }
  83 }
  84
  85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  86 {
  87         switch (type) {
  88         case HDMI_INFOFRAME_TYPE_AVI:
  89                 return VIDEO_DIP_ENABLE_AVI;
  90         case HDMI_INFOFRAME_TYPE_SPD:
  91                 return VIDEO_DIP_ENABLE_SPD;
  92         case HDMI_INFOFRAME_TYPE_VENDOR:
  93                 return VIDEO_DIP_ENABLE_VENDOR;
  94         default:
  95                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  96                 return 0;
  97         }
  98 }
  99
 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 101 {
 102         switch (type) {
 103         case HDMI_INFOFRAME_TYPE_AVI:
 104                 return VIDEO_DIP_ENABLE_AVI_HSW;
 105         case HDMI_INFOFRAME_TYPE_SPD:
 106                 return VIDEO_DIP_ENABLE_SPD_HSW;
 107         case HDMI_INFOFRAME_TYPE_VENDOR:
 108                 return VIDEO_DIP_ENABLE_VS_HSW;
 109         default:
 110                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 111                 return 0;
 112         }
 113 }
 114
 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 116                                   enum transcoder cpu_transcoder,
 117                                   struct drm_i915_private *dev_priv)
 118 {
 119         switch (type) {
 120         case HDMI_INFOFRAME_TYPE_AVI:
 121                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 122         case HDMI_INFOFRAME_TYPE_SPD:
 123                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 124         case HDMI_INFOFRAME_TYPE_VENDOR:
 125                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 126         default:
 127                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 128                 return 0;
 129         }
 130 }
 131
 132 static void g4x_write_infoframe(struct drm_encoder *encoder,
 133                                 enum hdmi_infoframe_type type,
 134                                 const void *frame, ssize_t len)
 135 {
 136         const uint32_t *data = frame;
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         u32 val = I915_READ(VIDEO_DIP_CTL);
 140         int i;
 141
 142         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 143
 144         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 145         val |= g4x_infoframe_index(type);
 146
 147         val &= ~g4x_infoframe_enable(type);
 148
 149         I915_WRITE(VIDEO_DIP_CTL, val);
 150
 151         mmiowb();
 152         for (i = 0; i < len; i += 4) {
 153                 I915_WRITE(VIDEO_DIP_DATA, *data);
 154                 data++;
 155         }
 156         /* Write every possible data byte to force correct ECC calculation. */
 157         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 158                 I915_WRITE(VIDEO_DIP_DATA, 0);
 159         mmiowb();
 160
 161         val |= g4x_infoframe_enable(type);
 162         val &= ~VIDEO_DIP_FREQ_MASK;
 163         val |= VIDEO_DIP_FREQ_VSYNC;
 164
 165         I915_WRITE(VIDEO_DIP_CTL, val);
 166         POSTING_READ(VIDEO_DIP_CTL);
 167 }
 168
 169 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
 170 {
 171         struct drm_device *dev = encoder->dev;
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 174         u32 val = I915_READ(VIDEO_DIP_CTL);
 175
 176         if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
 177                 return val & VIDEO_DIP_ENABLE;
 178
 179         return false;
 180 }
 181
 182 static void ibx_write_infoframe(struct drm_encoder *encoder,
 183                                 enum hdmi_infoframe_type type,
 184                                 const void *frame, ssize_t len)
 185 {
 186         const uint32_t *data = frame;
 187         struct drm_device *dev = encoder->dev;
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 190         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 191         u32 val = I915_READ(reg);
 192
 193         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 194
 195         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 196         val |= g4x_infoframe_index(type);
 197
 198         val &= ~g4x_infoframe_enable(type);
 199
 200         I915_WRITE(reg, val);
 201
 202         mmiowb();
 203         for (i = 0; i < len; i += 4) {
 204                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 205                 data++;
 206         }
 207         /* Write every possible data byte to force correct ECC calculation. */
 208         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 209                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 210         mmiowb();
 211
 212         val |= g4x_infoframe_enable(type);
 213         val &= ~VIDEO_DIP_FREQ_MASK;
 214         val |= VIDEO_DIP_FREQ_VSYNC;
 215
 216         I915_WRITE(reg, val);
 217         POSTING_READ(reg);
 218 }
 219
 220 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 221 {
 222         struct drm_device *dev = encoder->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 225         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 226         u32 val = I915_READ(reg);
 227
 228         return val & VIDEO_DIP_ENABLE;
 229 }
 230
 231 static void cpt_write_infoframe(struct drm_encoder *encoder,
 232                                 enum hdmi_infoframe_type type,
 233                                 const void *frame, ssize_t len)
 234 {
 235         const uint32_t *data = frame;
 236         struct drm_device *dev = encoder->dev;
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 239         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 240         u32 val = I915_READ(reg);
 241
 242         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 243
 244         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 245         val |= g4x_infoframe_index(type);
 246
 247         /* The DIP control register spec says that we need to update the AVI
 248          * infoframe without clearing its enable bit */
 249         if (type != HDMI_INFOFRAME_TYPE_AVI)
 250                 val &= ~g4x_infoframe_enable(type);
 251
 252         I915_WRITE(reg, val);
 253
 254         mmiowb();
 255         for (i = 0; i < len; i += 4) {
 256                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 257                 data++;
 258         }
 259         /* Write every possible data byte to force correct ECC calculation. */
 260         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 261                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 262         mmiowb();
 263
 264         val |= g4x_infoframe_enable(type);
 265         val &= ~VIDEO_DIP_FREQ_MASK;
 266         val |= VIDEO_DIP_FREQ_VSYNC;
 267
 268         I915_WRITE(reg, val);
 269         POSTING_READ(reg);
 270 }
 271
 272 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 273 {
 274         struct drm_device *dev = encoder->dev;
 275         struct drm_i915_private *dev_priv = dev->dev_private;
 276         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 277         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 278         u32 val = I915_READ(reg);
 279
 280         return val & VIDEO_DIP_ENABLE;
 281 }
 282
 283 static void vlv_write_infoframe(struct drm_encoder *encoder,
 284                                 enum hdmi_infoframe_type type,
 285                                 const void *frame, ssize_t len)
 286 {
 287         const uint32_t *data = frame;
 288         struct drm_device *dev = encoder->dev;
 289         struct drm_i915_private *dev_priv = dev->dev_private;
 290         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 291         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 292         u32 val = I915_READ(reg);
 293
 294         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 295
 296         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 297         val |= g4x_infoframe_index(type);
 298
 299         val &= ~g4x_infoframe_enable(type);
 300
 301         I915_WRITE(reg, val);
 302
 303         mmiowb();
 304         for (i = 0; i < len; i += 4) {
 305                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 306                 data++;
 307         }
 308         /* Write every possible data byte to force correct ECC calculation. */
 309         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 310                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 311         mmiowb();
 312
 313         val |= g4x_infoframe_enable(type);
 314         val &= ~VIDEO_DIP_FREQ_MASK;
 315         val |= VIDEO_DIP_FREQ_VSYNC;
 316
 317         I915_WRITE(reg, val);
 318         POSTING_READ(reg);
 319 }
 320
 321 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 322 {
 323         struct drm_device *dev = encoder->dev;
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 326         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 327         u32 val = I915_READ(reg);
 328
 329         return val & VIDEO_DIP_ENABLE;
 330 }
 331
 332 static void hsw_write_infoframe(struct drm_encoder *encoder,
 333                                 enum hdmi_infoframe_type type,
 334                                 const void *frame, ssize_t len)
 335 {
 336         const uint32_t *data = frame;
 337         struct drm_device *dev = encoder->dev;
 338         struct drm_i915_private *dev_priv = dev->dev_private;
 339         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 340         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 341         u32 data_reg;
 342         int i;
 343         u32 val = I915_READ(ctl_reg);
 344
 345         data_reg = hsw_infoframe_data_reg(type,
 346                                           intel_crtc->config.cpu_transcoder,
 347                                           dev_priv);
 348         if (data_reg == 0)
 349                 return;
 350
 351         val &= ~hsw_infoframe_enable(type);
 352         I915_WRITE(ctl_reg, val);
 353
 354         mmiowb();
 355         for (i = 0; i < len; i += 4) {
 356                 I915_WRITE(data_reg + i, *data);
 357                 data++;
 358         }
 359         /* Write every possible data byte to force correct ECC calculation. */
 360         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 361                 I915_WRITE(data_reg + i, 0);
 362         mmiowb();
 363
 364         val |= hsw_infoframe_enable(type);
 365         I915_WRITE(ctl_reg, val);
 366         POSTING_READ(ctl_reg);
 367 }
 368
 369 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 370 {
 371         struct drm_device *dev = encoder->dev;
 372         struct drm_i915_private *dev_priv = dev->dev_private;
 373         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 374         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 375         u32 val = I915_READ(ctl_reg);
 376
 377         return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
 378                       VIDEO_DIP_ENABLE_VS_HSW);
 379 }
 380
 381 /*
 382  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 383  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 384  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 385  * used for both technologies.
 386  *
 387  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 388  * DW1:       DB3       | DB2 | DB1 | DB0
 389  * DW2:       DB7       | DB6 | DB5 | DB4
 390  * DW3: ...
 391  *
 392  * (HB is Header Byte, DB is Data Byte)
 393  *
 394  * The hdmi pack() functions don't know about that hardware specific hole so we
 395  * trick them by giving an offset into the buffer and moving back the header
 396  * bytes by one.
 397  */
 398 static void intel_write_infoframe(struct drm_encoder *encoder,
 399                                   union hdmi_infoframe *frame)
 400 {
 401         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 402         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 403         ssize_t len;
 404
 405         /* see comment above for the reason for this offset */
 406         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 407         if (len < 0)
 408                 return;
 409
 410         /* Insert the 'hole' (see big comment above) at position 3 */
 411         buffer[0] = buffer[1];
 412         buffer[1] = buffer[2];
 413         buffer[2] = buffer[3];
 414         buffer[3] = 0;
 415         len++;
 416
 417         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 418 }
 419
 420 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 421                                          struct drm_display_mode *adjusted_mode)
 422 {
 423         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 424         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 425         union hdmi_infoframe frame;
 426         int ret;
 427
 428         /* Set user selected PAR to incoming mode's member */
 429         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 430
 431         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 432                                                        adjusted_mode);
 433         if (ret < 0) {
 434                 DRM_ERROR("couldn't fill AVI infoframe\n");
 435                 return;
 436         }
 437
 438         if (intel_hdmi->rgb_quant_range_selectable) {
 439                 if (intel_crtc->config.limited_color_range)
 440                         frame.avi.quantization_range =
 441                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 442                 else
 443                         frame.avi.quantization_range =
 444                                 HDMI_QUANTIZATION_RANGE_FULL;
 445         }
 446
 447         intel_write_infoframe(encoder, &frame);
 448 }
 449
 450 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 451 {
 452         union hdmi_infoframe frame;
 453         int ret;
 454
 455         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 456         if (ret < 0) {
 457                 DRM_ERROR("couldn't fill SPD infoframe\n");
 458                 return;
 459         }
 460
 461         frame.spd.sdi = HDMI_SPD_SDI_PC;
 462
 463         intel_write_infoframe(encoder, &frame);
 464 }
 465
 466 static void
 467 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 468                               struct drm_display_mode *adjusted_mode)
 469 {
 470         union hdmi_infoframe frame;
 471         int ret;
 472
 473         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 474                                                           adjusted_mode);
 475         if (ret < 0)
 476                 return;
 477
 478         intel_write_infoframe(encoder, &frame);
 479 }
 480
 481 static void g4x_set_infoframes(struct drm_encoder *encoder,
 482                                bool enable,
 483                                struct drm_display_mode *adjusted_mode)
 484 {
 485         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 486         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 487         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 488         u32 reg = VIDEO_DIP_CTL;
 489         u32 val = I915_READ(reg);
 490         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 491
 492         assert_hdmi_port_disabled(intel_hdmi);
 493
 494         /* If the registers were not initialized yet, they might be zeroes,
 495          * which means we're selecting the AVI DIP and we're setting its
 496          * frequency to once. This seems to really confuse the HW and make
 497          * things stop working (the register spec says the AVI always needs to
 498          * be sent every VSync). So here we avoid writing to the register more
 499          * than we need and also explicitly select the AVI DIP and explicitly
 500          * set its frequency to every VSync. Avoiding to write it twice seems to
 501          * be enough to solve the problem, but being defensive shouldn't hurt us
 502          * either. */
 503         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 504
 505         if (!enable) {
 506                 if (!(val & VIDEO_DIP_ENABLE))
 507                         return;
 508                 val &= ~VIDEO_DIP_ENABLE;
 509                 I915_WRITE(reg, val);
 510                 POSTING_READ(reg);
 511                 return;
 512         }
 513
 514         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 515                 if (val & VIDEO_DIP_ENABLE) {
 516                         val &= ~VIDEO_DIP_ENABLE;
 517                         I915_WRITE(reg, val);
 518                         POSTING_READ(reg);
 519                 }
 520                 val &= ~VIDEO_DIP_PORT_MASK;
 521                 val |= port;
 522         }
 523
 524         val |= VIDEO_DIP_ENABLE;
 525         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 526
 527         I915_WRITE(reg, val);
 528         POSTING_READ(reg);
 529
 530         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 531         intel_hdmi_set_spd_infoframe(encoder);
 532         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 533 }
 534
 535 static void ibx_set_infoframes(struct drm_encoder *encoder,
 536                                bool enable,
 537                                struct drm_display_mode *adjusted_mode)
 538 {
 539         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 540         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 541         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 542         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 543         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 544         u32 val = I915_READ(reg);
 545         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 546
 547         assert_hdmi_port_disabled(intel_hdmi);
 548
 549         /* See the big comment in g4x_set_infoframes() */
 550         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 551
 552         if (!enable) {
 553                 if (!(val & VIDEO_DIP_ENABLE))
 554                         return;
 555                 val &= ~VIDEO_DIP_ENABLE;
 556                 I915_WRITE(reg, val);
 557                 POSTING_READ(reg);
 558                 return;
 559         }
 560
 561         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 562                 if (val & VIDEO_DIP_ENABLE) {
 563                         val &= ~VIDEO_DIP_ENABLE;
 564                         I915_WRITE(reg, val);
 565                         POSTING_READ(reg);
 566                 }
 567                 val &= ~VIDEO_DIP_PORT_MASK;
 568                 val |= port;
 569         }
 570
 571         val |= VIDEO_DIP_ENABLE;
 572         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 573                  VIDEO_DIP_ENABLE_GCP);
 574
 575         I915_WRITE(reg, val);
 576         POSTING_READ(reg);
 577
 578         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 579         intel_hdmi_set_spd_infoframe(encoder);
 580         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 581 }
 582
 583 static void cpt_set_infoframes(struct drm_encoder *encoder,
 584                                bool enable,
 585                                struct drm_display_mode *adjusted_mode)
 586 {
 587         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 588         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 589         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 590         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 591         u32 val = I915_READ(reg);
 592
 593         assert_hdmi_port_disabled(intel_hdmi);
 594
 595         /* See the big comment in g4x_set_infoframes() */
 596         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 597
 598         if (!enable) {
 599                 if (!(val & VIDEO_DIP_ENABLE))
 600                         return;
 601                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 602                 I915_WRITE(reg, val);
 603                 POSTING_READ(reg);
 604                 return;
 605         }
 606
 607         /* Set both together, unset both together: see the spec. */
 608         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 609         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 610                  VIDEO_DIP_ENABLE_GCP);
 611
 612         I915_WRITE(reg, val);
 613         POSTING_READ(reg);
 614
 615         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 616         intel_hdmi_set_spd_infoframe(encoder);
 617         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 618 }
 619
 620 static void vlv_set_infoframes(struct drm_encoder *encoder,
 621                                bool enable,
 622                                struct drm_display_mode *adjusted_mode)
 623 {
 624         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 625         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 626         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 627         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 628         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 629         u32 val = I915_READ(reg);
 630         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 631
 632         assert_hdmi_port_disabled(intel_hdmi);
 633
 634         /* See the big comment in g4x_set_infoframes() */
 635         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 636
 637         if (!enable) {
 638                 if (!(val & VIDEO_DIP_ENABLE))
 639                         return;
 640                 val &= ~VIDEO_DIP_ENABLE;
 641                 I915_WRITE(reg, val);
 642                 POSTING_READ(reg);
 643                 return;
 644         }
 645
 646         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 647                 if (val & VIDEO_DIP_ENABLE) {
 648                         val &= ~VIDEO_DIP_ENABLE;
 649                         I915_WRITE(reg, val);
 650                         POSTING_READ(reg);
 651                 }
 652                 val &= ~VIDEO_DIP_PORT_MASK;
 653                 val |= port;
 654         }
 655
 656         val |= VIDEO_DIP_ENABLE;
 657         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 658                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 659
 660         I915_WRITE(reg, val);
 661         POSTING_READ(reg);
 662
 663         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 664         intel_hdmi_set_spd_infoframe(encoder);
 665         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 666 }
 667
 668 static void hsw_set_infoframes(struct drm_encoder *encoder,
 669                                bool enable,
 670                                struct drm_display_mode *adjusted_mode)
 671 {
 672         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 673         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 674         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 675         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 676         u32 val = I915_READ(reg);
 677
 678         assert_hdmi_port_disabled(intel_hdmi);
 679
 680         if (!enable) {
 681                 I915_WRITE(reg, 0);
 682                 POSTING_READ(reg);
 683                 return;
 684         }
 685
 686         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 687                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 688
 689         I915_WRITE(reg, val);
 690         POSTING_READ(reg);
 691
 692         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 693         intel_hdmi_set_spd_infoframe(encoder);
 694         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 695 }
 696
 697 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 698 {
 699         struct drm_device *dev = encoder->base.dev;
 700         struct drm_i915_private *dev_priv = dev->dev_private;
 701         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 702         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 703         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 704         u32 hdmi_val;
 705
 706         hdmi_val = SDVO_ENCODING_HDMI;
 707         if (!HAS_PCH_SPLIT(dev))
 708                 hdmi_val |= intel_hdmi->color_range;
 709         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 710                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 711         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 712                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 713
 714         if (crtc->config.pipe_bpp > 24)
 715                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 716         else
 717                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 718
 719         if (crtc->config.has_hdmi_sink)
 720                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 721
 722         if (HAS_PCH_CPT(dev))
 723                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 724         else if (IS_CHERRYVIEW(dev))
 725                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 726         else
 727                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 728
 729         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 730         POSTING_READ(intel_hdmi->hdmi_reg);
 731 }
 732
 733 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 734                                     enum pipe *pipe)
 735 {
 736         struct drm_device *dev = encoder->base.dev;
 737         struct drm_i915_private *dev_priv = dev->dev_private;
 738         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 739         enum intel_display_power_domain power_domain;
 740         u32 tmp;
 741
 742         power_domain = intel_display_port_power_domain(encoder);
 743         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 744                 return false;
 745
 746         tmp = I915_READ(intel_hdmi->hdmi_reg);
 747
 748         if (!(tmp & SDVO_ENABLE))
 749                 return false;
 750
 751         if (HAS_PCH_CPT(dev))
 752                 *pipe = PORT_TO_PIPE_CPT(tmp);
 753         else if (IS_CHERRYVIEW(dev))
 754                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 755         else
 756                 *pipe = PORT_TO_PIPE(tmp);
 757
 758         return true;
 759 }
 760
 761 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 762                                   struct intel_crtc_config *pipe_config)
 763 {
 764         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 765         struct drm_device *dev = encoder->base.dev;
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         u32 tmp, flags = 0;
 768         int dotclock;
 769
 770         tmp = I915_READ(intel_hdmi->hdmi_reg);
 771
 772         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 773                 flags |= DRM_MODE_FLAG_PHSYNC;
 774         else
 775                 flags |= DRM_MODE_FLAG_NHSYNC;
 776
 777         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 778                 flags |= DRM_MODE_FLAG_PVSYNC;
 779         else
 780                 flags |= DRM_MODE_FLAG_NVSYNC;
 781
 782         if (tmp & HDMI_MODE_SELECT_HDMI)
 783                 pipe_config->has_hdmi_sink = true;
 784
 785         if (intel_hdmi->infoframe_enabled(&encoder->base))
 786                 pipe_config->has_infoframe = true;
 787
 788         if (tmp & SDVO_AUDIO_ENABLE)
 789                 pipe_config->has_audio = true;
 790
 791         if (!HAS_PCH_SPLIT(dev) &&
 792             tmp & HDMI_COLOR_RANGE_16_235)
 793                 pipe_config->limited_color_range = true;
 794
 795         pipe_config->adjusted_mode.flags |= flags;
 796
 797         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 798                 dotclock = pipe_config->port_clock * 2 / 3;
 799         else
 800                 dotclock = pipe_config->port_clock;
 801
 802         if (HAS_PCH_SPLIT(dev_priv->dev))
 803                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 804
 805         pipe_config->adjusted_mode.crtc_clock = dotclock;
 806 }
 807
 808 static void intel_enable_hdmi(struct intel_encoder *encoder)
 809 {
 810         struct drm_device *dev = encoder->base.dev;
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 813         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 814         u32 temp;
 815         u32 enable_bits = SDVO_ENABLE;
 816
 817         if (intel_crtc->config.has_audio)
 818                 enable_bits |= SDVO_AUDIO_ENABLE;
 819
 820         temp = I915_READ(intel_hdmi->hdmi_reg);
 821
 822         /* HW workaround for IBX, we need to move the port to transcoder A
 823          * before disabling it, so restore the transcoder select bit here. */
 824         if (HAS_PCH_IBX(dev))
 825                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 826
 827         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 828          * we do this anyway which shows more stable in testing.
 829          */
 830         if (HAS_PCH_SPLIT(dev)) {
 831                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 832                 POSTING_READ(intel_hdmi->hdmi_reg);
 833         }
 834
 835         temp |= enable_bits;
 836
 837         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 838         POSTING_READ(intel_hdmi->hdmi_reg);
 839
 840         /* HW workaround, need to write this twice for issue that may result
 841          * in first write getting masked.
 842          */
 843         if (HAS_PCH_SPLIT(dev)) {
 844                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 845                 POSTING_READ(intel_hdmi->hdmi_reg);
 846         }
 847
 848         if (intel_crtc->config.has_audio) {
 849                 WARN_ON(!intel_crtc->config.has_hdmi_sink);
 850                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 851                                  pipe_name(intel_crtc->pipe));
 852                 intel_audio_codec_enable(encoder);
 853         }
 854 }
 855
 856 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 857 {
 858 }
 859
 860 static void intel_disable_hdmi(struct intel_encoder *encoder)
 861 {
 862         struct drm_device *dev = encoder->base.dev;
 863         struct drm_i915_private *dev_priv = dev->dev_private;
 864         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 865         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 866         u32 temp;
 867         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 868
 869         if (crtc->config.has_audio)
 870                 intel_audio_codec_disable(encoder);
 871
 872         temp = I915_READ(intel_hdmi->hdmi_reg);
 873
 874         /* HW workaround for IBX, we need to move the port to transcoder A
 875          * before disabling it. */
 876         if (HAS_PCH_IBX(dev)) {
 877                 struct drm_crtc *crtc = encoder->base.crtc;
 878                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 879
 880                 if (temp & SDVO_PIPE_B_SELECT) {
 881                         temp &= ~SDVO_PIPE_B_SELECT;
 882                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 883                         POSTING_READ(intel_hdmi->hdmi_reg);
 884
 885                         /* Again we need to write this twice. */
 886                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 887                         POSTING_READ(intel_hdmi->hdmi_reg);
 888
 889                         /* Transcoder selection bits only update
 890                          * effectively on vblank. */
 891                         if (crtc)
 892                                 intel_wait_for_vblank(dev, pipe);
 893                         else
 894                                 msleep(50);
 895                 }
 896         }
 897
 898         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 899          * we do this anyway which shows more stable in testing.
 900          */
 901         if (HAS_PCH_SPLIT(dev)) {
 902                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 903                 POSTING_READ(intel_hdmi->hdmi_reg);
 904         }
 905
 906         temp &= ~enable_bits;
 907
 908         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 909         POSTING_READ(intel_hdmi->hdmi_reg);
 910
 911         /* HW workaround, need to write this twice for issue that may result
 912          * in first write getting masked.
 913          */
 914         if (HAS_PCH_SPLIT(dev)) {
 915                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 916                 POSTING_READ(intel_hdmi->hdmi_reg);
 917         }
 918 }
 919
 920 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 921 {
 922         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 923
 924         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 925                 return 165000;
 926         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 927                 return 300000;
 928         else
 929                 return 225000;
 930 }
 931
 932 static enum drm_mode_status
 933 intel_hdmi_mode_valid(struct drm_connector *connector,
 934                       struct drm_display_mode *mode)
 935 {
 936         int clock = mode->clock;
 937
 938         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 939                 clock *= 2;
 940
 941         if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 942                                          true))
 943                 return MODE_CLOCK_HIGH;
 944         if (clock < 20000)
 945                 return MODE_CLOCK_LOW;
 946
 947         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 948                 return MODE_NO_DBLESCAN;
 949
 950         return MODE_OK;
 951 }
 952
 953 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
 954 {
 955         struct drm_device *dev = crtc->base.dev;
 956         struct intel_encoder *encoder;
 957         int count = 0, count_hdmi = 0;
 958
 959         if (HAS_GMCH_DISPLAY(dev))
 960                 return false;
 961
 962         for_each_intel_encoder(dev, encoder) {
 963                 if (encoder->new_crtc != crtc)
 964                         continue;
 965
 966                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 967                 count++;
 968         }
 969
 970         /*
 971          * HDMI 12bpc affects the clocks, so it's only possible
 972          * when not cloning with other encoder types.
 973          */
 974         return count_hdmi > 0 && count_hdmi == count;
 975 }
 976
 977 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 978                                struct intel_crtc_config *pipe_config)
 979 {
 980         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 981         struct drm_device *dev = encoder->base.dev;
 982         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 983         int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
 984         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
 985         int desired_bpp;
 986
 987         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
 988
 989         if (pipe_config->has_hdmi_sink)
 990                 pipe_config->has_infoframe = true;
 991
 992         if (intel_hdmi->color_range_auto) {
 993                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 994                 if (pipe_config->has_hdmi_sink &&
 995                     drm_match_cea_mode(adjusted_mode) > 1)
 996                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 997                 else
 998                         intel_hdmi->color_range = 0;
 999         }
1000
1001         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1002                 pipe_config->pixel_multiplier = 2;
1003         }
1004
1005         if (intel_hdmi->color_range)
1006                 pipe_config->limited_color_range = true;
1007
1008         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1009                 pipe_config->has_pch_encoder = true;
1010
1011         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1012                 pipe_config->has_audio = true;
1013
1014         /*
1015          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1016          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1017          * outputs. We also need to check that the higher clock still fits
1018          * within limits.
1019          */
1020         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1021             clock_12bpc <= portclock_limit &&
1022             hdmi_12bpc_possible(encoder->new_crtc)) {
1023                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1024                 desired_bpp = 12*3;
1025
1026                 /* Need to adjust the port link by 1.5x for 12bpc. */
1027                 pipe_config->port_clock = clock_12bpc;
1028         } else {
1029                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1030                 desired_bpp = 8*3;
1031         }
1032
1033         if (!pipe_config->bw_constrained) {
1034                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1035                 pipe_config->pipe_bpp = desired_bpp;
1036         }
1037
1038         if (adjusted_mode->crtc_clock > portclock_limit) {
1039                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1040                 return false;
1041         }
1042
1043         return true;
1044 }
1045
1046 static void
1047 intel_hdmi_unset_edid(struct drm_connector *connector)
1048 {
1049         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1050
1051         intel_hdmi->has_hdmi_sink = false;
1052         intel_hdmi->has_audio = false;
1053         intel_hdmi->rgb_quant_range_selectable = false;
1054
1055         kfree(to_intel_connector(connector)->detect_edid);
1056         to_intel_connector(connector)->detect_edid = NULL;
1057 }
1058
1059 static bool
1060 intel_hdmi_set_edid(struct drm_connector *connector)
1061 {
1062         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1063         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1064         struct intel_encoder *intel_encoder =
1065                 &hdmi_to_dig_port(intel_hdmi)->base;
1066         enum intel_display_power_domain power_domain;
1067         struct edid *edid;
1068         bool connected = false;
1069
1070         power_domain = intel_display_port_power_domain(intel_encoder);
1071         intel_display_power_get(dev_priv, power_domain);
1072
1073         edid = drm_get_edid(connector,
1074                             intel_gmbus_get_adapter(dev_priv,
1075                                                     intel_hdmi->ddc_bus));
1076
1077         intel_display_power_put(dev_priv, power_domain);
1078
1079         to_intel_connector(connector)->detect_edid = edid;
1080         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1081                 intel_hdmi->rgb_quant_range_selectable =
1082                         drm_rgb_quant_range_selectable(edid);
1083
1084                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1085                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1086                         intel_hdmi->has_audio =
1087                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1088
1089                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1090                         intel_hdmi->has_hdmi_sink =
1091                                 drm_detect_hdmi_monitor(edid);
1092
1093                 connected = true;
1094         }
1095
1096         return connected;
1097 }
1098
1099 static enum drm_connector_status
1100 intel_hdmi_detect(struct drm_connector *connector, bool force)
1101 {
1102         enum drm_connector_status status;
1103
1104         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1105                       connector->base.id, connector->name);
1106
1107         intel_hdmi_unset_edid(connector);
1108
1109         if (intel_hdmi_set_edid(connector)) {
1110                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1111
1112                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1113                 status = connector_status_connected;
1114         } else
1115                 status = connector_status_disconnected;
1116
1117         return status;
1118 }
1119
1120 static void
1121 intel_hdmi_force(struct drm_connector *connector)
1122 {
1123         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1124
1125         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1126                       connector->base.id, connector->name);
1127
1128         intel_hdmi_unset_edid(connector);
1129
1130         if (connector->status != connector_status_connected)
1131                 return;
1132
1133         intel_hdmi_set_edid(connector);
1134         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1135 }
1136
1137 static int intel_hdmi_get_modes(struct drm_connector *connector)
1138 {
1139         struct edid *edid;
1140
1141         edid = to_intel_connector(connector)->detect_edid;
1142         if (edid == NULL)
1143                 return 0;
1144
1145         return intel_connector_update_modes(connector, edid);
1146 }
1147
1148 static bool
1149 intel_hdmi_detect_audio(struct drm_connector *connector)
1150 {
1151         bool has_audio = false;
1152         struct edid *edid;
1153
1154         edid = to_intel_connector(connector)->detect_edid;
1155         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1156                 has_audio = drm_detect_monitor_audio(edid);
1157
1158         return has_audio;
1159 }
1160
1161 static int
1162 intel_hdmi_set_property(struct drm_connector *connector,
1163                         struct drm_property *property,
1164                         uint64_t val)
1165 {
1166         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1167         struct intel_digital_port *intel_dig_port =
1168                 hdmi_to_dig_port(intel_hdmi);
1169         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1170         int ret;
1171
1172         ret = drm_object_property_set_value(&connector->base, property, val);
1173         if (ret)
1174                 return ret;
1175
1176         if (property == dev_priv->force_audio_property) {
1177                 enum hdmi_force_audio i = val;
1178                 bool has_audio;
1179
1180                 if (i == intel_hdmi->force_audio)
1181                         return 0;
1182
1183                 intel_hdmi->force_audio = i;
1184
1185                 if (i == HDMI_AUDIO_AUTO)
1186                         has_audio = intel_hdmi_detect_audio(connector);
1187                 else
1188                         has_audio = (i == HDMI_AUDIO_ON);
1189
1190                 if (i == HDMI_AUDIO_OFF_DVI)
1191                         intel_hdmi->has_hdmi_sink = 0;
1192
1193                 intel_hdmi->has_audio = has_audio;
1194                 goto done;
1195         }
1196
1197         if (property == dev_priv->broadcast_rgb_property) {
1198                 bool old_auto = intel_hdmi->color_range_auto;
1199                 uint32_t old_range = intel_hdmi->color_range;
1200
1201                 switch (val) {
1202                 case INTEL_BROADCAST_RGB_AUTO:
1203                         intel_hdmi->color_range_auto = true;
1204                         break;
1205                 case INTEL_BROADCAST_RGB_FULL:
1206                         intel_hdmi->color_range_auto = false;
1207                         intel_hdmi->color_range = 0;
1208                         break;
1209                 case INTEL_BROADCAST_RGB_LIMITED:
1210                         intel_hdmi->color_range_auto = false;
1211                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1212                         break;
1213                 default:
1214                         return -EINVAL;
1215                 }
1216
1217                 if (old_auto == intel_hdmi->color_range_auto &&
1218                     old_range == intel_hdmi->color_range)
1219                         return 0;
1220
1221                 goto done;
1222         }
1223
1224         if (property == connector->dev->mode_config.aspect_ratio_property) {
1225                 switch (val) {
1226                 case DRM_MODE_PICTURE_ASPECT_NONE:
1227                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1228                         break;
1229                 case DRM_MODE_PICTURE_ASPECT_4_3:
1230                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1231                         break;
1232                 case DRM_MODE_PICTURE_ASPECT_16_9:
1233                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1234                         break;
1235                 default:
1236                         return -EINVAL;
1237                 }
1238                 goto done;
1239         }
1240
1241         return -EINVAL;
1242
1243 done:
1244         if (intel_dig_port->base.base.crtc)
1245                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1246
1247         return 0;
1248 }
1249
1250 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1251 {
1252         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1253         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1254         struct drm_display_mode *adjusted_mode =
1255                 &intel_crtc->config.adjusted_mode;
1256
1257         intel_hdmi_prepare(encoder);
1258
1259         intel_hdmi->set_infoframes(&encoder->base,
1260                                    intel_crtc->config.has_hdmi_sink,
1261                                    adjusted_mode);
1262 }
1263
1264 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1265 {
1266         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1267         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1268         struct drm_device *dev = encoder->base.dev;
1269         struct drm_i915_private *dev_priv = dev->dev_private;
1270         struct intel_crtc *intel_crtc =
1271                 to_intel_crtc(encoder->base.crtc);
1272         struct drm_display_mode *adjusted_mode =
1273                 &intel_crtc->config.adjusted_mode;
1274         enum dpio_channel port = vlv_dport_to_channel(dport);
1275         int pipe = intel_crtc->pipe;
1276         u32 val;
1277
1278         /* Enable clock channels for this port */
1279         mutex_lock(&dev_priv->dpio_lock);
1280         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1281         val = 0;
1282         if (pipe)
1283                 val |= (1<<21);
1284         else
1285                 val &= ~(1<<21);
1286         val |= 0x001000c4;
1287         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1288
1289         /* HDMI 1.0V-2dB */
1290         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1291         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1292         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1293         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1294         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1295         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1296         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1297         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1298
1299         /* Program lane clock */
1300         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1301         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1302         mutex_unlock(&dev_priv->dpio_lock);
1303
1304         intel_hdmi->set_infoframes(&encoder->base,
1305                                    intel_crtc->config.has_hdmi_sink,
1306                                    adjusted_mode);
1307
1308         intel_enable_hdmi(encoder);
1309
1310         vlv_wait_port_ready(dev_priv, dport);
1311 }
1312
1313 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1314 {
1315         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1316         struct drm_device *dev = encoder->base.dev;
1317         struct drm_i915_private *dev_priv = dev->dev_private;
1318         struct intel_crtc *intel_crtc =
1319                 to_intel_crtc(encoder->base.crtc);
1320         enum dpio_channel port = vlv_dport_to_channel(dport);
1321         int pipe = intel_crtc->pipe;
1322
1323         intel_hdmi_prepare(encoder);
1324
1325         /* Program Tx lane resets to default */
1326         mutex_lock(&dev_priv->dpio_lock);
1327         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1328                          DPIO_PCS_TX_LANE2_RESET |
1329                          DPIO_PCS_TX_LANE1_RESET);
1330         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1331                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1332                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1333                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1334                          DPIO_PCS_CLK_SOFT_RESET);
1335
1336         /* Fix up inter-pair skew failure */
1337         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1338         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1339         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1340
1341         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1342         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1343         mutex_unlock(&dev_priv->dpio_lock);
1344 }
1345
1346 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1347 {
1348         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1349         struct drm_device *dev = encoder->base.dev;
1350         struct drm_i915_private *dev_priv = dev->dev_private;
1351         struct intel_crtc *intel_crtc =
1352                 to_intel_crtc(encoder->base.crtc);
1353         enum dpio_channel ch = vlv_dport_to_channel(dport);
1354         enum pipe pipe = intel_crtc->pipe;
1355         u32 val;
1356
1357         intel_hdmi_prepare(encoder);
1358
1359         mutex_lock(&dev_priv->dpio_lock);
1360
1361         /* program left/right clock distribution */
1362         if (pipe != PIPE_B) {
1363                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1364                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1365                 if (ch == DPIO_CH0)
1366                         val |= CHV_BUFLEFTENA1_FORCE;
1367                 if (ch == DPIO_CH1)
1368                         val |= CHV_BUFRIGHTENA1_FORCE;
1369                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1370         } else {
1371                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1372                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1373                 if (ch == DPIO_CH0)
1374                         val |= CHV_BUFLEFTENA2_FORCE;
1375                 if (ch == DPIO_CH1)
1376                         val |= CHV_BUFRIGHTENA2_FORCE;
1377                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1378         }
1379
1380         /* program clock channel usage */
1381         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1382         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1383         if (pipe != PIPE_B)
1384                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1385         else
1386                 val |= CHV_PCS_USEDCLKCHANNEL;
1387         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1388
1389         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1390         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1391         if (pipe != PIPE_B)
1392                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1393         else
1394                 val |= CHV_PCS_USEDCLKCHANNEL;
1395         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1396
1397         /*
1398          * This a a bit weird since generally CL
1399          * matches the pipe, but here we need to
1400          * pick the CL based on the port.
1401          */
1402         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1403         if (pipe != PIPE_B)
1404                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1405         else
1406                 val |= CHV_CMN_USEDCLKCHANNEL;
1407         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1408
1409         mutex_unlock(&dev_priv->dpio_lock);
1410 }
1411
1412 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1413 {
1414         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1415         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1416         struct intel_crtc *intel_crtc =
1417                 to_intel_crtc(encoder->base.crtc);
1418         enum dpio_channel port = vlv_dport_to_channel(dport);
1419         int pipe = intel_crtc->pipe;
1420
1421         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1422         mutex_lock(&dev_priv->dpio_lock);
1423         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1424         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1425         mutex_unlock(&dev_priv->dpio_lock);
1426 }
1427
1428 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1429 {
1430         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1431         struct drm_device *dev = encoder->base.dev;
1432         struct drm_i915_private *dev_priv = dev->dev_private;
1433         struct intel_crtc *intel_crtc =
1434                 to_intel_crtc(encoder->base.crtc);
1435         enum dpio_channel ch = vlv_dport_to_channel(dport);
1436         enum pipe pipe = intel_crtc->pipe;
1437         u32 val;
1438
1439         mutex_lock(&dev_priv->dpio_lock);
1440
1441         /* Propagate soft reset to data lane reset */
1442         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1443         val |= CHV_PCS_REQ_SOFTRESET_EN;
1444         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1445
1446         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1447         val |= CHV_PCS_REQ_SOFTRESET_EN;
1448         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1449
1450         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1451         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1452         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1453
1454         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1455         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1456         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1457
1458         mutex_unlock(&dev_priv->dpio_lock);
1459 }
1460
1461 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1462 {
1463         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1464         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1465         struct drm_device *dev = encoder->base.dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467         struct intel_crtc *intel_crtc =
1468                 to_intel_crtc(encoder->base.crtc);
1469         struct drm_display_mode *adjusted_mode =
1470                 &intel_crtc->config.adjusted_mode;
1471         enum dpio_channel ch = vlv_dport_to_channel(dport);
1472         int pipe = intel_crtc->pipe;
1473         int data, i;
1474         u32 val;
1475
1476         mutex_lock(&dev_priv->dpio_lock);
1477
1478         /* allow hardware to manage TX FIFO reset source */
1479         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1480         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1481         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1482
1483         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1484         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1485         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1486
1487         /* Deassert soft data lane reset*/
1488         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1489         val |= CHV_PCS_REQ_SOFTRESET_EN;
1490         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1491
1492         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1493         val |= CHV_PCS_REQ_SOFTRESET_EN;
1494         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1495
1496         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1497         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1498         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1499
1500         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1501         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1502         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1503
1504         /* Program Tx latency optimal setting */
1505         for (i = 0; i < 4; i++) {
1506                 /* Set the latency optimal bit */
1507                 data = (i == 1) ? 0x0 : 0x6;
1508                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1509                                 data << DPIO_FRC_LATENCY_SHFIT);
1510
1511                 /* Set the upar bit */
1512                 data = (i == 1) ? 0x0 : 0x1;
1513                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1514                                 data << DPIO_UPAR_SHIFT);
1515         }
1516
1517         /* Data lane stagger programming */
1518         /* FIXME: Fix up value only after power analysis */
1519
1520         /* Clear calc init */
1521         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1522         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1523         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1524         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1525         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1526
1527         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1528         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1529         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1530         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1531         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1532
1533         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1534         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1535         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1536         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1537
1538         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1539         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1540         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1541         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1542
1543         /* FIXME: Program the support xxx V-dB */
1544         /* Use 800mV-0dB */
1545         for (i = 0; i < 4; i++) {
1546                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1547                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1548                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1549                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1550         }
1551
1552         for (i = 0; i < 4; i++) {
1553                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1554                 val &= ~DPIO_SWING_MARGIN000_MASK;
1555                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1556                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1557         }
1558
1559         /* Disable unique transition scale */
1560         for (i = 0; i < 4; i++) {
1561                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1562                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1563                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1564         }
1565
1566         /* Additional steps for 1200mV-0dB */
1567 #if 0
1568         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1569         if (ch)
1570                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1571         else
1572                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1573         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1574
1575         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1576                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1577                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1578 #endif
1579         /* Start swing calculation */
1580         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1581         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1582         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1583
1584         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1585         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1586         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1587
1588         /* LRC Bypass */
1589         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1590         val |= DPIO_LRC_BYPASS;
1591         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1592
1593         mutex_unlock(&dev_priv->dpio_lock);
1594
1595         intel_hdmi->set_infoframes(&encoder->base,
1596                                    intel_crtc->config.has_hdmi_sink,
1597                                    adjusted_mode);
1598
1599         intel_enable_hdmi(encoder);
1600
1601         vlv_wait_port_ready(dev_priv, dport);
1602 }
1603
1604 static void intel_hdmi_destroy(struct drm_connector *connector)
1605 {
1606         kfree(to_intel_connector(connector)->detect_edid);
1607         drm_connector_cleanup(connector);
1608         kfree(connector);
1609 }
1610
1611 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1612         .dpms = intel_connector_dpms,
1613         .detect = intel_hdmi_detect,
1614         .force = intel_hdmi_force,
1615         .fill_modes = drm_helper_probe_single_connector_modes,
1616         .set_property = intel_hdmi_set_property,
1617         .destroy = intel_hdmi_destroy,
1618 };
1619
1620 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1621         .get_modes = intel_hdmi_get_modes,
1622         .mode_valid = intel_hdmi_mode_valid,
1623         .best_encoder = intel_best_encoder,
1624 };
1625
1626 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1627         .destroy = intel_encoder_destroy,
1628 };
1629
1630 static void
1631 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1632 {
1633         if (!drm_mode_create_aspect_ratio_property(connector->dev))
1634                 drm_object_attach_property(&connector->base,
1635                         connector->dev->mode_config.aspect_ratio_property,
1636                         DRM_MODE_PICTURE_ASPECT_NONE);
1637 }
1638
1639 static void
1640 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1641 {
1642         intel_attach_force_audio_property(connector);
1643         intel_attach_broadcast_rgb_property(connector);
1644         intel_hdmi->color_range_auto = true;
1645         intel_attach_aspect_ratio_property(connector);
1646         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1647 }
1648
1649 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1650                                struct intel_connector *intel_connector)
1651 {
1652         struct drm_connector *connector = &intel_connector->base;
1653         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1654         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1655         struct drm_device *dev = intel_encoder->base.dev;
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657         enum port port = intel_dig_port->port;
1658
1659         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1660                            DRM_MODE_CONNECTOR_HDMIA);
1661         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1662
1663         connector->interlace_allowed = 1;
1664         connector->doublescan_allowed = 0;
1665         connector->stereo_allowed = 1;
1666
1667         switch (port) {
1668         case PORT_B:
1669                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1670                 intel_encoder->hpd_pin = HPD_PORT_B;
1671                 break;
1672         case PORT_C:
1673                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1674                 intel_encoder->hpd_pin = HPD_PORT_C;
1675                 break;
1676         case PORT_D:
1677                 if (IS_CHERRYVIEW(dev))
1678                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1679                 else
1680                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1681                 intel_encoder->hpd_pin = HPD_PORT_D;
1682                 break;
1683         case PORT_A:
1684                 intel_encoder->hpd_pin = HPD_PORT_A;
1685                 /* Internal port only for eDP. */
1686         default:
1687                 BUG();
1688         }
1689
1690         if (IS_VALLEYVIEW(dev)) {
1691                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1692                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1693                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1694         } else if (IS_G4X(dev)) {
1695                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1696                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1697                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1698         } else if (HAS_DDI(dev)) {
1699                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1700                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1701                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1702         } else if (HAS_PCH_IBX(dev)) {
1703                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1704                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1705                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1706         } else {
1707                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1708                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1709                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1710         }
1711
1712         if (HAS_DDI(dev))
1713                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1714         else
1715                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1716         intel_connector->unregister = intel_connector_unregister;
1717
1718         intel_hdmi_add_properties(intel_hdmi, connector);
1719
1720         intel_connector_attach_encoder(intel_connector, intel_encoder);
1721         drm_connector_register(connector);
1722
1723         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1724          * 0xd.  Failure to do so will result in spurious interrupts being
1725          * generated on the port when a cable is not attached.
1726          */
1727         if (IS_G4X(dev) && !IS_GM45(dev)) {
1728                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1729                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1730         }
1731 }
1732
1733 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1734 {
1735         struct intel_digital_port *intel_dig_port;
1736         struct intel_encoder *intel_encoder;
1737         struct intel_connector *intel_connector;
1738
1739         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1740         if (!intel_dig_port)
1741                 return;
1742
1743         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1744         if (!intel_connector) {
1745                 kfree(intel_dig_port);
1746                 return;
1747         }
1748
1749         intel_encoder = &intel_dig_port->base;
1750
1751         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1752                          DRM_MODE_ENCODER_TMDS);
1753
1754         intel_encoder->compute_config = intel_hdmi_compute_config;
1755         intel_encoder->disable = intel_disable_hdmi;
1756         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1757         intel_encoder->get_config = intel_hdmi_get_config;
1758         if (IS_CHERRYVIEW(dev)) {
1759                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1760                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1761                 intel_encoder->enable = vlv_enable_hdmi;
1762                 intel_encoder->post_disable = chv_hdmi_post_disable;
1763         } else if (IS_VALLEYVIEW(dev)) {
1764                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1765                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1766                 intel_encoder->enable = vlv_enable_hdmi;
1767                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1768         } else {
1769                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1770                 intel_encoder->enable = intel_enable_hdmi;
1771         }
1772
1773         intel_encoder->type = INTEL_OUTPUT_HDMI;
1774         if (IS_CHERRYVIEW(dev)) {
1775                 if (port == PORT_D)
1776                         intel_encoder->crtc_mask = 1 << 2;
1777                 else
1778                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1779         } else {
1780                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1781         }
1782         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1783         /*
1784          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1785          * to work on real hardware. And since g4x can send infoframes to
1786          * only one port anyway, nothing is lost by allowing it.
1787          */
1788         if (IS_G4X(dev))
1789                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1790
1791         intel_dig_port->port = port;
1792         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1793         intel_dig_port->dp.output_reg = 0;
1794
1795         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1796 }