drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42 {
  43         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44 }
  45
  46 static void
  47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48 {
  49         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50         struct drm_i915_private *dev_priv = dev->dev_private;
  51         uint32_t enabled_bits;
  52
  53         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54
  55         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56              "HDMI port enabled, expecting disabled\n");
  57 }
  58
  59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60 {
  61         struct intel_digital_port *intel_dig_port =
  62                 container_of(encoder, struct intel_digital_port, base.base);
  63         return &intel_dig_port->hdmi;
  64 }
  65
  66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67 {
  68         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69 }
  70
  71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72 {
  73         switch (type) {
  74         case HDMI_INFOFRAME_TYPE_AVI:
  75                 return VIDEO_DIP_SELECT_AVI;
  76         case HDMI_INFOFRAME_TYPE_SPD:
  77                 return VIDEO_DIP_SELECT_SPD;
  78         case HDMI_INFOFRAME_TYPE_VENDOR:
  79                 return VIDEO_DIP_SELECT_VENDOR;
  80         default:
  81                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  82                 return 0;
  83         }
  84 }
  85
  86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87 {
  88         switch (type) {
  89         case HDMI_INFOFRAME_TYPE_AVI:
  90                 return VIDEO_DIP_ENABLE_AVI;
  91         case HDMI_INFOFRAME_TYPE_SPD:
  92                 return VIDEO_DIP_ENABLE_SPD;
  93         case HDMI_INFOFRAME_TYPE_VENDOR:
  94                 return VIDEO_DIP_ENABLE_VENDOR;
  95         default:
  96                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  97                 return 0;
  98         }
  99 }
 100
 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 102 {
 103         switch (type) {
 104         case HDMI_INFOFRAME_TYPE_AVI:
 105                 return VIDEO_DIP_ENABLE_AVI_HSW;
 106         case HDMI_INFOFRAME_TYPE_SPD:
 107                 return VIDEO_DIP_ENABLE_SPD_HSW;
 108         case HDMI_INFOFRAME_TYPE_VENDOR:
 109                 return VIDEO_DIP_ENABLE_VS_HSW;
 110         default:
 111                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 112                 return 0;
 113         }
 114 }
 115
 116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 117                                   enum transcoder cpu_transcoder,
 118                                   struct drm_i915_private *dev_priv)
 119 {
 120         switch (type) {
 121         case HDMI_INFOFRAME_TYPE_AVI:
 122                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 123         case HDMI_INFOFRAME_TYPE_SPD:
 124                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 125         case HDMI_INFOFRAME_TYPE_VENDOR:
 126                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 127         default:
 128                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 129                 return 0;
 130         }
 131 }
 132
 133 static void g4x_write_infoframe(struct drm_encoder *encoder,
 134                                 enum hdmi_infoframe_type type,
 135                                 const void *frame, ssize_t len)
 136 {
 137         const uint32_t *data = frame;
 138         struct drm_device *dev = encoder->dev;
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140         u32 val = I915_READ(VIDEO_DIP_CTL);
 141         int i;
 142
 143         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 144
 145         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 146         val |= g4x_infoframe_index(type);
 147
 148         val &= ~g4x_infoframe_enable(type);
 149
 150         I915_WRITE(VIDEO_DIP_CTL, val);
 151
 152         mmiowb();
 153         for (i = 0; i < len; i += 4) {
 154                 I915_WRITE(VIDEO_DIP_DATA, *data);
 155                 data++;
 156         }
 157         /* Write every possible data byte to force correct ECC calculation. */
 158         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 159                 I915_WRITE(VIDEO_DIP_DATA, 0);
 160         mmiowb();
 161
 162         val |= g4x_infoframe_enable(type);
 163         val &= ~VIDEO_DIP_FREQ_MASK;
 164         val |= VIDEO_DIP_FREQ_VSYNC;
 165
 166         I915_WRITE(VIDEO_DIP_CTL, val);
 167         POSTING_READ(VIDEO_DIP_CTL);
 168 }
 169
 170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
 171 {
 172         struct drm_device *dev = encoder->dev;
 173         struct drm_i915_private *dev_priv = dev->dev_private;
 174         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 175         u32 val = I915_READ(VIDEO_DIP_CTL);
 176
 177         if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
 178                 return val & VIDEO_DIP_ENABLE;
 179
 180         return false;
 181 }
 182
 183 static void ibx_write_infoframe(struct drm_encoder *encoder,
 184                                 enum hdmi_infoframe_type type,
 185                                 const void *frame, ssize_t len)
 186 {
 187         const uint32_t *data = frame;
 188         struct drm_device *dev = encoder->dev;
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 191         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 192         u32 val = I915_READ(reg);
 193
 194         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 195
 196         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 197         val |= g4x_infoframe_index(type);
 198
 199         val &= ~g4x_infoframe_enable(type);
 200
 201         I915_WRITE(reg, val);
 202
 203         mmiowb();
 204         for (i = 0; i < len; i += 4) {
 205                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 206                 data++;
 207         }
 208         /* Write every possible data byte to force correct ECC calculation. */
 209         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 210                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 211         mmiowb();
 212
 213         val |= g4x_infoframe_enable(type);
 214         val &= ~VIDEO_DIP_FREQ_MASK;
 215         val |= VIDEO_DIP_FREQ_VSYNC;
 216
 217         I915_WRITE(reg, val);
 218         POSTING_READ(reg);
 219 }
 220
 221 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 222 {
 223         struct drm_device *dev = encoder->dev;
 224         struct drm_i915_private *dev_priv = dev->dev_private;
 225         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 226         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 227         u32 val = I915_READ(reg);
 228
 229         return val & VIDEO_DIP_ENABLE;
 230 }
 231
 232 static void cpt_write_infoframe(struct drm_encoder *encoder,
 233                                 enum hdmi_infoframe_type type,
 234                                 const void *frame, ssize_t len)
 235 {
 236         const uint32_t *data = frame;
 237         struct drm_device *dev = encoder->dev;
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 240         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 241         u32 val = I915_READ(reg);
 242
 243         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 244
 245         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 246         val |= g4x_infoframe_index(type);
 247
 248         /* The DIP control register spec says that we need to update the AVI
 249          * infoframe without clearing its enable bit */
 250         if (type != HDMI_INFOFRAME_TYPE_AVI)
 251                 val &= ~g4x_infoframe_enable(type);
 252
 253         I915_WRITE(reg, val);
 254
 255         mmiowb();
 256         for (i = 0; i < len; i += 4) {
 257                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 258                 data++;
 259         }
 260         /* Write every possible data byte to force correct ECC calculation. */
 261         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 262                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 263         mmiowb();
 264
 265         val |= g4x_infoframe_enable(type);
 266         val &= ~VIDEO_DIP_FREQ_MASK;
 267         val |= VIDEO_DIP_FREQ_VSYNC;
 268
 269         I915_WRITE(reg, val);
 270         POSTING_READ(reg);
 271 }
 272
 273 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 274 {
 275         struct drm_device *dev = encoder->dev;
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 278         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 279         u32 val = I915_READ(reg);
 280
 281         return val & VIDEO_DIP_ENABLE;
 282 }
 283
 284 static void vlv_write_infoframe(struct drm_encoder *encoder,
 285                                 enum hdmi_infoframe_type type,
 286                                 const void *frame, ssize_t len)
 287 {
 288         const uint32_t *data = frame;
 289         struct drm_device *dev = encoder->dev;
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 292         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 293         u32 val = I915_READ(reg);
 294
 295         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 296
 297         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 298         val |= g4x_infoframe_index(type);
 299
 300         val &= ~g4x_infoframe_enable(type);
 301
 302         I915_WRITE(reg, val);
 303
 304         mmiowb();
 305         for (i = 0; i < len; i += 4) {
 306                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 307                 data++;
 308         }
 309         /* Write every possible data byte to force correct ECC calculation. */
 310         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 311                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 312         mmiowb();
 313
 314         val |= g4x_infoframe_enable(type);
 315         val &= ~VIDEO_DIP_FREQ_MASK;
 316         val |= VIDEO_DIP_FREQ_VSYNC;
 317
 318         I915_WRITE(reg, val);
 319         POSTING_READ(reg);
 320 }
 321
 322 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 323 {
 324         struct drm_device *dev = encoder->dev;
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 327         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 328         u32 val = I915_READ(reg);
 329
 330         return val & VIDEO_DIP_ENABLE;
 331 }
 332
 333 static void hsw_write_infoframe(struct drm_encoder *encoder,
 334                                 enum hdmi_infoframe_type type,
 335                                 const void *frame, ssize_t len)
 336 {
 337         const uint32_t *data = frame;
 338         struct drm_device *dev = encoder->dev;
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 341         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 342         u32 data_reg;
 343         int i;
 344         u32 val = I915_READ(ctl_reg);
 345
 346         data_reg = hsw_infoframe_data_reg(type,
 347                                           intel_crtc->config->cpu_transcoder,
 348                                           dev_priv);
 349         if (data_reg == 0)
 350                 return;
 351
 352         val &= ~hsw_infoframe_enable(type);
 353         I915_WRITE(ctl_reg, val);
 354
 355         mmiowb();
 356         for (i = 0; i < len; i += 4) {
 357                 I915_WRITE(data_reg + i, *data);
 358                 data++;
 359         }
 360         /* Write every possible data byte to force correct ECC calculation. */
 361         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 362                 I915_WRITE(data_reg + i, 0);
 363         mmiowb();
 364
 365         val |= hsw_infoframe_enable(type);
 366         I915_WRITE(ctl_reg, val);
 367         POSTING_READ(ctl_reg);
 368 }
 369
 370 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 371 {
 372         struct drm_device *dev = encoder->dev;
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 375         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 376         u32 val = I915_READ(ctl_reg);
 377
 378         return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
 379                       VIDEO_DIP_ENABLE_VS_HSW);
 380 }
 381
 382 /*
 383  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 384  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 385  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 386  * used for both technologies.
 387  *
 388  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 389  * DW1:       DB3       | DB2 | DB1 | DB0
 390  * DW2:       DB7       | DB6 | DB5 | DB4
 391  * DW3: ...
 392  *
 393  * (HB is Header Byte, DB is Data Byte)
 394  *
 395  * The hdmi pack() functions don't know about that hardware specific hole so we
 396  * trick them by giving an offset into the buffer and moving back the header
 397  * bytes by one.
 398  */
 399 static void intel_write_infoframe(struct drm_encoder *encoder,
 400                                   union hdmi_infoframe *frame)
 401 {
 402         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 403         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 404         ssize_t len;
 405
 406         /* see comment above for the reason for this offset */
 407         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 408         if (len < 0)
 409                 return;
 410
 411         /* Insert the 'hole' (see big comment above) at position 3 */
 412         buffer[0] = buffer[1];
 413         buffer[1] = buffer[2];
 414         buffer[2] = buffer[3];
 415         buffer[3] = 0;
 416         len++;
 417
 418         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 419 }
 420
 421 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 422                                          struct drm_display_mode *adjusted_mode)
 423 {
 424         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 425         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 426         union hdmi_infoframe frame;
 427         int ret;
 428
 429         /* Set user selected PAR to incoming mode's member */
 430         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 431
 432         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 433                                                        adjusted_mode);
 434         if (ret < 0) {
 435                 DRM_ERROR("couldn't fill AVI infoframe\n");
 436                 return;
 437         }
 438
 439         if (intel_hdmi->rgb_quant_range_selectable) {
 440                 if (intel_crtc->config->limited_color_range)
 441                         frame.avi.quantization_range =
 442                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 443                 else
 444                         frame.avi.quantization_range =
 445                                 HDMI_QUANTIZATION_RANGE_FULL;
 446         }
 447
 448         intel_write_infoframe(encoder, &frame);
 449 }
 450
 451 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 452 {
 453         union hdmi_infoframe frame;
 454         int ret;
 455
 456         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 457         if (ret < 0) {
 458                 DRM_ERROR("couldn't fill SPD infoframe\n");
 459                 return;
 460         }
 461
 462         frame.spd.sdi = HDMI_SPD_SDI_PC;
 463
 464         intel_write_infoframe(encoder, &frame);
 465 }
 466
 467 static void
 468 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 469                               struct drm_display_mode *adjusted_mode)
 470 {
 471         union hdmi_infoframe frame;
 472         int ret;
 473
 474         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 475                                                           adjusted_mode);
 476         if (ret < 0)
 477                 return;
 478
 479         intel_write_infoframe(encoder, &frame);
 480 }
 481
 482 static void g4x_set_infoframes(struct drm_encoder *encoder,
 483                                bool enable,
 484                                struct drm_display_mode *adjusted_mode)
 485 {
 486         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 487         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 488         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 489         u32 reg = VIDEO_DIP_CTL;
 490         u32 val = I915_READ(reg);
 491         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 492
 493         assert_hdmi_port_disabled(intel_hdmi);
 494
 495         /* If the registers were not initialized yet, they might be zeroes,
 496          * which means we're selecting the AVI DIP and we're setting its
 497          * frequency to once. This seems to really confuse the HW and make
 498          * things stop working (the register spec says the AVI always needs to
 499          * be sent every VSync). So here we avoid writing to the register more
 500          * than we need and also explicitly select the AVI DIP and explicitly
 501          * set its frequency to every VSync. Avoiding to write it twice seems to
 502          * be enough to solve the problem, but being defensive shouldn't hurt us
 503          * either. */
 504         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 505
 506         if (!enable) {
 507                 if (!(val & VIDEO_DIP_ENABLE))
 508                         return;
 509                 val &= ~VIDEO_DIP_ENABLE;
 510                 I915_WRITE(reg, val);
 511                 POSTING_READ(reg);
 512                 return;
 513         }
 514
 515         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 516                 if (val & VIDEO_DIP_ENABLE) {
 517                         val &= ~VIDEO_DIP_ENABLE;
 518                         I915_WRITE(reg, val);
 519                         POSTING_READ(reg);
 520                 }
 521                 val &= ~VIDEO_DIP_PORT_MASK;
 522                 val |= port;
 523         }
 524
 525         val |= VIDEO_DIP_ENABLE;
 526         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 527
 528         I915_WRITE(reg, val);
 529         POSTING_READ(reg);
 530
 531         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 532         intel_hdmi_set_spd_infoframe(encoder);
 533         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 534 }
 535
 536 static void ibx_set_infoframes(struct drm_encoder *encoder,
 537                                bool enable,
 538                                struct drm_display_mode *adjusted_mode)
 539 {
 540         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 541         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 542         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 543         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 544         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 545         u32 val = I915_READ(reg);
 546         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 547
 548         assert_hdmi_port_disabled(intel_hdmi);
 549
 550         /* See the big comment in g4x_set_infoframes() */
 551         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 552
 553         if (!enable) {
 554                 if (!(val & VIDEO_DIP_ENABLE))
 555                         return;
 556                 val &= ~VIDEO_DIP_ENABLE;
 557                 I915_WRITE(reg, val);
 558                 POSTING_READ(reg);
 559                 return;
 560         }
 561
 562         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 563                 if (val & VIDEO_DIP_ENABLE) {
 564                         val &= ~VIDEO_DIP_ENABLE;
 565                         I915_WRITE(reg, val);
 566                         POSTING_READ(reg);
 567                 }
 568                 val &= ~VIDEO_DIP_PORT_MASK;
 569                 val |= port;
 570         }
 571
 572         val |= VIDEO_DIP_ENABLE;
 573         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 574                  VIDEO_DIP_ENABLE_GCP);
 575
 576         I915_WRITE(reg, val);
 577         POSTING_READ(reg);
 578
 579         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 580         intel_hdmi_set_spd_infoframe(encoder);
 581         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 582 }
 583
 584 static void cpt_set_infoframes(struct drm_encoder *encoder,
 585                                bool enable,
 586                                struct drm_display_mode *adjusted_mode)
 587 {
 588         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 589         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 590         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 591         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 592         u32 val = I915_READ(reg);
 593
 594         assert_hdmi_port_disabled(intel_hdmi);
 595
 596         /* See the big comment in g4x_set_infoframes() */
 597         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 598
 599         if (!enable) {
 600                 if (!(val & VIDEO_DIP_ENABLE))
 601                         return;
 602                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 603                 I915_WRITE(reg, val);
 604                 POSTING_READ(reg);
 605                 return;
 606         }
 607
 608         /* Set both together, unset both together: see the spec. */
 609         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 610         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 611                  VIDEO_DIP_ENABLE_GCP);
 612
 613         I915_WRITE(reg, val);
 614         POSTING_READ(reg);
 615
 616         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 617         intel_hdmi_set_spd_infoframe(encoder);
 618         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 619 }
 620
 621 static void vlv_set_infoframes(struct drm_encoder *encoder,
 622                                bool enable,
 623                                struct drm_display_mode *adjusted_mode)
 624 {
 625         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 626         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 627         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 628         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 629         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 630         u32 val = I915_READ(reg);
 631         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 632
 633         assert_hdmi_port_disabled(intel_hdmi);
 634
 635         /* See the big comment in g4x_set_infoframes() */
 636         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 637
 638         if (!enable) {
 639                 if (!(val & VIDEO_DIP_ENABLE))
 640                         return;
 641                 val &= ~VIDEO_DIP_ENABLE;
 642                 I915_WRITE(reg, val);
 643                 POSTING_READ(reg);
 644                 return;
 645         }
 646
 647         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 648                 if (val & VIDEO_DIP_ENABLE) {
 649                         val &= ~VIDEO_DIP_ENABLE;
 650                         I915_WRITE(reg, val);
 651                         POSTING_READ(reg);
 652                 }
 653                 val &= ~VIDEO_DIP_PORT_MASK;
 654                 val |= port;
 655         }
 656
 657         val |= VIDEO_DIP_ENABLE;
 658         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 659                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 660
 661         I915_WRITE(reg, val);
 662         POSTING_READ(reg);
 663
 664         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 665         intel_hdmi_set_spd_infoframe(encoder);
 666         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 667 }
 668
 669 static void hsw_set_infoframes(struct drm_encoder *encoder,
 670                                bool enable,
 671                                struct drm_display_mode *adjusted_mode)
 672 {
 673         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 674         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 675         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 676         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 677         u32 val = I915_READ(reg);
 678
 679         assert_hdmi_port_disabled(intel_hdmi);
 680
 681         if (!enable) {
 682                 I915_WRITE(reg, 0);
 683                 POSTING_READ(reg);
 684                 return;
 685         }
 686
 687         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 688                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 689
 690         I915_WRITE(reg, val);
 691         POSTING_READ(reg);
 692
 693         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 694         intel_hdmi_set_spd_infoframe(encoder);
 695         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 696 }
 697
 698 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 699 {
 700         struct drm_device *dev = encoder->base.dev;
 701         struct drm_i915_private *dev_priv = dev->dev_private;
 702         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 703         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 704         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 705         u32 hdmi_val;
 706
 707         hdmi_val = SDVO_ENCODING_HDMI;
 708         if (!HAS_PCH_SPLIT(dev))
 709                 hdmi_val |= intel_hdmi->color_range;
 710         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 711                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 712         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 713                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 714
 715         if (crtc->config->pipe_bpp > 24)
 716                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 717         else
 718                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 719
 720         if (crtc->config->has_hdmi_sink)
 721                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 722
 723         if (HAS_PCH_CPT(dev))
 724                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 725         else if (IS_CHERRYVIEW(dev))
 726                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 727         else
 728                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 729
 730         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 731         POSTING_READ(intel_hdmi->hdmi_reg);
 732 }
 733
 734 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 735                                     enum pipe *pipe)
 736 {
 737         struct drm_device *dev = encoder->base.dev;
 738         struct drm_i915_private *dev_priv = dev->dev_private;
 739         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 740         enum intel_display_power_domain power_domain;
 741         u32 tmp;
 742
 743         power_domain = intel_display_port_power_domain(encoder);
 744         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 745                 return false;
 746
 747         tmp = I915_READ(intel_hdmi->hdmi_reg);
 748
 749         if (!(tmp & SDVO_ENABLE))
 750                 return false;
 751
 752         if (HAS_PCH_CPT(dev))
 753                 *pipe = PORT_TO_PIPE_CPT(tmp);
 754         else if (IS_CHERRYVIEW(dev))
 755                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 756         else
 757                 *pipe = PORT_TO_PIPE(tmp);
 758
 759         return true;
 760 }
 761
 762 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 763                                   struct intel_crtc_state *pipe_config)
 764 {
 765         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 766         struct drm_device *dev = encoder->base.dev;
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         u32 tmp, flags = 0;
 769         int dotclock;
 770
 771         tmp = I915_READ(intel_hdmi->hdmi_reg);
 772
 773         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 774                 flags |= DRM_MODE_FLAG_PHSYNC;
 775         else
 776                 flags |= DRM_MODE_FLAG_NHSYNC;
 777
 778         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 779                 flags |= DRM_MODE_FLAG_PVSYNC;
 780         else
 781                 flags |= DRM_MODE_FLAG_NVSYNC;
 782
 783         if (tmp & HDMI_MODE_SELECT_HDMI)
 784                 pipe_config->has_hdmi_sink = true;
 785
 786         if (intel_hdmi->infoframe_enabled(&encoder->base))
 787                 pipe_config->has_infoframe = true;
 788
 789         if (tmp & SDVO_AUDIO_ENABLE)
 790                 pipe_config->has_audio = true;
 791
 792         if (!HAS_PCH_SPLIT(dev) &&
 793             tmp & HDMI_COLOR_RANGE_16_235)
 794                 pipe_config->limited_color_range = true;
 795
 796         pipe_config->base.adjusted_mode.flags |= flags;
 797
 798         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 799                 dotclock = pipe_config->port_clock * 2 / 3;
 800         else
 801                 dotclock = pipe_config->port_clock;
 802
 803         if (HAS_PCH_SPLIT(dev_priv->dev))
 804                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 805
 806         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 807 }
 808
 809 static void intel_enable_hdmi(struct intel_encoder *encoder)
 810 {
 811         struct drm_device *dev = encoder->base.dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 814         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 815         u32 temp;
 816         u32 enable_bits = SDVO_ENABLE;
 817
 818         if (intel_crtc->config->has_audio)
 819                 enable_bits |= SDVO_AUDIO_ENABLE;
 820
 821         temp = I915_READ(intel_hdmi->hdmi_reg);
 822
 823         /* HW workaround for IBX, we need to move the port to transcoder A
 824          * before disabling it, so restore the transcoder select bit here. */
 825         if (HAS_PCH_IBX(dev))
 826                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 827
 828         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 829          * we do this anyway which shows more stable in testing.
 830          */
 831         if (HAS_PCH_SPLIT(dev)) {
 832                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 833                 POSTING_READ(intel_hdmi->hdmi_reg);
 834         }
 835
 836         temp |= enable_bits;
 837
 838         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 839         POSTING_READ(intel_hdmi->hdmi_reg);
 840
 841         /* HW workaround, need to write this twice for issue that may result
 842          * in first write getting masked.
 843          */
 844         if (HAS_PCH_SPLIT(dev)) {
 845                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 846                 POSTING_READ(intel_hdmi->hdmi_reg);
 847         }
 848
 849         if (intel_crtc->config->has_audio) {
 850                 WARN_ON(!intel_crtc->config->has_hdmi_sink);
 851                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 852                                  pipe_name(intel_crtc->pipe));
 853                 intel_audio_codec_enable(encoder);
 854         }
 855 }
 856
 857 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 858 {
 859 }
 860
 861 static void intel_disable_hdmi(struct intel_encoder *encoder)
 862 {
 863         struct drm_device *dev = encoder->base.dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 866         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 867         u32 temp;
 868         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 869
 870         if (crtc->config->has_audio)
 871                 intel_audio_codec_disable(encoder);
 872
 873         temp = I915_READ(intel_hdmi->hdmi_reg);
 874
 875         /* HW workaround for IBX, we need to move the port to transcoder A
 876          * before disabling it. */
 877         if (HAS_PCH_IBX(dev)) {
 878                 struct drm_crtc *crtc = encoder->base.crtc;
 879                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 880
 881                 if (temp & SDVO_PIPE_B_SELECT) {
 882                         temp &= ~SDVO_PIPE_B_SELECT;
 883                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 884                         POSTING_READ(intel_hdmi->hdmi_reg);
 885
 886                         /* Again we need to write this twice. */
 887                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 888                         POSTING_READ(intel_hdmi->hdmi_reg);
 889
 890                         /* Transcoder selection bits only update
 891                          * effectively on vblank. */
 892                         if (crtc)
 893                                 intel_wait_for_vblank(dev, pipe);
 894                         else
 895                                 msleep(50);
 896                 }
 897         }
 898
 899         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 900          * we do this anyway which shows more stable in testing.
 901          */
 902         if (HAS_PCH_SPLIT(dev)) {
 903                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 904                 POSTING_READ(intel_hdmi->hdmi_reg);
 905         }
 906
 907         temp &= ~enable_bits;
 908
 909         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 910         POSTING_READ(intel_hdmi->hdmi_reg);
 911
 912         /* HW workaround, need to write this twice for issue that may result
 913          * in first write getting masked.
 914          */
 915         if (HAS_PCH_SPLIT(dev)) {
 916                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 917                 POSTING_READ(intel_hdmi->hdmi_reg);
 918         }
 919 }
 920
 921 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 922 {
 923         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 924
 925         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 926                 return 165000;
 927         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 928                 return 300000;
 929         else
 930                 return 225000;
 931 }
 932
 933 static enum drm_mode_status
 934 intel_hdmi_mode_valid(struct drm_connector *connector,
 935                       struct drm_display_mode *mode)
 936 {
 937         int clock = mode->clock;
 938
 939         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 940                 clock *= 2;
 941
 942         if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 943                                          true))
 944                 return MODE_CLOCK_HIGH;
 945         if (clock < 20000)
 946                 return MODE_CLOCK_LOW;
 947
 948         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 949                 return MODE_NO_DBLESCAN;
 950
 951         return MODE_OK;
 952 }
 953
 954 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
 955 {
 956         struct drm_device *dev = crtc->base.dev;
 957         struct intel_encoder *encoder;
 958         int count = 0, count_hdmi = 0;
 959
 960         if (HAS_GMCH_DISPLAY(dev))
 961                 return false;
 962
 963         for_each_intel_encoder(dev, encoder) {
 964                 if (encoder->new_crtc != crtc)
 965                         continue;
 966
 967                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 968                 count++;
 969         }
 970
 971         /*
 972          * HDMI 12bpc affects the clocks, so it's only possible
 973          * when not cloning with other encoder types.
 974          */
 975         return count_hdmi > 0 && count_hdmi == count;
 976 }
 977
 978 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 979                                struct intel_crtc_state *pipe_config)
 980 {
 981         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 982         struct drm_device *dev = encoder->base.dev;
 983         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 984         int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
 985         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
 986         int desired_bpp;
 987
 988         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
 989
 990         if (pipe_config->has_hdmi_sink)
 991                 pipe_config->has_infoframe = true;
 992
 993         if (intel_hdmi->color_range_auto) {
 994                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 995                 if (pipe_config->has_hdmi_sink &&
 996                     drm_match_cea_mode(adjusted_mode) > 1)
 997                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 998                 else
 999                         intel_hdmi->color_range = 0;
1000         }
1001
1002         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1003                 pipe_config->pixel_multiplier = 2;
1004         }
1005
1006         if (intel_hdmi->color_range)
1007                 pipe_config->limited_color_range = true;
1008
1009         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1010                 pipe_config->has_pch_encoder = true;
1011
1012         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1013                 pipe_config->has_audio = true;
1014
1015         /*
1016          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1017          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1018          * outputs. We also need to check that the higher clock still fits
1019          * within limits.
1020          */
1021         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1022             clock_12bpc <= portclock_limit &&
1023             hdmi_12bpc_possible(encoder->new_crtc)) {
1024                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1025                 desired_bpp = 12*3;
1026
1027                 /* Need to adjust the port link by 1.5x for 12bpc. */
1028                 pipe_config->port_clock = clock_12bpc;
1029         } else {
1030                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1031                 desired_bpp = 8*3;
1032         }
1033
1034         if (!pipe_config->bw_constrained) {
1035                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1036                 pipe_config->pipe_bpp = desired_bpp;
1037         }
1038
1039         if (adjusted_mode->crtc_clock > portclock_limit) {
1040                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1041                 return false;
1042         }
1043
1044         return true;
1045 }
1046
1047 static void
1048 intel_hdmi_unset_edid(struct drm_connector *connector)
1049 {
1050         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1051
1052         intel_hdmi->has_hdmi_sink = false;
1053         intel_hdmi->has_audio = false;
1054         intel_hdmi->rgb_quant_range_selectable = false;
1055
1056         kfree(to_intel_connector(connector)->detect_edid);
1057         to_intel_connector(connector)->detect_edid = NULL;
1058 }
1059
1060 static bool
1061 intel_hdmi_set_edid(struct drm_connector *connector)
1062 {
1063         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1064         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1065         struct intel_encoder *intel_encoder =
1066                 &hdmi_to_dig_port(intel_hdmi)->base;
1067         enum intel_display_power_domain power_domain;
1068         struct edid *edid;
1069         bool connected = false;
1070
1071         power_domain = intel_display_port_power_domain(intel_encoder);
1072         intel_display_power_get(dev_priv, power_domain);
1073
1074         edid = drm_get_edid(connector,
1075                             intel_gmbus_get_adapter(dev_priv,
1076                                                     intel_hdmi->ddc_bus));
1077
1078         intel_display_power_put(dev_priv, power_domain);
1079
1080         to_intel_connector(connector)->detect_edid = edid;
1081         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1082                 intel_hdmi->rgb_quant_range_selectable =
1083                         drm_rgb_quant_range_selectable(edid);
1084
1085                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1086                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1087                         intel_hdmi->has_audio =
1088                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1089
1090                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1091                         intel_hdmi->has_hdmi_sink =
1092                                 drm_detect_hdmi_monitor(edid);
1093
1094                 connected = true;
1095         }
1096
1097         return connected;
1098 }
1099
1100 static enum drm_connector_status
1101 intel_hdmi_detect(struct drm_connector *connector, bool force)
1102 {
1103         enum drm_connector_status status;
1104
1105         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1106                       connector->base.id, connector->name);
1107
1108         intel_hdmi_unset_edid(connector);
1109
1110         if (intel_hdmi_set_edid(connector)) {
1111                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1112
1113                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1114                 status = connector_status_connected;
1115         } else
1116                 status = connector_status_disconnected;
1117
1118         return status;
1119 }
1120
1121 static void
1122 intel_hdmi_force(struct drm_connector *connector)
1123 {
1124         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1125
1126         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1127                       connector->base.id, connector->name);
1128
1129         intel_hdmi_unset_edid(connector);
1130
1131         if (connector->status != connector_status_connected)
1132                 return;
1133
1134         intel_hdmi_set_edid(connector);
1135         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1136 }
1137
1138 static int intel_hdmi_get_modes(struct drm_connector *connector)
1139 {
1140         struct edid *edid;
1141
1142         edid = to_intel_connector(connector)->detect_edid;
1143         if (edid == NULL)
1144                 return 0;
1145
1146         return intel_connector_update_modes(connector, edid);
1147 }
1148
1149 static bool
1150 intel_hdmi_detect_audio(struct drm_connector *connector)
1151 {
1152         bool has_audio = false;
1153         struct edid *edid;
1154
1155         edid = to_intel_connector(connector)->detect_edid;
1156         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1157                 has_audio = drm_detect_monitor_audio(edid);
1158
1159         return has_audio;
1160 }
1161
1162 static int
1163 intel_hdmi_set_property(struct drm_connector *connector,
1164                         struct drm_property *property,
1165                         uint64_t val)
1166 {
1167         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1168         struct intel_digital_port *intel_dig_port =
1169                 hdmi_to_dig_port(intel_hdmi);
1170         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1171         int ret;
1172
1173         ret = drm_object_property_set_value(&connector->base, property, val);
1174         if (ret)
1175                 return ret;
1176
1177         if (property == dev_priv->force_audio_property) {
1178                 enum hdmi_force_audio i = val;
1179                 bool has_audio;
1180
1181                 if (i == intel_hdmi->force_audio)
1182                         return 0;
1183
1184                 intel_hdmi->force_audio = i;
1185
1186                 if (i == HDMI_AUDIO_AUTO)
1187                         has_audio = intel_hdmi_detect_audio(connector);
1188                 else
1189                         has_audio = (i == HDMI_AUDIO_ON);
1190
1191                 if (i == HDMI_AUDIO_OFF_DVI)
1192                         intel_hdmi->has_hdmi_sink = 0;
1193
1194                 intel_hdmi->has_audio = has_audio;
1195                 goto done;
1196         }
1197
1198         if (property == dev_priv->broadcast_rgb_property) {
1199                 bool old_auto = intel_hdmi->color_range_auto;
1200                 uint32_t old_range = intel_hdmi->color_range;
1201
1202                 switch (val) {
1203                 case INTEL_BROADCAST_RGB_AUTO:
1204                         intel_hdmi->color_range_auto = true;
1205                         break;
1206                 case INTEL_BROADCAST_RGB_FULL:
1207                         intel_hdmi->color_range_auto = false;
1208                         intel_hdmi->color_range = 0;
1209                         break;
1210                 case INTEL_BROADCAST_RGB_LIMITED:
1211                         intel_hdmi->color_range_auto = false;
1212                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1213                         break;
1214                 default:
1215                         return -EINVAL;
1216                 }
1217
1218                 if (old_auto == intel_hdmi->color_range_auto &&
1219                     old_range == intel_hdmi->color_range)
1220                         return 0;
1221
1222                 goto done;
1223         }
1224
1225         if (property == connector->dev->mode_config.aspect_ratio_property) {
1226                 switch (val) {
1227                 case DRM_MODE_PICTURE_ASPECT_NONE:
1228                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1229                         break;
1230                 case DRM_MODE_PICTURE_ASPECT_4_3:
1231                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1232                         break;
1233                 case DRM_MODE_PICTURE_ASPECT_16_9:
1234                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1235                         break;
1236                 default:
1237                         return -EINVAL;
1238                 }
1239                 goto done;
1240         }
1241
1242         return -EINVAL;
1243
1244 done:
1245         if (intel_dig_port->base.base.crtc)
1246                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1247
1248         return 0;
1249 }
1250
1251 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1252 {
1253         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1254         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1255         struct drm_display_mode *adjusted_mode =
1256                 &intel_crtc->config->base.adjusted_mode;
1257
1258         intel_hdmi_prepare(encoder);
1259
1260         intel_hdmi->set_infoframes(&encoder->base,
1261                                    intel_crtc->config->has_hdmi_sink,
1262                                    adjusted_mode);
1263 }
1264
1265 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1266 {
1267         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1268         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1269         struct drm_device *dev = encoder->base.dev;
1270         struct drm_i915_private *dev_priv = dev->dev_private;
1271         struct intel_crtc *intel_crtc =
1272                 to_intel_crtc(encoder->base.crtc);
1273         struct drm_display_mode *adjusted_mode =
1274                 &intel_crtc->config->base.adjusted_mode;
1275         enum dpio_channel port = vlv_dport_to_channel(dport);
1276         int pipe = intel_crtc->pipe;
1277         u32 val;
1278
1279         /* Enable clock channels for this port */
1280         mutex_lock(&dev_priv->dpio_lock);
1281         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1282         val = 0;
1283         if (pipe)
1284                 val |= (1<<21);
1285         else
1286                 val &= ~(1<<21);
1287         val |= 0x001000c4;
1288         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1289
1290         /* HDMI 1.0V-2dB */
1291         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1292         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1293         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1294         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1295         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1296         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1297         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1298         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1299
1300         /* Program lane clock */
1301         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1302         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1303         mutex_unlock(&dev_priv->dpio_lock);
1304
1305         intel_hdmi->set_infoframes(&encoder->base,
1306                                    intel_crtc->config->has_hdmi_sink,
1307                                    adjusted_mode);
1308
1309         intel_enable_hdmi(encoder);
1310
1311         vlv_wait_port_ready(dev_priv, dport);
1312 }
1313
1314 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1315 {
1316         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1317         struct drm_device *dev = encoder->base.dev;
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319         struct intel_crtc *intel_crtc =
1320                 to_intel_crtc(encoder->base.crtc);
1321         enum dpio_channel port = vlv_dport_to_channel(dport);
1322         int pipe = intel_crtc->pipe;
1323
1324         intel_hdmi_prepare(encoder);
1325
1326         /* Program Tx lane resets to default */
1327         mutex_lock(&dev_priv->dpio_lock);
1328         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1329                          DPIO_PCS_TX_LANE2_RESET |
1330                          DPIO_PCS_TX_LANE1_RESET);
1331         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1332                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1333                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1334                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1335                          DPIO_PCS_CLK_SOFT_RESET);
1336
1337         /* Fix up inter-pair skew failure */
1338         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1339         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1340         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1341
1342         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1343         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1344         mutex_unlock(&dev_priv->dpio_lock);
1345 }
1346
1347 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1348 {
1349         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1350         struct drm_device *dev = encoder->base.dev;
1351         struct drm_i915_private *dev_priv = dev->dev_private;
1352         struct intel_crtc *intel_crtc =
1353                 to_intel_crtc(encoder->base.crtc);
1354         enum dpio_channel ch = vlv_dport_to_channel(dport);
1355         enum pipe pipe = intel_crtc->pipe;
1356         u32 val;
1357
1358         intel_hdmi_prepare(encoder);
1359
1360         mutex_lock(&dev_priv->dpio_lock);
1361
1362         /* program left/right clock distribution */
1363         if (pipe != PIPE_B) {
1364                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1365                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1366                 if (ch == DPIO_CH0)
1367                         val |= CHV_BUFLEFTENA1_FORCE;
1368                 if (ch == DPIO_CH1)
1369                         val |= CHV_BUFRIGHTENA1_FORCE;
1370                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1371         } else {
1372                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1373                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1374                 if (ch == DPIO_CH0)
1375                         val |= CHV_BUFLEFTENA2_FORCE;
1376                 if (ch == DPIO_CH1)
1377                         val |= CHV_BUFRIGHTENA2_FORCE;
1378                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1379         }
1380
1381         /* program clock channel usage */
1382         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1383         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1384         if (pipe != PIPE_B)
1385                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1386         else
1387                 val |= CHV_PCS_USEDCLKCHANNEL;
1388         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1389
1390         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1391         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1392         if (pipe != PIPE_B)
1393                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1394         else
1395                 val |= CHV_PCS_USEDCLKCHANNEL;
1396         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1397
1398         /*
1399          * This a a bit weird since generally CL
1400          * matches the pipe, but here we need to
1401          * pick the CL based on the port.
1402          */
1403         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1404         if (pipe != PIPE_B)
1405                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1406         else
1407                 val |= CHV_CMN_USEDCLKCHANNEL;
1408         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1409
1410         mutex_unlock(&dev_priv->dpio_lock);
1411 }
1412
1413 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1414 {
1415         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1416         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1417         struct intel_crtc *intel_crtc =
1418                 to_intel_crtc(encoder->base.crtc);
1419         enum dpio_channel port = vlv_dport_to_channel(dport);
1420         int pipe = intel_crtc->pipe;
1421
1422         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1423         mutex_lock(&dev_priv->dpio_lock);
1424         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1425         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1426         mutex_unlock(&dev_priv->dpio_lock);
1427 }
1428
1429 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1430 {
1431         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1432         struct drm_device *dev = encoder->base.dev;
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         struct intel_crtc *intel_crtc =
1435                 to_intel_crtc(encoder->base.crtc);
1436         enum dpio_channel ch = vlv_dport_to_channel(dport);
1437         enum pipe pipe = intel_crtc->pipe;
1438         u32 val;
1439
1440         mutex_lock(&dev_priv->dpio_lock);
1441
1442         /* Propagate soft reset to data lane reset */
1443         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1444         val |= CHV_PCS_REQ_SOFTRESET_EN;
1445         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1446
1447         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1448         val |= CHV_PCS_REQ_SOFTRESET_EN;
1449         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1450
1451         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1452         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1453         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1454
1455         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1456         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1457         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1458
1459         mutex_unlock(&dev_priv->dpio_lock);
1460 }
1461
1462 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1463 {
1464         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1465         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1466         struct drm_device *dev = encoder->base.dev;
1467         struct drm_i915_private *dev_priv = dev->dev_private;
1468         struct intel_crtc *intel_crtc =
1469                 to_intel_crtc(encoder->base.crtc);
1470         struct drm_display_mode *adjusted_mode =
1471                 &intel_crtc->config->base.adjusted_mode;
1472         enum dpio_channel ch = vlv_dport_to_channel(dport);
1473         int pipe = intel_crtc->pipe;
1474         int data, i;
1475         u32 val;
1476
1477         mutex_lock(&dev_priv->dpio_lock);
1478
1479         /* allow hardware to manage TX FIFO reset source */
1480         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1481         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1482         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1483
1484         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1485         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1486         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1487
1488         /* Deassert soft data lane reset*/
1489         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1490         val |= CHV_PCS_REQ_SOFTRESET_EN;
1491         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1492
1493         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1494         val |= CHV_PCS_REQ_SOFTRESET_EN;
1495         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1496
1497         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1498         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1499         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1500
1501         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1502         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1503         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1504
1505         /* Program Tx latency optimal setting */
1506         for (i = 0; i < 4; i++) {
1507                 /* Set the latency optimal bit */
1508                 data = (i == 1) ? 0x0 : 0x6;
1509                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1510                                 data << DPIO_FRC_LATENCY_SHFIT);
1511
1512                 /* Set the upar bit */
1513                 data = (i == 1) ? 0x0 : 0x1;
1514                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1515                                 data << DPIO_UPAR_SHIFT);
1516         }
1517
1518         /* Data lane stagger programming */
1519         /* FIXME: Fix up value only after power analysis */
1520
1521         /* Clear calc init */
1522         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1523         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1524         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1525         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1526         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1527
1528         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1529         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1530         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1531         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1532         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1533
1534         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1535         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1536         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1537         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1538
1539         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1540         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1541         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1542         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1543
1544         /* FIXME: Program the support xxx V-dB */
1545         /* Use 800mV-0dB */
1546         for (i = 0; i < 4; i++) {
1547                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1548                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1549                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1550                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1551         }
1552
1553         for (i = 0; i < 4; i++) {
1554                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1555                 val &= ~DPIO_SWING_MARGIN000_MASK;
1556                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1557                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1558         }
1559
1560         /* Disable unique transition scale */
1561         for (i = 0; i < 4; i++) {
1562                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1563                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1564                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1565         }
1566
1567         /* Additional steps for 1200mV-0dB */
1568 #if 0
1569         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1570         if (ch)
1571                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1572         else
1573                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1574         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1575
1576         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1577                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1578                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1579 #endif
1580         /* Start swing calculation */
1581         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1582         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1583         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1584
1585         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1586         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1587         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1588
1589         /* LRC Bypass */
1590         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1591         val |= DPIO_LRC_BYPASS;
1592         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1593
1594         mutex_unlock(&dev_priv->dpio_lock);
1595
1596         intel_hdmi->set_infoframes(&encoder->base,
1597                                    intel_crtc->config->has_hdmi_sink,
1598                                    adjusted_mode);
1599
1600         intel_enable_hdmi(encoder);
1601
1602         vlv_wait_port_ready(dev_priv, dport);
1603 }
1604
1605 static void intel_hdmi_destroy(struct drm_connector *connector)
1606 {
1607         kfree(to_intel_connector(connector)->detect_edid);
1608         drm_connector_cleanup(connector);
1609         kfree(connector);
1610 }
1611
1612 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1613         .dpms = intel_connector_dpms,
1614         .detect = intel_hdmi_detect,
1615         .force = intel_hdmi_force,
1616         .fill_modes = drm_helper_probe_single_connector_modes,
1617         .set_property = intel_hdmi_set_property,
1618         .atomic_get_property = intel_connector_atomic_get_property,
1619         .destroy = intel_hdmi_destroy,
1620         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1621 };
1622
1623 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1624         .get_modes = intel_hdmi_get_modes,
1625         .mode_valid = intel_hdmi_mode_valid,
1626         .best_encoder = intel_best_encoder,
1627 };
1628
1629 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1630         .destroy = intel_encoder_destroy,
1631 };
1632
1633 static void
1634 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1635 {
1636         if (!drm_mode_create_aspect_ratio_property(connector->dev))
1637                 drm_object_attach_property(&connector->base,
1638                         connector->dev->mode_config.aspect_ratio_property,
1639                         DRM_MODE_PICTURE_ASPECT_NONE);
1640 }
1641
1642 static void
1643 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1644 {
1645         intel_attach_force_audio_property(connector);
1646         intel_attach_broadcast_rgb_property(connector);
1647         intel_hdmi->color_range_auto = true;
1648         intel_attach_aspect_ratio_property(connector);
1649         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1650 }
1651
1652 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1653                                struct intel_connector *intel_connector)
1654 {
1655         struct drm_connector *connector = &intel_connector->base;
1656         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1657         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1658         struct drm_device *dev = intel_encoder->base.dev;
1659         struct drm_i915_private *dev_priv = dev->dev_private;
1660         enum port port = intel_dig_port->port;
1661
1662         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1663                            DRM_MODE_CONNECTOR_HDMIA);
1664         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1665
1666         connector->interlace_allowed = 1;
1667         connector->doublescan_allowed = 0;
1668         connector->stereo_allowed = 1;
1669
1670         switch (port) {
1671         case PORT_B:
1672                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1673                 intel_encoder->hpd_pin = HPD_PORT_B;
1674                 break;
1675         case PORT_C:
1676                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1677                 intel_encoder->hpd_pin = HPD_PORT_C;
1678                 break;
1679         case PORT_D:
1680                 if (IS_CHERRYVIEW(dev))
1681                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1682                 else
1683                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1684                 intel_encoder->hpd_pin = HPD_PORT_D;
1685                 break;
1686         case PORT_A:
1687                 intel_encoder->hpd_pin = HPD_PORT_A;
1688                 /* Internal port only for eDP. */
1689         default:
1690                 BUG();
1691         }
1692
1693         if (IS_VALLEYVIEW(dev)) {
1694                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1695                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1696                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1697         } else if (IS_G4X(dev)) {
1698                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1699                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1700                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1701         } else if (HAS_DDI(dev)) {
1702                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1703                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1704                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1705         } else if (HAS_PCH_IBX(dev)) {
1706                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1707                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1708                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1709         } else {
1710                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1711                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1712                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1713         }
1714
1715         if (HAS_DDI(dev))
1716                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1717         else
1718                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1719         intel_connector->unregister = intel_connector_unregister;
1720
1721         intel_hdmi_add_properties(intel_hdmi, connector);
1722
1723         intel_connector_attach_encoder(intel_connector, intel_encoder);
1724         drm_connector_register(connector);
1725
1726         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1727          * 0xd.  Failure to do so will result in spurious interrupts being
1728          * generated on the port when a cable is not attached.
1729          */
1730         if (IS_G4X(dev) && !IS_GM45(dev)) {
1731                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1732                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1733         }
1734 }
1735
1736 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1737 {
1738         struct intel_digital_port *intel_dig_port;
1739         struct intel_encoder *intel_encoder;
1740         struct intel_connector *intel_connector;
1741
1742         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1743         if (!intel_dig_port)
1744                 return;
1745
1746         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1747         if (!intel_connector) {
1748                 kfree(intel_dig_port);
1749                 return;
1750         }
1751
1752         intel_encoder = &intel_dig_port->base;
1753
1754         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1755                          DRM_MODE_ENCODER_TMDS);
1756
1757         intel_encoder->compute_config = intel_hdmi_compute_config;
1758         intel_encoder->disable = intel_disable_hdmi;
1759         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1760         intel_encoder->get_config = intel_hdmi_get_config;
1761         if (IS_CHERRYVIEW(dev)) {
1762                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1763                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1764                 intel_encoder->enable = vlv_enable_hdmi;
1765                 intel_encoder->post_disable = chv_hdmi_post_disable;
1766         } else if (IS_VALLEYVIEW(dev)) {
1767                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1768                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1769                 intel_encoder->enable = vlv_enable_hdmi;
1770                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1771         } else {
1772                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1773                 intel_encoder->enable = intel_enable_hdmi;
1774         }
1775
1776         intel_encoder->type = INTEL_OUTPUT_HDMI;
1777         if (IS_CHERRYVIEW(dev)) {
1778                 if (port == PORT_D)
1779                         intel_encoder->crtc_mask = 1 << 2;
1780                 else
1781                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1782         } else {
1783                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1784         }
1785         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1786         /*
1787          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1788          * to work on real hardware. And since g4x can send infoframes to
1789          * only one port anyway, nothing is lost by allowing it.
1790          */
1791         if (IS_G4X(dev))
1792                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1793
1794         intel_dig_port->port = port;
1795         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1796         intel_dig_port->dp.output_reg = 0;
1797
1798         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1799 }