drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_crtc.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  41 {
  42         return container_of(encoder, struct intel_hdmi, base.base);
  43 }
  44
  45 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  46 {
  47         return container_of(intel_attached_encoder(connector),
  48                             struct intel_hdmi, base);
  49 }
  50
  51 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  52 {
  53         uint8_t *data = (uint8_t *)frame;
  54         uint8_t sum = 0;
  55         unsigned i;
  56
  57         frame->checksum = 0;
  58         frame->ecc = 0;
  59
  60         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  61                 sum += data[i];
  62
  63         frame->checksum = 0x100 - sum;
  64 }
  65
  66 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  67 {
  68         switch (frame->type) {
  69         case DIP_TYPE_AVI:
  70                 return VIDEO_DIP_SELECT_AVI;
  71         case DIP_TYPE_SPD:
  72                 return VIDEO_DIP_SELECT_SPD;
  73         default:
  74                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  75                 return 0;
  76         }
  77 }
  78
  79 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  80 {
  81         switch (frame->type) {
  82         case DIP_TYPE_AVI:
  83                 return VIDEO_DIP_ENABLE_AVI;
  84         case DIP_TYPE_SPD:
  85                 return VIDEO_DIP_ENABLE_SPD;
  86         default:
  87                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  88                 return 0;
  89         }
  90 }
  91
  92 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
  93 {
  94         switch (frame->type) {
  95         case DIP_TYPE_AVI:
  96                 return VIDEO_DIP_ENABLE_AVI_HSW;
  97         case DIP_TYPE_SPD:
  98                 return VIDEO_DIP_ENABLE_SPD_HSW;
  99         default:
 100                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 101                 return 0;
 102         }
 103 }
 104
 105 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
 106 {
 107         switch (frame->type) {
 108         case DIP_TYPE_AVI:
 109                 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
 110         case DIP_TYPE_SPD:
 111                 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
 112         default:
 113                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 114                 return 0;
 115         }
 116 }
 117
 118 static void g4x_write_infoframe(struct drm_encoder *encoder,
 119                                 struct dip_infoframe *frame)
 120 {
 121         uint32_t *data = (uint32_t *)frame;
 122         struct drm_device *dev = encoder->dev;
 123         struct drm_i915_private *dev_priv = dev->dev_private;
 124         u32 val = I915_READ(VIDEO_DIP_CTL);
 125         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 126
 127         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 128
 129         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 130         val |= g4x_infoframe_index(frame);
 131
 132         val &= ~g4x_infoframe_enable(frame);
 133
 134         I915_WRITE(VIDEO_DIP_CTL, val);
 135
 136         for (i = 0; i < len; i += 4) {
 137                 I915_WRITE(VIDEO_DIP_DATA, *data);
 138                 data++;
 139         }
 140
 141         val |= g4x_infoframe_enable(frame);
 142         val &= ~VIDEO_DIP_FREQ_MASK;
 143         val |= VIDEO_DIP_FREQ_VSYNC;
 144
 145         I915_WRITE(VIDEO_DIP_CTL, val);
 146 }
 147
 148 static void ibx_write_infoframe(struct drm_encoder *encoder,
 149                                 struct dip_infoframe *frame)
 150 {
 151         uint32_t *data = (uint32_t *)frame;
 152         struct drm_device *dev = encoder->dev;
 153         struct drm_i915_private *dev_priv = dev->dev_private;
 154         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 155         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 156         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 157         u32 val = I915_READ(reg);
 158
 159         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 160
 161         intel_wait_for_vblank(dev, intel_crtc->pipe);
 162
 163         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 164         val |= g4x_infoframe_index(frame);
 165
 166         val &= ~g4x_infoframe_enable(frame);
 167
 168         I915_WRITE(reg, val);
 169
 170         for (i = 0; i < len; i += 4) {
 171                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 172                 data++;
 173         }
 174
 175         val |= g4x_infoframe_enable(frame);
 176         val &= ~VIDEO_DIP_FREQ_MASK;
 177         val |= VIDEO_DIP_FREQ_VSYNC;
 178
 179         I915_WRITE(reg, val);
 180 }
 181
 182 static void cpt_write_infoframe(struct drm_encoder *encoder,
 183                                 struct dip_infoframe *frame)
 184 {
 185         uint32_t *data = (uint32_t *)frame;
 186         struct drm_device *dev = encoder->dev;
 187         struct drm_i915_private *dev_priv = dev->dev_private;
 188         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 189         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 190         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 191         u32 val = I915_READ(reg);
 192
 193         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 194
 195         intel_wait_for_vblank(dev, intel_crtc->pipe);
 196
 197         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 198         val |= g4x_infoframe_index(frame);
 199
 200         /* The DIP control register spec says that we need to update the AVI
 201          * infoframe without clearing its enable bit */
 202         if (frame->type != DIP_TYPE_AVI)
 203                 val &= ~g4x_infoframe_enable(frame);
 204
 205         I915_WRITE(reg, val);
 206
 207         for (i = 0; i < len; i += 4) {
 208                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 209                 data++;
 210         }
 211
 212         val |= g4x_infoframe_enable(frame);
 213         val &= ~VIDEO_DIP_FREQ_MASK;
 214         val |= VIDEO_DIP_FREQ_VSYNC;
 215
 216         I915_WRITE(reg, val);
 217 }
 218
 219 static void vlv_write_infoframe(struct drm_encoder *encoder,
 220                                      struct dip_infoframe *frame)
 221 {
 222         uint32_t *data = (uint32_t *)frame;
 223         struct drm_device *dev = encoder->dev;
 224         struct drm_i915_private *dev_priv = dev->dev_private;
 225         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 226         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 227         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 228         u32 val = I915_READ(reg);
 229
 230         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 231
 232         intel_wait_for_vblank(dev, intel_crtc->pipe);
 233
 234         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 235         val |= g4x_infoframe_index(frame);
 236
 237         val &= ~g4x_infoframe_enable(frame);
 238
 239         I915_WRITE(reg, val);
 240
 241         for (i = 0; i < len; i += 4) {
 242                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 243                 data++;
 244         }
 245
 246         val |= g4x_infoframe_enable(frame);
 247         val &= ~VIDEO_DIP_FREQ_MASK;
 248         val |= VIDEO_DIP_FREQ_VSYNC;
 249
 250         I915_WRITE(reg, val);
 251 }
 252
 253 static void hsw_write_infoframe(struct drm_encoder *encoder,
 254                                 struct dip_infoframe *frame)
 255 {
 256         uint32_t *data = (uint32_t *)frame;
 257         struct drm_device *dev = encoder->dev;
 258         struct drm_i915_private *dev_priv = dev->dev_private;
 259         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 260         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 261         u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
 262         unsigned int i, len = DIP_HEADER_SIZE + frame->len;
 263         u32 val = I915_READ(ctl_reg);
 264
 265         if (data_reg == 0)
 266                 return;
 267
 268         intel_wait_for_vblank(dev, intel_crtc->pipe);
 269
 270         val &= ~hsw_infoframe_enable(frame);
 271         I915_WRITE(ctl_reg, val);
 272
 273         for (i = 0; i < len; i += 4) {
 274                 I915_WRITE(data_reg + i, *data);
 275                 data++;
 276         }
 277
 278         val |= hsw_infoframe_enable(frame);
 279         I915_WRITE(ctl_reg, val);
 280 }
 281
 282 static void intel_set_infoframe(struct drm_encoder *encoder,
 283                                 struct dip_infoframe *frame)
 284 {
 285         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 286
 287         intel_dip_infoframe_csum(frame);
 288         intel_hdmi->write_infoframe(encoder, frame);
 289 }
 290
 291 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 292                                          struct drm_display_mode *adjusted_mode)
 293 {
 294         struct dip_infoframe avi_if = {
 295                 .type = DIP_TYPE_AVI,
 296                 .ver = DIP_VERSION_AVI,
 297                 .len = DIP_LEN_AVI,
 298         };
 299
 300         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 301                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 302
 303         intel_set_infoframe(encoder, &avi_if);
 304 }
 305
 306 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 307 {
 308         struct dip_infoframe spd_if;
 309
 310         memset(&spd_if, 0, sizeof(spd_if));
 311         spd_if.type = DIP_TYPE_SPD;
 312         spd_if.ver = DIP_VERSION_SPD;
 313         spd_if.len = DIP_LEN_SPD;
 314         strcpy(spd_if.body.spd.vn, "Intel");
 315         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 316         spd_if.body.spd.sdi = DIP_SPD_PC;
 317
 318         intel_set_infoframe(encoder, &spd_if);
 319 }
 320
 321 static void g4x_set_infoframes(struct drm_encoder *encoder,
 322                                struct drm_display_mode *adjusted_mode)
 323 {
 324         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 325         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 326         u32 reg = VIDEO_DIP_CTL;
 327         u32 val = I915_READ(reg);
 328
 329         /* If the registers were not initialized yet, they might be zeroes,
 330          * which means we're selecting the AVI DIP and we're setting its
 331          * frequency to once. This seems to really confuse the HW and make
 332          * things stop working (the register spec says the AVI always needs to
 333          * be sent every VSync). So here we avoid writing to the register more
 334          * than we need and also explicitly select the AVI DIP and explicitly
 335          * set its frequency to every VSync. Avoiding to write it twice seems to
 336          * be enough to solve the problem, but being defensive shouldn't hurt us
 337          * either. */
 338         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 339
 340         if (!intel_hdmi->has_hdmi_sink) {
 341                 if (!(val & VIDEO_DIP_ENABLE))
 342                         return;
 343                 val &= ~VIDEO_DIP_ENABLE;
 344                 I915_WRITE(reg, val);
 345                 return;
 346         }
 347
 348         val &= ~VIDEO_DIP_PORT_MASK;
 349         switch (intel_hdmi->sdvox_reg) {
 350         case SDVOB:
 351                 val |= VIDEO_DIP_PORT_B;
 352                 break;
 353         case SDVOC:
 354                 val |= VIDEO_DIP_PORT_C;
 355                 break;
 356         default:
 357                 return;
 358         }
 359
 360         val |= VIDEO_DIP_ENABLE;
 361
 362         I915_WRITE(reg, val);
 363
 364         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 365         intel_hdmi_set_spd_infoframe(encoder);
 366 }
 367
 368 static void ibx_set_infoframes(struct drm_encoder *encoder,
 369                                struct drm_display_mode *adjusted_mode)
 370 {
 371         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 372         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 373         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 374         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 375         u32 val = I915_READ(reg);
 376
 377         /* See the big comment in g4x_set_infoframes() */
 378         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 379
 380         if (!intel_hdmi->has_hdmi_sink) {
 381                 if (!(val & VIDEO_DIP_ENABLE))
 382                         return;
 383                 val &= ~VIDEO_DIP_ENABLE;
 384                 I915_WRITE(reg, val);
 385                 return;
 386         }
 387
 388         val &= ~VIDEO_DIP_PORT_MASK;
 389         switch (intel_hdmi->sdvox_reg) {
 390         case HDMIB:
 391                 val |= VIDEO_DIP_PORT_B;
 392                 break;
 393         case HDMIC:
 394                 val |= VIDEO_DIP_PORT_C;
 395                 break;
 396         case HDMID:
 397                 val |= VIDEO_DIP_PORT_D;
 398                 break;
 399         default:
 400                 return;
 401         }
 402
 403         val |= VIDEO_DIP_ENABLE;
 404
 405         I915_WRITE(reg, val);
 406
 407         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 408         intel_hdmi_set_spd_infoframe(encoder);
 409 }
 410
 411 static void cpt_set_infoframes(struct drm_encoder *encoder,
 412                                struct drm_display_mode *adjusted_mode)
 413 {
 414         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 415         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 416         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 417         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 418         u32 val = I915_READ(reg);
 419
 420         /* See the big comment in g4x_set_infoframes() */
 421         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 422
 423         if (!intel_hdmi->has_hdmi_sink) {
 424                 if (!(val & VIDEO_DIP_ENABLE))
 425                         return;
 426                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 427                 I915_WRITE(reg, val);
 428                 return;
 429         }
 430
 431         /* Set both together, unset both together: see the spec. */
 432         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 433
 434         I915_WRITE(reg, val);
 435
 436         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 437         intel_hdmi_set_spd_infoframe(encoder);
 438 }
 439
 440 static void vlv_set_infoframes(struct drm_encoder *encoder,
 441                                struct drm_display_mode *adjusted_mode)
 442 {
 443         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 444         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 445         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 446         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 447         u32 val = I915_READ(reg);
 448
 449         /* See the big comment in g4x_set_infoframes() */
 450         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 451
 452         if (!intel_hdmi->has_hdmi_sink) {
 453                 if (!(val & VIDEO_DIP_ENABLE))
 454                         return;
 455                 val &= ~VIDEO_DIP_ENABLE;
 456                 I915_WRITE(reg, val);
 457                 return;
 458         }
 459
 460         val |= VIDEO_DIP_ENABLE;
 461
 462         I915_WRITE(reg, val);
 463
 464         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 465         intel_hdmi_set_spd_infoframe(encoder);
 466 }
 467
 468 static void hsw_set_infoframes(struct drm_encoder *encoder,
 469                                struct drm_display_mode *adjusted_mode)
 470 {
 471         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 472         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 473         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 474         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 475
 476         if (!intel_hdmi->has_hdmi_sink) {
 477                 I915_WRITE(reg, 0);
 478                 return;
 479         }
 480
 481         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 482         intel_hdmi_set_spd_infoframe(encoder);
 483 }
 484
 485 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 486                                 struct drm_display_mode *mode,
 487                                 struct drm_display_mode *adjusted_mode)
 488 {
 489         struct drm_device *dev = encoder->dev;
 490         struct drm_i915_private *dev_priv = dev->dev_private;
 491         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 492         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 493         u32 sdvox;
 494
 495         sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
 496         if (!HAS_PCH_SPLIT(dev))
 497                 sdvox |= intel_hdmi->color_range;
 498         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 499                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 500         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 501                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 502
 503         if (intel_crtc->bpp > 24)
 504                 sdvox |= COLOR_FORMAT_12bpc;
 505         else
 506                 sdvox |= COLOR_FORMAT_8bpc;
 507
 508         /* Required on CPT */
 509         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 510                 sdvox |= HDMI_MODE_SELECT;
 511
 512         if (intel_hdmi->has_audio) {
 513                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 514                                  pipe_name(intel_crtc->pipe));
 515                 sdvox |= SDVO_AUDIO_ENABLE;
 516                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 517                 intel_write_eld(encoder, adjusted_mode);
 518         }
 519
 520         if (HAS_PCH_CPT(dev))
 521                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 522         else if (intel_crtc->pipe == 1)
 523                 sdvox |= SDVO_PIPE_B_SELECT;
 524
 525         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 526         POSTING_READ(intel_hdmi->sdvox_reg);
 527
 528         intel_hdmi->set_infoframes(encoder, adjusted_mode);
 529 }
 530
 531 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
 532 {
 533         struct drm_device *dev = encoder->dev;
 534         struct drm_i915_private *dev_priv = dev->dev_private;
 535         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 536         u32 temp;
 537         u32 enable_bits = SDVO_ENABLE;
 538
 539         if (intel_hdmi->has_audio)
 540                 enable_bits |= SDVO_AUDIO_ENABLE;
 541
 542         temp = I915_READ(intel_hdmi->sdvox_reg);
 543
 544         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 545          * we do this anyway which shows more stable in testing.
 546          */
 547         if (HAS_PCH_SPLIT(dev)) {
 548                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 549                 POSTING_READ(intel_hdmi->sdvox_reg);
 550         }
 551
 552         if (mode != DRM_MODE_DPMS_ON) {
 553                 temp &= ~enable_bits;
 554         } else {
 555                 temp |= enable_bits;
 556         }
 557
 558         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 559         POSTING_READ(intel_hdmi->sdvox_reg);
 560
 561         /* HW workaround, need to write this twice for issue that may result
 562          * in first write getting masked.
 563          */
 564         if (HAS_PCH_SPLIT(dev)) {
 565                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 566                 POSTING_READ(intel_hdmi->sdvox_reg);
 567         }
 568 }
 569
 570 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 571                                  struct drm_display_mode *mode)
 572 {
 573         if (mode->clock > 165000)
 574                 return MODE_CLOCK_HIGH;
 575         if (mode->clock < 20000)
 576                 return MODE_CLOCK_LOW;
 577
 578         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 579                 return MODE_NO_DBLESCAN;
 580
 581         return MODE_OK;
 582 }
 583
 584 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 585                                   struct drm_display_mode *mode,
 586                                   struct drm_display_mode *adjusted_mode)
 587 {
 588         return true;
 589 }
 590
 591 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
 592 {
 593         struct drm_device *dev = intel_hdmi->base.base.dev;
 594         struct drm_i915_private *dev_priv = dev->dev_private;
 595         uint32_t bit;
 596
 597         switch (intel_hdmi->sdvox_reg) {
 598         case SDVOB:
 599                 bit = HDMIB_HOTPLUG_LIVE_STATUS;
 600                 break;
 601         case SDVOC:
 602                 bit = HDMIC_HOTPLUG_LIVE_STATUS;
 603                 break;
 604         default:
 605                 bit = 0;
 606                 break;
 607         }
 608
 609         return I915_READ(PORT_HOTPLUG_STAT) & bit;
 610 }
 611
 612 static enum drm_connector_status
 613 intel_hdmi_detect(struct drm_connector *connector, bool force)
 614 {
 615         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 616         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 617         struct edid *edid;
 618         enum drm_connector_status status = connector_status_disconnected;
 619
 620         if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
 621                 return status;
 622
 623         intel_hdmi->has_hdmi_sink = false;
 624         intel_hdmi->has_audio = false;
 625         edid = drm_get_edid(connector,
 626                             intel_gmbus_get_adapter(dev_priv,
 627                                                     intel_hdmi->ddc_bus));
 628
 629         if (edid) {
 630                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 631                         status = connector_status_connected;
 632                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 633                                 intel_hdmi->has_hdmi_sink =
 634                                                 drm_detect_hdmi_monitor(edid);
 635                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 636                 }
 637                 connector->display_info.raw_edid = NULL;
 638                 kfree(edid);
 639         }
 640
 641         if (status == connector_status_connected) {
 642                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 643                         intel_hdmi->has_audio =
 644                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 645         }
 646
 647         return status;
 648 }
 649
 650 static int intel_hdmi_get_modes(struct drm_connector *connector)
 651 {
 652         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 653         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 654
 655         /* We should parse the EDID data and find out if it's an HDMI sink so
 656          * we can send audio to it.
 657          */
 658
 659         return intel_ddc_get_modes(connector,
 660                                    intel_gmbus_get_adapter(dev_priv,
 661                                                            intel_hdmi->ddc_bus));
 662 }
 663
 664 static bool
 665 intel_hdmi_detect_audio(struct drm_connector *connector)
 666 {
 667         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 668         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 669         struct edid *edid;
 670         bool has_audio = false;
 671
 672         edid = drm_get_edid(connector,
 673                             intel_gmbus_get_adapter(dev_priv,
 674                                                     intel_hdmi->ddc_bus));
 675         if (edid) {
 676                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 677                         has_audio = drm_detect_monitor_audio(edid);
 678
 679                 connector->display_info.raw_edid = NULL;
 680                 kfree(edid);
 681         }
 682
 683         return has_audio;
 684 }
 685
 686 static int
 687 intel_hdmi_set_property(struct drm_connector *connector,
 688                         struct drm_property *property,
 689                         uint64_t val)
 690 {
 691         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 692         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 693         int ret;
 694
 695         ret = drm_connector_property_set_value(connector, property, val);
 696         if (ret)
 697                 return ret;
 698
 699         if (property == dev_priv->force_audio_property) {
 700                 enum hdmi_force_audio i = val;
 701                 bool has_audio;
 702
 703                 if (i == intel_hdmi->force_audio)
 704                         return 0;
 705
 706                 intel_hdmi->force_audio = i;
 707
 708                 if (i == HDMI_AUDIO_AUTO)
 709                         has_audio = intel_hdmi_detect_audio(connector);
 710                 else
 711                         has_audio = (i == HDMI_AUDIO_ON);
 712
 713                 if (i == HDMI_AUDIO_OFF_DVI)
 714                         intel_hdmi->has_hdmi_sink = 0;
 715
 716                 intel_hdmi->has_audio = has_audio;
 717                 goto done;
 718         }
 719
 720         if (property == dev_priv->broadcast_rgb_property) {
 721                 if (val == !!intel_hdmi->color_range)
 722                         return 0;
 723
 724                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 725                 goto done;
 726         }
 727
 728         return -EINVAL;
 729
 730 done:
 731         if (intel_hdmi->base.base.crtc) {
 732                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
 733                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
 734                                          crtc->x, crtc->y,
 735                                          crtc->fb);
 736         }
 737
 738         return 0;
 739 }
 740
 741 static void intel_hdmi_destroy(struct drm_connector *connector)
 742 {
 743         drm_sysfs_connector_remove(connector);
 744         drm_connector_cleanup(connector);
 745         kfree(connector);
 746 }
 747
 748 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
 749         .dpms = intel_ddi_dpms,
 750         .mode_fixup = intel_hdmi_mode_fixup,
 751         .prepare = intel_encoder_prepare,
 752         .mode_set = intel_ddi_mode_set,
 753         .commit = intel_encoder_commit,
 754 };
 755
 756 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 757         .dpms = intel_hdmi_dpms,
 758         .mode_fixup = intel_hdmi_mode_fixup,
 759         .prepare = intel_encoder_prepare,
 760         .mode_set = intel_hdmi_mode_set,
 761         .commit = intel_encoder_commit,
 762 };
 763
 764 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 765         .dpms = drm_helper_connector_dpms,
 766         .detect = intel_hdmi_detect,
 767         .fill_modes = drm_helper_probe_single_connector_modes,
 768         .set_property = intel_hdmi_set_property,
 769         .destroy = intel_hdmi_destroy,
 770 };
 771
 772 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 773         .get_modes = intel_hdmi_get_modes,
 774         .mode_valid = intel_hdmi_mode_valid,
 775         .best_encoder = intel_best_encoder,
 776 };
 777
 778 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 779         .destroy = intel_encoder_destroy,
 780 };
 781
 782 static void
 783 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 784 {
 785         intel_attach_force_audio_property(connector);
 786         intel_attach_broadcast_rgb_property(connector);
 787 }
 788
 789 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 790 {
 791         struct drm_i915_private *dev_priv = dev->dev_private;
 792         struct drm_connector *connector;
 793         struct intel_encoder *intel_encoder;
 794         struct intel_connector *intel_connector;
 795         struct intel_hdmi *intel_hdmi;
 796         int i;
 797
 798         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 799         if (!intel_hdmi)
 800                 return;
 801
 802         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 803         if (!intel_connector) {
 804                 kfree(intel_hdmi);
 805                 return;
 806         }
 807
 808         intel_encoder = &intel_hdmi->base;
 809         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
 810                          DRM_MODE_ENCODER_TMDS);
 811
 812         connector = &intel_connector->base;
 813         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 814                            DRM_MODE_CONNECTOR_HDMIA);
 815         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 816
 817         intel_encoder->type = INTEL_OUTPUT_HDMI;
 818
 819         connector->polled = DRM_CONNECTOR_POLL_HPD;
 820         connector->interlace_allowed = 1;
 821         connector->doublescan_allowed = 0;
 822         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 823
 824         /* Set up the DDC bus. */
 825         if (sdvox_reg == SDVOB) {
 826                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 827                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 828                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 829         } else if (sdvox_reg == SDVOC) {
 830                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 831                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 832                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 833         } else if (sdvox_reg == HDMIB) {
 834                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 835                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 836                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 837         } else if (sdvox_reg == HDMIC) {
 838                 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
 839                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 840                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 841         } else if (sdvox_reg == HDMID) {
 842                 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
 843                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 844                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 845         } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
 846                 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
 847                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 848                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 849                 intel_hdmi->ddi_port = PORT_B;
 850                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 851         } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
 852                 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
 853                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 854                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 855                 intel_hdmi->ddi_port = PORT_C;
 856                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 857         } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
 858                 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
 859                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 860                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 861                 intel_hdmi->ddi_port = PORT_D;
 862                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 863         } else {
 864                 /* If we got an unknown sdvox_reg, things are pretty much broken
 865                  * in a way that we should let the kernel know about it */
 866                 BUG();
 867         }
 868
 869         intel_hdmi->sdvox_reg = sdvox_reg;
 870
 871         if (!HAS_PCH_SPLIT(dev)) {
 872                 intel_hdmi->write_infoframe = g4x_write_infoframe;
 873                 intel_hdmi->set_infoframes = g4x_set_infoframes;
 874                 I915_WRITE(VIDEO_DIP_CTL, 0);
 875         } else if (IS_VALLEYVIEW(dev)) {
 876                 intel_hdmi->write_infoframe = vlv_write_infoframe;
 877                 intel_hdmi->set_infoframes = vlv_set_infoframes;
 878                 for_each_pipe(i)
 879                         I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
 880         } else if (IS_HASWELL(dev)) {
 881                 /* FIXME: Haswell has a new set of DIP frame registers, but we are
 882                  * just doing the minimal required for HDMI to work at this stage.
 883                  */
 884                 intel_hdmi->write_infoframe = hsw_write_infoframe;
 885                 intel_hdmi->set_infoframes = hsw_set_infoframes;
 886                 for_each_pipe(i)
 887                         I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
 888         } else if (HAS_PCH_IBX(dev)) {
 889                 intel_hdmi->write_infoframe = ibx_write_infoframe;
 890                 intel_hdmi->set_infoframes = ibx_set_infoframes;
 891                 for_each_pipe(i)
 892                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 893         } else {
 894                 intel_hdmi->write_infoframe = cpt_write_infoframe;
 895                 intel_hdmi->set_infoframes = cpt_set_infoframes;
 896                 for_each_pipe(i)
 897                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 898         }
 899
 900         if (IS_HASWELL(dev))
 901                 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
 902         else
 903                 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
 904
 905         intel_hdmi_add_properties(intel_hdmi, connector);
 906
 907         intel_connector_attach_encoder(intel_connector, intel_encoder);
 908         drm_sysfs_connector_add(connector);
 909
 910         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
 911          * 0xd.  Failure to do so will result in spurious interrupts being
 912          * generated on the port when a cable is not attached.
 913          */
 914         if (IS_G4X(dev) && !IS_GM45(dev)) {
 915                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
 916                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
 917         }
 918 }