2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
42 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
46 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
48 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
49 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
50 uint32_t enabled_bits
;
52 enabled_bits
= HAS_DDI(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
54 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
55 "HDMI port enabled, expecting disabled\n");
58 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
60 struct intel_digital_port
*intel_dig_port
=
61 container_of(encoder
, struct intel_digital_port
, base
.base
);
62 return &intel_dig_port
->hdmi
;
65 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
67 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
70 static u32
g4x_infoframe_index(enum hdmi_infoframe_type type
)
73 case HDMI_INFOFRAME_TYPE_AVI
:
74 return VIDEO_DIP_SELECT_AVI
;
75 case HDMI_INFOFRAME_TYPE_SPD
:
76 return VIDEO_DIP_SELECT_SPD
;
77 case HDMI_INFOFRAME_TYPE_VENDOR
:
78 return VIDEO_DIP_SELECT_VENDOR
;
80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
85 static u32
g4x_infoframe_enable(enum hdmi_infoframe_type type
)
88 case HDMI_INFOFRAME_TYPE_AVI
:
89 return VIDEO_DIP_ENABLE_AVI
;
90 case HDMI_INFOFRAME_TYPE_SPD
:
91 return VIDEO_DIP_ENABLE_SPD
;
92 case HDMI_INFOFRAME_TYPE_VENDOR
:
93 return VIDEO_DIP_ENABLE_VENDOR
;
95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
100 static u32
hsw_infoframe_enable(enum hdmi_infoframe_type type
)
103 case HDMI_INFOFRAME_TYPE_AVI
:
104 return VIDEO_DIP_ENABLE_AVI_HSW
;
105 case HDMI_INFOFRAME_TYPE_SPD
:
106 return VIDEO_DIP_ENABLE_SPD_HSW
;
107 case HDMI_INFOFRAME_TYPE_VENDOR
:
108 return VIDEO_DIP_ENABLE_VS_HSW
;
110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
115 static u32
hsw_infoframe_data_reg(enum hdmi_infoframe_type type
,
116 enum transcoder cpu_transcoder
,
117 struct drm_i915_private
*dev_priv
)
120 case HDMI_INFOFRAME_TYPE_AVI
:
121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
);
122 case HDMI_INFOFRAME_TYPE_SPD
:
123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
);
124 case HDMI_INFOFRAME_TYPE_VENDOR
:
125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
);
127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
132 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
133 enum hdmi_infoframe_type type
,
134 const void *frame
, ssize_t len
)
136 const uint32_t *data
= frame
;
137 struct drm_device
*dev
= encoder
->dev
;
138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
139 u32 val
= I915_READ(VIDEO_DIP_CTL
);
142 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
144 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
145 val
|= g4x_infoframe_index(type
);
147 val
&= ~g4x_infoframe_enable(type
);
149 I915_WRITE(VIDEO_DIP_CTL
, val
);
152 for (i
= 0; i
< len
; i
+= 4) {
153 I915_WRITE(VIDEO_DIP_DATA
, *data
);
156 /* Write every possible data byte to force correct ECC calculation. */
157 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
158 I915_WRITE(VIDEO_DIP_DATA
, 0);
161 val
|= g4x_infoframe_enable(type
);
162 val
&= ~VIDEO_DIP_FREQ_MASK
;
163 val
|= VIDEO_DIP_FREQ_VSYNC
;
165 I915_WRITE(VIDEO_DIP_CTL
, val
);
166 POSTING_READ(VIDEO_DIP_CTL
);
169 static bool g4x_infoframe_enabled(struct drm_encoder
*encoder
)
171 struct drm_device
*dev
= encoder
->dev
;
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
174 u32 val
= I915_READ(VIDEO_DIP_CTL
);
176 if (VIDEO_DIP_PORT(intel_dig_port
->port
) == (val
& VIDEO_DIP_PORT_MASK
))
177 return val
& VIDEO_DIP_ENABLE
;
182 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
183 enum hdmi_infoframe_type type
,
184 const void *frame
, ssize_t len
)
186 const uint32_t *data
= frame
;
187 struct drm_device
*dev
= encoder
->dev
;
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
189 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
190 int i
, reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
191 u32 val
= I915_READ(reg
);
193 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
195 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
196 val
|= g4x_infoframe_index(type
);
198 val
&= ~g4x_infoframe_enable(type
);
200 I915_WRITE(reg
, val
);
203 for (i
= 0; i
< len
; i
+= 4) {
204 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
207 /* Write every possible data byte to force correct ECC calculation. */
208 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
209 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
212 val
|= g4x_infoframe_enable(type
);
213 val
&= ~VIDEO_DIP_FREQ_MASK
;
214 val
|= VIDEO_DIP_FREQ_VSYNC
;
216 I915_WRITE(reg
, val
);
220 static bool ibx_infoframe_enabled(struct drm_encoder
*encoder
)
222 struct drm_device
*dev
= encoder
->dev
;
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
224 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
225 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
226 u32 val
= I915_READ(reg
);
228 return val
& VIDEO_DIP_ENABLE
;
231 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
232 enum hdmi_infoframe_type type
,
233 const void *frame
, ssize_t len
)
235 const uint32_t *data
= frame
;
236 struct drm_device
*dev
= encoder
->dev
;
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
239 int i
, reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
240 u32 val
= I915_READ(reg
);
242 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
244 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
245 val
|= g4x_infoframe_index(type
);
247 /* The DIP control register spec says that we need to update the AVI
248 * infoframe without clearing its enable bit */
249 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
250 val
&= ~g4x_infoframe_enable(type
);
252 I915_WRITE(reg
, val
);
255 for (i
= 0; i
< len
; i
+= 4) {
256 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
259 /* Write every possible data byte to force correct ECC calculation. */
260 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
261 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
264 val
|= g4x_infoframe_enable(type
);
265 val
&= ~VIDEO_DIP_FREQ_MASK
;
266 val
|= VIDEO_DIP_FREQ_VSYNC
;
268 I915_WRITE(reg
, val
);
272 static bool cpt_infoframe_enabled(struct drm_encoder
*encoder
)
274 struct drm_device
*dev
= encoder
->dev
;
275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
276 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
277 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
278 u32 val
= I915_READ(reg
);
280 return val
& VIDEO_DIP_ENABLE
;
283 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
284 enum hdmi_infoframe_type type
,
285 const void *frame
, ssize_t len
)
287 const uint32_t *data
= frame
;
288 struct drm_device
*dev
= encoder
->dev
;
289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
290 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
291 int i
, reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
292 u32 val
= I915_READ(reg
);
294 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
296 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
297 val
|= g4x_infoframe_index(type
);
299 val
&= ~g4x_infoframe_enable(type
);
301 I915_WRITE(reg
, val
);
304 for (i
= 0; i
< len
; i
+= 4) {
305 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
308 /* Write every possible data byte to force correct ECC calculation. */
309 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
310 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
313 val
|= g4x_infoframe_enable(type
);
314 val
&= ~VIDEO_DIP_FREQ_MASK
;
315 val
|= VIDEO_DIP_FREQ_VSYNC
;
317 I915_WRITE(reg
, val
);
321 static bool vlv_infoframe_enabled(struct drm_encoder
*encoder
)
323 struct drm_device
*dev
= encoder
->dev
;
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
325 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
326 int reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
327 u32 val
= I915_READ(reg
);
329 return val
& VIDEO_DIP_ENABLE
;
332 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
333 enum hdmi_infoframe_type type
,
334 const void *frame
, ssize_t len
)
336 const uint32_t *data
= frame
;
337 struct drm_device
*dev
= encoder
->dev
;
338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
339 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
340 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
343 u32 val
= I915_READ(ctl_reg
);
345 data_reg
= hsw_infoframe_data_reg(type
,
346 intel_crtc
->config
.cpu_transcoder
,
351 val
&= ~hsw_infoframe_enable(type
);
352 I915_WRITE(ctl_reg
, val
);
355 for (i
= 0; i
< len
; i
+= 4) {
356 I915_WRITE(data_reg
+ i
, *data
);
359 /* Write every possible data byte to force correct ECC calculation. */
360 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
361 I915_WRITE(data_reg
+ i
, 0);
364 val
|= hsw_infoframe_enable(type
);
365 I915_WRITE(ctl_reg
, val
);
366 POSTING_READ(ctl_reg
);
369 static bool hsw_infoframe_enabled(struct drm_encoder
*encoder
)
371 struct drm_device
*dev
= encoder
->dev
;
372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
373 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
374 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
375 u32 val
= I915_READ(ctl_reg
);
377 return val
& (VIDEO_DIP_ENABLE_AVI_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
|
378 VIDEO_DIP_ENABLE_VS_HSW
);
382 * The data we write to the DIP data buffer registers is 1 byte bigger than the
383 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
384 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
385 * used for both technologies.
387 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
388 * DW1: DB3 | DB2 | DB1 | DB0
389 * DW2: DB7 | DB6 | DB5 | DB4
392 * (HB is Header Byte, DB is Data Byte)
394 * The hdmi pack() functions don't know about that hardware specific hole so we
395 * trick them by giving an offset into the buffer and moving back the header
398 static void intel_write_infoframe(struct drm_encoder
*encoder
,
399 union hdmi_infoframe
*frame
)
401 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
402 uint8_t buffer
[VIDEO_DIP_DATA_SIZE
];
405 /* see comment above for the reason for this offset */
406 len
= hdmi_infoframe_pack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
410 /* Insert the 'hole' (see big comment above) at position 3 */
411 buffer
[0] = buffer
[1];
412 buffer
[1] = buffer
[2];
413 buffer
[2] = buffer
[3];
417 intel_hdmi
->write_infoframe(encoder
, frame
->any
.type
, buffer
, len
);
420 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
421 struct drm_display_mode
*adjusted_mode
)
423 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
424 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
425 union hdmi_infoframe frame
;
428 /* Set user selected PAR to incoming mode's member */
429 adjusted_mode
->picture_aspect_ratio
= intel_hdmi
->aspect_ratio
;
431 ret
= drm_hdmi_avi_infoframe_from_display_mode(&frame
.avi
,
434 DRM_ERROR("couldn't fill AVI infoframe\n");
438 if (intel_hdmi
->rgb_quant_range_selectable
) {
439 if (intel_crtc
->config
.limited_color_range
)
440 frame
.avi
.quantization_range
=
441 HDMI_QUANTIZATION_RANGE_LIMITED
;
443 frame
.avi
.quantization_range
=
444 HDMI_QUANTIZATION_RANGE_FULL
;
447 intel_write_infoframe(encoder
, &frame
);
450 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
452 union hdmi_infoframe frame
;
455 ret
= hdmi_spd_infoframe_init(&frame
.spd
, "Intel", "Integrated gfx");
457 DRM_ERROR("couldn't fill SPD infoframe\n");
461 frame
.spd
.sdi
= HDMI_SPD_SDI_PC
;
463 intel_write_infoframe(encoder
, &frame
);
467 intel_hdmi_set_hdmi_infoframe(struct drm_encoder
*encoder
,
468 struct drm_display_mode
*adjusted_mode
)
470 union hdmi_infoframe frame
;
473 ret
= drm_hdmi_vendor_infoframe_from_display_mode(&frame
.vendor
.hdmi
,
478 intel_write_infoframe(encoder
, &frame
);
481 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
483 struct drm_display_mode
*adjusted_mode
)
485 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
486 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
487 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
488 u32 reg
= VIDEO_DIP_CTL
;
489 u32 val
= I915_READ(reg
);
490 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
492 assert_hdmi_port_disabled(intel_hdmi
);
494 /* If the registers were not initialized yet, they might be zeroes,
495 * which means we're selecting the AVI DIP and we're setting its
496 * frequency to once. This seems to really confuse the HW and make
497 * things stop working (the register spec says the AVI always needs to
498 * be sent every VSync). So here we avoid writing to the register more
499 * than we need and also explicitly select the AVI DIP and explicitly
500 * set its frequency to every VSync. Avoiding to write it twice seems to
501 * be enough to solve the problem, but being defensive shouldn't hurt us
503 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
506 if (!(val
& VIDEO_DIP_ENABLE
))
508 val
&= ~VIDEO_DIP_ENABLE
;
509 I915_WRITE(reg
, val
);
514 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
515 if (val
& VIDEO_DIP_ENABLE
) {
516 val
&= ~VIDEO_DIP_ENABLE
;
517 I915_WRITE(reg
, val
);
520 val
&= ~VIDEO_DIP_PORT_MASK
;
524 val
|= VIDEO_DIP_ENABLE
;
525 val
&= ~VIDEO_DIP_ENABLE_VENDOR
;
527 I915_WRITE(reg
, val
);
530 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
531 intel_hdmi_set_spd_infoframe(encoder
);
532 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
535 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
537 struct drm_display_mode
*adjusted_mode
)
539 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
540 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
541 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
542 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
543 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
544 u32 val
= I915_READ(reg
);
545 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
547 assert_hdmi_port_disabled(intel_hdmi
);
549 /* See the big comment in g4x_set_infoframes() */
550 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
553 if (!(val
& VIDEO_DIP_ENABLE
))
555 val
&= ~VIDEO_DIP_ENABLE
;
556 I915_WRITE(reg
, val
);
561 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
562 if (val
& VIDEO_DIP_ENABLE
) {
563 val
&= ~VIDEO_DIP_ENABLE
;
564 I915_WRITE(reg
, val
);
567 val
&= ~VIDEO_DIP_PORT_MASK
;
571 val
|= VIDEO_DIP_ENABLE
;
572 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
573 VIDEO_DIP_ENABLE_GCP
);
575 I915_WRITE(reg
, val
);
578 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
579 intel_hdmi_set_spd_infoframe(encoder
);
580 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
583 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
585 struct drm_display_mode
*adjusted_mode
)
587 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
588 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
589 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
590 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
591 u32 val
= I915_READ(reg
);
593 assert_hdmi_port_disabled(intel_hdmi
);
595 /* See the big comment in g4x_set_infoframes() */
596 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
599 if (!(val
& VIDEO_DIP_ENABLE
))
601 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
);
602 I915_WRITE(reg
, val
);
607 /* Set both together, unset both together: see the spec. */
608 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
609 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
610 VIDEO_DIP_ENABLE_GCP
);
612 I915_WRITE(reg
, val
);
615 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
616 intel_hdmi_set_spd_infoframe(encoder
);
617 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
620 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
622 struct drm_display_mode
*adjusted_mode
)
624 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
625 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
626 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
627 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
628 u32 reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
629 u32 val
= I915_READ(reg
);
630 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
632 assert_hdmi_port_disabled(intel_hdmi
);
634 /* See the big comment in g4x_set_infoframes() */
635 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
638 if (!(val
& VIDEO_DIP_ENABLE
))
640 val
&= ~VIDEO_DIP_ENABLE
;
641 I915_WRITE(reg
, val
);
646 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
647 if (val
& VIDEO_DIP_ENABLE
) {
648 val
&= ~VIDEO_DIP_ENABLE
;
649 I915_WRITE(reg
, val
);
652 val
&= ~VIDEO_DIP_PORT_MASK
;
656 val
|= VIDEO_DIP_ENABLE
;
657 val
&= ~(VIDEO_DIP_ENABLE_AVI
| VIDEO_DIP_ENABLE_VENDOR
|
658 VIDEO_DIP_ENABLE_GAMUT
| VIDEO_DIP_ENABLE_GCP
);
660 I915_WRITE(reg
, val
);
663 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
664 intel_hdmi_set_spd_infoframe(encoder
);
665 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
668 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
670 struct drm_display_mode
*adjusted_mode
)
672 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
673 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
674 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
675 u32 reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
676 u32 val
= I915_READ(reg
);
678 assert_hdmi_port_disabled(intel_hdmi
);
686 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_GCP_HSW
|
687 VIDEO_DIP_ENABLE_VS_HSW
| VIDEO_DIP_ENABLE_GMP_HSW
);
689 I915_WRITE(reg
, val
);
692 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
693 intel_hdmi_set_spd_infoframe(encoder
);
694 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
697 static void intel_hdmi_prepare(struct intel_encoder
*encoder
)
699 struct drm_device
*dev
= encoder
->base
.dev
;
700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
701 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
702 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
703 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
706 hdmi_val
= SDVO_ENCODING_HDMI
;
707 if (!HAS_PCH_SPLIT(dev
))
708 hdmi_val
|= intel_hdmi
->color_range
;
709 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
710 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
711 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
712 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
714 if (crtc
->config
.pipe_bpp
> 24)
715 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
717 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
719 if (crtc
->config
.has_hdmi_sink
)
720 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
722 if (HAS_PCH_CPT(dev
))
723 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
724 else if (IS_CHERRYVIEW(dev
))
725 hdmi_val
|= SDVO_PIPE_SEL_CHV(crtc
->pipe
);
727 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
729 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
730 POSTING_READ(intel_hdmi
->hdmi_reg
);
733 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
736 struct drm_device
*dev
= encoder
->base
.dev
;
737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
738 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
739 enum intel_display_power_domain power_domain
;
742 power_domain
= intel_display_port_power_domain(encoder
);
743 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
746 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
748 if (!(tmp
& SDVO_ENABLE
))
751 if (HAS_PCH_CPT(dev
))
752 *pipe
= PORT_TO_PIPE_CPT(tmp
);
753 else if (IS_CHERRYVIEW(dev
))
754 *pipe
= SDVO_PORT_TO_PIPE_CHV(tmp
);
756 *pipe
= PORT_TO_PIPE(tmp
);
761 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
762 struct intel_crtc_config
*pipe_config
)
764 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
765 struct drm_device
*dev
= encoder
->base
.dev
;
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
770 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
772 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
773 flags
|= DRM_MODE_FLAG_PHSYNC
;
775 flags
|= DRM_MODE_FLAG_NHSYNC
;
777 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
778 flags
|= DRM_MODE_FLAG_PVSYNC
;
780 flags
|= DRM_MODE_FLAG_NVSYNC
;
782 if (tmp
& HDMI_MODE_SELECT_HDMI
)
783 pipe_config
->has_hdmi_sink
= true;
785 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
786 pipe_config
->has_infoframe
= true;
788 if (tmp
& SDVO_AUDIO_ENABLE
)
789 pipe_config
->has_audio
= true;
791 if (!HAS_PCH_SPLIT(dev
) &&
792 tmp
& HDMI_COLOR_RANGE_16_235
)
793 pipe_config
->limited_color_range
= true;
795 pipe_config
->adjusted_mode
.flags
|= flags
;
797 if ((tmp
& SDVO_COLOR_FORMAT_MASK
) == HDMI_COLOR_FORMAT_12bpc
)
798 dotclock
= pipe_config
->port_clock
* 2 / 3;
800 dotclock
= pipe_config
->port_clock
;
802 if (HAS_PCH_SPLIT(dev_priv
->dev
))
803 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
805 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
808 static void intel_enable_hdmi(struct intel_encoder
*encoder
)
810 struct drm_device
*dev
= encoder
->base
.dev
;
811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
812 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
813 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
815 u32 enable_bits
= SDVO_ENABLE
;
817 if (intel_crtc
->config
.has_audio
)
818 enable_bits
|= SDVO_AUDIO_ENABLE
;
820 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
822 /* HW workaround for IBX, we need to move the port to transcoder A
823 * before disabling it, so restore the transcoder select bit here. */
824 if (HAS_PCH_IBX(dev
))
825 enable_bits
|= SDVO_PIPE_SEL(intel_crtc
->pipe
);
827 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
828 * we do this anyway which shows more stable in testing.
830 if (HAS_PCH_SPLIT(dev
)) {
831 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
832 POSTING_READ(intel_hdmi
->hdmi_reg
);
837 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
838 POSTING_READ(intel_hdmi
->hdmi_reg
);
840 /* HW workaround, need to write this twice for issue that may result
841 * in first write getting masked.
843 if (HAS_PCH_SPLIT(dev
)) {
844 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
845 POSTING_READ(intel_hdmi
->hdmi_reg
);
848 if (intel_crtc
->config
.has_audio
) {
849 WARN_ON(!intel_crtc
->config
.has_hdmi_sink
);
850 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
851 pipe_name(intel_crtc
->pipe
));
852 intel_audio_codec_enable(encoder
);
856 static void vlv_enable_hdmi(struct intel_encoder
*encoder
)
860 static void intel_disable_hdmi(struct intel_encoder
*encoder
)
862 struct drm_device
*dev
= encoder
->base
.dev
;
863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
864 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
865 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
867 u32 enable_bits
= SDVO_ENABLE
| SDVO_AUDIO_ENABLE
;
869 if (crtc
->config
.has_audio
)
870 intel_audio_codec_disable(encoder
);
872 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
874 /* HW workaround for IBX, we need to move the port to transcoder A
875 * before disabling it. */
876 if (HAS_PCH_IBX(dev
)) {
877 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
878 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
880 if (temp
& SDVO_PIPE_B_SELECT
) {
881 temp
&= ~SDVO_PIPE_B_SELECT
;
882 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
883 POSTING_READ(intel_hdmi
->hdmi_reg
);
885 /* Again we need to write this twice. */
886 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
887 POSTING_READ(intel_hdmi
->hdmi_reg
);
889 /* Transcoder selection bits only update
890 * effectively on vblank. */
892 intel_wait_for_vblank(dev
, pipe
);
898 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
899 * we do this anyway which shows more stable in testing.
901 if (HAS_PCH_SPLIT(dev
)) {
902 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
903 POSTING_READ(intel_hdmi
->hdmi_reg
);
906 temp
&= ~enable_bits
;
908 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
909 POSTING_READ(intel_hdmi
->hdmi_reg
);
911 /* HW workaround, need to write this twice for issue that may result
912 * in first write getting masked.
914 if (HAS_PCH_SPLIT(dev
)) {
915 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
916 POSTING_READ(intel_hdmi
->hdmi_reg
);
920 static int hdmi_portclock_limit(struct intel_hdmi
*hdmi
, bool respect_dvi_limit
)
922 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
924 if ((respect_dvi_limit
&& !hdmi
->has_hdmi_sink
) || IS_G4X(dev
))
926 else if (IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8)
932 static enum drm_mode_status
933 intel_hdmi_mode_valid(struct drm_connector
*connector
,
934 struct drm_display_mode
*mode
)
936 int clock
= mode
->clock
;
938 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
941 if (clock
> hdmi_portclock_limit(intel_attached_hdmi(connector
),
943 return MODE_CLOCK_HIGH
;
945 return MODE_CLOCK_LOW
;
947 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
948 return MODE_NO_DBLESCAN
;
953 static bool hdmi_12bpc_possible(struct intel_crtc
*crtc
)
955 struct drm_device
*dev
= crtc
->base
.dev
;
956 struct intel_encoder
*encoder
;
957 int count
= 0, count_hdmi
= 0;
959 if (HAS_GMCH_DISPLAY(dev
))
962 for_each_intel_encoder(dev
, encoder
) {
963 if (encoder
->new_crtc
!= crtc
)
966 count_hdmi
+= encoder
->type
== INTEL_OUTPUT_HDMI
;
971 * HDMI 12bpc affects the clocks, so it's only possible
972 * when not cloning with other encoder types.
974 return count_hdmi
> 0 && count_hdmi
== count
;
977 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
978 struct intel_crtc_config
*pipe_config
)
980 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
981 struct drm_device
*dev
= encoder
->base
.dev
;
982 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
983 int clock_12bpc
= pipe_config
->adjusted_mode
.crtc_clock
* 3 / 2;
984 int portclock_limit
= hdmi_portclock_limit(intel_hdmi
, false);
987 pipe_config
->has_hdmi_sink
= intel_hdmi
->has_hdmi_sink
;
989 if (pipe_config
->has_hdmi_sink
)
990 pipe_config
->has_infoframe
= true;
992 if (intel_hdmi
->color_range_auto
) {
993 /* See CEA-861-E - 5.1 Default Encoding Parameters */
994 if (pipe_config
->has_hdmi_sink
&&
995 drm_match_cea_mode(adjusted_mode
) > 1)
996 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
998 intel_hdmi
->color_range
= 0;
1001 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
) {
1002 pipe_config
->pixel_multiplier
= 2;
1005 if (intel_hdmi
->color_range
)
1006 pipe_config
->limited_color_range
= true;
1008 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
))
1009 pipe_config
->has_pch_encoder
= true;
1011 if (pipe_config
->has_hdmi_sink
&& intel_hdmi
->has_audio
)
1012 pipe_config
->has_audio
= true;
1015 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1016 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1017 * outputs. We also need to check that the higher clock still fits
1020 if (pipe_config
->pipe_bpp
> 8*3 && pipe_config
->has_hdmi_sink
&&
1021 clock_12bpc
<= portclock_limit
&&
1022 hdmi_12bpc_possible(encoder
->new_crtc
)) {
1023 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1026 /* Need to adjust the port link by 1.5x for 12bpc. */
1027 pipe_config
->port_clock
= clock_12bpc
;
1029 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1033 if (!pipe_config
->bw_constrained
) {
1034 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp
);
1035 pipe_config
->pipe_bpp
= desired_bpp
;
1038 if (adjusted_mode
->crtc_clock
> portclock_limit
) {
1039 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1047 intel_hdmi_unset_edid(struct drm_connector
*connector
)
1049 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1051 intel_hdmi
->has_hdmi_sink
= false;
1052 intel_hdmi
->has_audio
= false;
1053 intel_hdmi
->rgb_quant_range_selectable
= false;
1055 kfree(to_intel_connector(connector
)->detect_edid
);
1056 to_intel_connector(connector
)->detect_edid
= NULL
;
1060 intel_hdmi_set_edid(struct drm_connector
*connector
)
1062 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
1063 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1064 struct intel_encoder
*intel_encoder
=
1065 &hdmi_to_dig_port(intel_hdmi
)->base
;
1066 enum intel_display_power_domain power_domain
;
1068 bool connected
= false;
1070 power_domain
= intel_display_port_power_domain(intel_encoder
);
1071 intel_display_power_get(dev_priv
, power_domain
);
1073 edid
= drm_get_edid(connector
,
1074 intel_gmbus_get_adapter(dev_priv
,
1075 intel_hdmi
->ddc_bus
));
1077 intel_display_power_put(dev_priv
, power_domain
);
1079 to_intel_connector(connector
)->detect_edid
= edid
;
1080 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
1081 intel_hdmi
->rgb_quant_range_selectable
=
1082 drm_rgb_quant_range_selectable(edid
);
1084 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
1085 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
1086 intel_hdmi
->has_audio
=
1087 intel_hdmi
->force_audio
== HDMI_AUDIO_ON
;
1089 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
1090 intel_hdmi
->has_hdmi_sink
=
1091 drm_detect_hdmi_monitor(edid
);
1099 static enum drm_connector_status
1100 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
1102 enum drm_connector_status status
;
1104 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1105 connector
->base
.id
, connector
->name
);
1107 intel_hdmi_unset_edid(connector
);
1109 if (intel_hdmi_set_edid(connector
)) {
1110 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1112 hdmi_to_dig_port(intel_hdmi
)->base
.type
= INTEL_OUTPUT_HDMI
;
1113 status
= connector_status_connected
;
1115 status
= connector_status_disconnected
;
1121 intel_hdmi_force(struct drm_connector
*connector
)
1123 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1125 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1126 connector
->base
.id
, connector
->name
);
1128 intel_hdmi_unset_edid(connector
);
1130 if (connector
->status
!= connector_status_connected
)
1133 intel_hdmi_set_edid(connector
);
1134 hdmi_to_dig_port(intel_hdmi
)->base
.type
= INTEL_OUTPUT_HDMI
;
1137 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
1141 edid
= to_intel_connector(connector
)->detect_edid
;
1145 return intel_connector_update_modes(connector
, edid
);
1149 intel_hdmi_detect_audio(struct drm_connector
*connector
)
1151 bool has_audio
= false;
1154 edid
= to_intel_connector(connector
)->detect_edid
;
1155 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
)
1156 has_audio
= drm_detect_monitor_audio(edid
);
1162 intel_hdmi_set_property(struct drm_connector
*connector
,
1163 struct drm_property
*property
,
1166 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1167 struct intel_digital_port
*intel_dig_port
=
1168 hdmi_to_dig_port(intel_hdmi
);
1169 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1172 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
1176 if (property
== dev_priv
->force_audio_property
) {
1177 enum hdmi_force_audio i
= val
;
1180 if (i
== intel_hdmi
->force_audio
)
1183 intel_hdmi
->force_audio
= i
;
1185 if (i
== HDMI_AUDIO_AUTO
)
1186 has_audio
= intel_hdmi_detect_audio(connector
);
1188 has_audio
= (i
== HDMI_AUDIO_ON
);
1190 if (i
== HDMI_AUDIO_OFF_DVI
)
1191 intel_hdmi
->has_hdmi_sink
= 0;
1193 intel_hdmi
->has_audio
= has_audio
;
1197 if (property
== dev_priv
->broadcast_rgb_property
) {
1198 bool old_auto
= intel_hdmi
->color_range_auto
;
1199 uint32_t old_range
= intel_hdmi
->color_range
;
1202 case INTEL_BROADCAST_RGB_AUTO
:
1203 intel_hdmi
->color_range_auto
= true;
1205 case INTEL_BROADCAST_RGB_FULL
:
1206 intel_hdmi
->color_range_auto
= false;
1207 intel_hdmi
->color_range
= 0;
1209 case INTEL_BROADCAST_RGB_LIMITED
:
1210 intel_hdmi
->color_range_auto
= false;
1211 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
1217 if (old_auto
== intel_hdmi
->color_range_auto
&&
1218 old_range
== intel_hdmi
->color_range
)
1224 if (property
== connector
->dev
->mode_config
.aspect_ratio_property
) {
1226 case DRM_MODE_PICTURE_ASPECT_NONE
:
1227 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_NONE
;
1229 case DRM_MODE_PICTURE_ASPECT_4_3
:
1230 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
;
1232 case DRM_MODE_PICTURE_ASPECT_16_9
:
1233 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
;
1244 if (intel_dig_port
->base
.base
.crtc
)
1245 intel_crtc_restore_mode(intel_dig_port
->base
.base
.crtc
);
1250 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
)
1252 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1253 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1254 struct drm_display_mode
*adjusted_mode
=
1255 &intel_crtc
->config
.adjusted_mode
;
1257 intel_hdmi_prepare(encoder
);
1259 intel_hdmi
->set_infoframes(&encoder
->base
,
1260 intel_crtc
->config
.has_hdmi_sink
,
1264 static void vlv_hdmi_pre_enable(struct intel_encoder
*encoder
)
1266 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1267 struct intel_hdmi
*intel_hdmi
= &dport
->hdmi
;
1268 struct drm_device
*dev
= encoder
->base
.dev
;
1269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1270 struct intel_crtc
*intel_crtc
=
1271 to_intel_crtc(encoder
->base
.crtc
);
1272 struct drm_display_mode
*adjusted_mode
=
1273 &intel_crtc
->config
.adjusted_mode
;
1274 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1275 int pipe
= intel_crtc
->pipe
;
1278 /* Enable clock channels for this port */
1279 mutex_lock(&dev_priv
->dpio_lock
);
1280 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1287 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1290 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0);
1291 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), 0x2b245f5f);
1292 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
), 0x5578b83a);
1293 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0c782040);
1294 vlv_dpio_write(dev_priv
, pipe
, VLV_TX3_DW4(port
), 0x2b247878);
1295 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
1296 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), 0x00002000);
1297 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), DPIO_TX_OCALINIT_EN
);
1299 /* Program lane clock */
1300 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1301 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1302 mutex_unlock(&dev_priv
->dpio_lock
);
1304 intel_hdmi
->set_infoframes(&encoder
->base
,
1305 intel_crtc
->config
.has_hdmi_sink
,
1308 intel_enable_hdmi(encoder
);
1310 vlv_wait_port_ready(dev_priv
, dport
);
1313 static void vlv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1315 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1316 struct drm_device
*dev
= encoder
->base
.dev
;
1317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1318 struct intel_crtc
*intel_crtc
=
1319 to_intel_crtc(encoder
->base
.crtc
);
1320 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1321 int pipe
= intel_crtc
->pipe
;
1323 intel_hdmi_prepare(encoder
);
1325 /* Program Tx lane resets to default */
1326 mutex_lock(&dev_priv
->dpio_lock
);
1327 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
1328 DPIO_PCS_TX_LANE2_RESET
|
1329 DPIO_PCS_TX_LANE1_RESET
);
1330 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
1331 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1332 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1333 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1334 DPIO_PCS_CLK_SOFT_RESET
);
1336 /* Fix up inter-pair skew failure */
1337 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
1338 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
1339 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
1341 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), 0x00002000);
1342 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), DPIO_TX_OCALINIT_EN
);
1343 mutex_unlock(&dev_priv
->dpio_lock
);
1346 static void chv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1348 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1349 struct drm_device
*dev
= encoder
->base
.dev
;
1350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1351 struct intel_crtc
*intel_crtc
=
1352 to_intel_crtc(encoder
->base
.crtc
);
1353 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1354 enum pipe pipe
= intel_crtc
->pipe
;
1357 intel_hdmi_prepare(encoder
);
1359 mutex_lock(&dev_priv
->dpio_lock
);
1361 /* program left/right clock distribution */
1362 if (pipe
!= PIPE_B
) {
1363 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1364 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1366 val
|= CHV_BUFLEFTENA1_FORCE
;
1368 val
|= CHV_BUFRIGHTENA1_FORCE
;
1369 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1371 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1372 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1374 val
|= CHV_BUFLEFTENA2_FORCE
;
1376 val
|= CHV_BUFRIGHTENA2_FORCE
;
1377 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1380 /* program clock channel usage */
1381 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
1382 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
1384 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
1386 val
|= CHV_PCS_USEDCLKCHANNEL
;
1387 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
1389 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
1390 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
1392 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
1394 val
|= CHV_PCS_USEDCLKCHANNEL
;
1395 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
1398 * This a a bit weird since generally CL
1399 * matches the pipe, but here we need to
1400 * pick the CL based on the port.
1402 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
1404 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
1406 val
|= CHV_CMN_USEDCLKCHANNEL
;
1407 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
1409 mutex_unlock(&dev_priv
->dpio_lock
);
1412 static void vlv_hdmi_post_disable(struct intel_encoder
*encoder
)
1414 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1415 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1416 struct intel_crtc
*intel_crtc
=
1417 to_intel_crtc(encoder
->base
.crtc
);
1418 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1419 int pipe
= intel_crtc
->pipe
;
1421 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1422 mutex_lock(&dev_priv
->dpio_lock
);
1423 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
), 0x00000000);
1424 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
), 0x00e00060);
1425 mutex_unlock(&dev_priv
->dpio_lock
);
1428 static void chv_hdmi_post_disable(struct intel_encoder
*encoder
)
1430 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1431 struct drm_device
*dev
= encoder
->base
.dev
;
1432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1433 struct intel_crtc
*intel_crtc
=
1434 to_intel_crtc(encoder
->base
.crtc
);
1435 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1436 enum pipe pipe
= intel_crtc
->pipe
;
1439 mutex_lock(&dev_priv
->dpio_lock
);
1441 /* Propagate soft reset to data lane reset */
1442 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
1443 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1444 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
1446 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
1447 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1448 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
1450 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
1451 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1452 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
1454 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
1455 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1456 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
1458 mutex_unlock(&dev_priv
->dpio_lock
);
1461 static void chv_hdmi_pre_enable(struct intel_encoder
*encoder
)
1463 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1464 struct intel_hdmi
*intel_hdmi
= &dport
->hdmi
;
1465 struct drm_device
*dev
= encoder
->base
.dev
;
1466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1467 struct intel_crtc
*intel_crtc
=
1468 to_intel_crtc(encoder
->base
.crtc
);
1469 struct drm_display_mode
*adjusted_mode
=
1470 &intel_crtc
->config
.adjusted_mode
;
1471 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1472 int pipe
= intel_crtc
->pipe
;
1476 mutex_lock(&dev_priv
->dpio_lock
);
1478 /* allow hardware to manage TX FIFO reset source */
1479 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
1480 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
1481 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
1483 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
1484 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
1485 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
1487 /* Deassert soft data lane reset*/
1488 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
1489 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1490 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
1492 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
1493 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1494 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
1496 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
1497 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1498 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
1500 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
1501 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1502 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
1504 /* Program Tx latency optimal setting */
1505 for (i
= 0; i
< 4; i
++) {
1506 /* Set the latency optimal bit */
1507 data
= (i
== 1) ? 0x0 : 0x6;
1508 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
1509 data
<< DPIO_FRC_LATENCY_SHFIT
);
1511 /* Set the upar bit */
1512 data
= (i
== 1) ? 0x0 : 0x1;
1513 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
1514 data
<< DPIO_UPAR_SHIFT
);
1517 /* Data lane stagger programming */
1518 /* FIXME: Fix up value only after power analysis */
1520 /* Clear calc init */
1521 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
1522 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
1523 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
1524 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
1525 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
1527 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
1528 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
1529 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
1530 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
1531 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
1533 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
1534 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
1535 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
1536 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
1538 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
1539 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
1540 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
1541 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
1543 /* FIXME: Program the support xxx V-dB */
1545 for (i
= 0; i
< 4; i
++) {
1546 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
1547 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
1548 val
|= 128 << DPIO_SWING_DEEMPH9P5_SHIFT
;
1549 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
1552 for (i
= 0; i
< 4; i
++) {
1553 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
1554 val
&= ~DPIO_SWING_MARGIN000_MASK
;
1555 val
|= 102 << DPIO_SWING_MARGIN000_SHIFT
;
1556 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
1559 /* Disable unique transition scale */
1560 for (i
= 0; i
< 4; i
++) {
1561 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
1562 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
1563 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
1566 /* Additional steps for 1200mV-0dB */
1568 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_TX_DW3(ch
));
1570 val
|= DPIO_TX_UNIQ_TRANS_SCALE_CH1
;
1572 val
|= DPIO_TX_UNIQ_TRANS_SCALE_CH0
;
1573 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(ch
), val
);
1575 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(ch
),
1576 vlv_dpio_read(dev_priv
, pipe
, VLV_TX_DW2(ch
)) |
1577 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
));
1579 /* Start swing calculation */
1580 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
1581 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
1582 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
1584 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
1585 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
1586 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
1589 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
1590 val
|= DPIO_LRC_BYPASS
;
1591 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
1593 mutex_unlock(&dev_priv
->dpio_lock
);
1595 intel_hdmi
->set_infoframes(&encoder
->base
,
1596 intel_crtc
->config
.has_hdmi_sink
,
1599 intel_enable_hdmi(encoder
);
1601 vlv_wait_port_ready(dev_priv
, dport
);
1604 static void intel_hdmi_destroy(struct drm_connector
*connector
)
1606 kfree(to_intel_connector(connector
)->detect_edid
);
1607 drm_connector_cleanup(connector
);
1611 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
1612 .dpms
= intel_connector_dpms
,
1613 .detect
= intel_hdmi_detect
,
1614 .force
= intel_hdmi_force
,
1615 .fill_modes
= drm_helper_probe_single_connector_modes
,
1616 .set_property
= intel_hdmi_set_property
,
1617 .destroy
= intel_hdmi_destroy
,
1620 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
1621 .get_modes
= intel_hdmi_get_modes
,
1622 .mode_valid
= intel_hdmi_mode_valid
,
1623 .best_encoder
= intel_best_encoder
,
1626 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
1627 .destroy
= intel_encoder_destroy
,
1631 intel_attach_aspect_ratio_property(struct drm_connector
*connector
)
1633 if (!drm_mode_create_aspect_ratio_property(connector
->dev
))
1634 drm_object_attach_property(&connector
->base
,
1635 connector
->dev
->mode_config
.aspect_ratio_property
,
1636 DRM_MODE_PICTURE_ASPECT_NONE
);
1640 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
1642 intel_attach_force_audio_property(connector
);
1643 intel_attach_broadcast_rgb_property(connector
);
1644 intel_hdmi
->color_range_auto
= true;
1645 intel_attach_aspect_ratio_property(connector
);
1646 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_NONE
;
1649 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1650 struct intel_connector
*intel_connector
)
1652 struct drm_connector
*connector
= &intel_connector
->base
;
1653 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
1654 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1655 struct drm_device
*dev
= intel_encoder
->base
.dev
;
1656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1657 enum port port
= intel_dig_port
->port
;
1659 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
1660 DRM_MODE_CONNECTOR_HDMIA
);
1661 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
1663 connector
->interlace_allowed
= 1;
1664 connector
->doublescan_allowed
= 0;
1665 connector
->stereo_allowed
= 1;
1669 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
1670 intel_encoder
->hpd_pin
= HPD_PORT_B
;
1673 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
1674 intel_encoder
->hpd_pin
= HPD_PORT_C
;
1677 if (IS_CHERRYVIEW(dev
))
1678 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD_CHV
;
1680 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
1681 intel_encoder
->hpd_pin
= HPD_PORT_D
;
1684 intel_encoder
->hpd_pin
= HPD_PORT_A
;
1685 /* Internal port only for eDP. */
1690 if (IS_VALLEYVIEW(dev
)) {
1691 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
1692 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
1693 intel_hdmi
->infoframe_enabled
= vlv_infoframe_enabled
;
1694 } else if (IS_G4X(dev
)) {
1695 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
1696 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
1697 intel_hdmi
->infoframe_enabled
= g4x_infoframe_enabled
;
1698 } else if (HAS_DDI(dev
)) {
1699 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
1700 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
1701 intel_hdmi
->infoframe_enabled
= hsw_infoframe_enabled
;
1702 } else if (HAS_PCH_IBX(dev
)) {
1703 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
1704 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
1705 intel_hdmi
->infoframe_enabled
= ibx_infoframe_enabled
;
1707 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
1708 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
1709 intel_hdmi
->infoframe_enabled
= cpt_infoframe_enabled
;
1713 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
1715 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1716 intel_connector
->unregister
= intel_connector_unregister
;
1718 intel_hdmi_add_properties(intel_hdmi
, connector
);
1720 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1721 drm_connector_register(connector
);
1723 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1724 * 0xd. Failure to do so will result in spurious interrupts being
1725 * generated on the port when a cable is not attached.
1727 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1728 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1729 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
1733 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
)
1735 struct intel_digital_port
*intel_dig_port
;
1736 struct intel_encoder
*intel_encoder
;
1737 struct intel_connector
*intel_connector
;
1739 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
1740 if (!intel_dig_port
)
1743 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
1744 if (!intel_connector
) {
1745 kfree(intel_dig_port
);
1749 intel_encoder
= &intel_dig_port
->base
;
1751 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
1752 DRM_MODE_ENCODER_TMDS
);
1754 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
1755 intel_encoder
->disable
= intel_disable_hdmi
;
1756 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
1757 intel_encoder
->get_config
= intel_hdmi_get_config
;
1758 if (IS_CHERRYVIEW(dev
)) {
1759 intel_encoder
->pre_pll_enable
= chv_hdmi_pre_pll_enable
;
1760 intel_encoder
->pre_enable
= chv_hdmi_pre_enable
;
1761 intel_encoder
->enable
= vlv_enable_hdmi
;
1762 intel_encoder
->post_disable
= chv_hdmi_post_disable
;
1763 } else if (IS_VALLEYVIEW(dev
)) {
1764 intel_encoder
->pre_pll_enable
= vlv_hdmi_pre_pll_enable
;
1765 intel_encoder
->pre_enable
= vlv_hdmi_pre_enable
;
1766 intel_encoder
->enable
= vlv_enable_hdmi
;
1767 intel_encoder
->post_disable
= vlv_hdmi_post_disable
;
1769 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
1770 intel_encoder
->enable
= intel_enable_hdmi
;
1773 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
1774 if (IS_CHERRYVIEW(dev
)) {
1776 intel_encoder
->crtc_mask
= 1 << 2;
1778 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
1780 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1782 intel_encoder
->cloneable
= 1 << INTEL_OUTPUT_ANALOG
;
1784 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1785 * to work on real hardware. And since g4x can send infoframes to
1786 * only one port anyway, nothing is lost by allowing it.
1789 intel_encoder
->cloneable
|= 1 << INTEL_OUTPUT_HDMI
;
1791 intel_dig_port
->port
= port
;
1792 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
1793 intel_dig_port
->dp
.output_reg
= 0;
1795 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);