drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include <linux/export.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37
  38 /* Intel GPIO access functions */
  39
  40 #define I2C_RISEFALL_TIME 10
  41
  42 static inline struct intel_gmbus *
  43 to_intel_gmbus(struct i2c_adapter *i2c)
  44 {
  45         return container_of(i2c, struct intel_gmbus, adapter);
  46 }
  47
  48 struct intel_gpio {
  49         struct i2c_adapter adapter;
  50         struct i2c_algo_bit_data algo;
  51         struct drm_i915_private *dev_priv;
  52         u32 reg;
  53 };
  54
  55 void
  56 intel_i2c_reset(struct drm_device *dev)
  57 {
  58         struct drm_i915_private *dev_priv = dev->dev_private;
  59         if (HAS_PCH_SPLIT(dev))
  60                 I915_WRITE(PCH_GMBUS0, 0);
  61         else
  62                 I915_WRITE(GMBUS0, 0);
  63 }
  64
  65 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  66 {
  67         u32 val;
  68
  69         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  70         if (!IS_PINEVIEW(dev_priv->dev))
  71                 return;
  72
  73         val = I915_READ(DSPCLK_GATE_D);
  74         if (enable)
  75                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  76         else
  77                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  78         I915_WRITE(DSPCLK_GATE_D, val);
  79 }
  80
  81 static u32 get_reserved(struct intel_gpio *gpio)
  82 {
  83         struct drm_i915_private *dev_priv = gpio->dev_priv;
  84         struct drm_device *dev = dev_priv->dev;
  85         u32 reserved = 0;
  86
  87         /* On most chips, these bits must be preserved in software. */
  88         if (!IS_I830(dev) && !IS_845G(dev))
  89                 reserved = I915_READ_NOTRACE(gpio->reg) &
  90                                              (GPIO_DATA_PULLUP_DISABLE |
  91                                               GPIO_CLOCK_PULLUP_DISABLE);
  92
  93         return reserved;
  94 }
  95
  96 static int get_clock(void *data)
  97 {
  98         struct intel_gpio *gpio = data;
  99         struct drm_i915_private *dev_priv = gpio->dev_priv;
 100         u32 reserved = get_reserved(gpio);
 101         I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
 102         I915_WRITE_NOTRACE(gpio->reg, reserved);
 103         return (I915_READ_NOTRACE(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
 104 }
 105
 106 static int get_data(void *data)
 107 {
 108         struct intel_gpio *gpio = data;
 109         struct drm_i915_private *dev_priv = gpio->dev_priv;
 110         u32 reserved = get_reserved(gpio);
 111         I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
 112         I915_WRITE_NOTRACE(gpio->reg, reserved);
 113         return (I915_READ_NOTRACE(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
 114 }
 115
 116 static void set_clock(void *data, int state_high)
 117 {
 118         struct intel_gpio *gpio = data;
 119         struct drm_i915_private *dev_priv = gpio->dev_priv;
 120         u32 reserved = get_reserved(gpio);
 121         u32 clock_bits;
 122
 123         if (state_high)
 124                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 125         else
 126                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 127                         GPIO_CLOCK_VAL_MASK;
 128
 129         I915_WRITE_NOTRACE(gpio->reg, reserved | clock_bits);
 130         POSTING_READ(gpio->reg);
 131 }
 132
 133 static void set_data(void *data, int state_high)
 134 {
 135         struct intel_gpio *gpio = data;
 136         struct drm_i915_private *dev_priv = gpio->dev_priv;
 137         u32 reserved = get_reserved(gpio);
 138         u32 data_bits;
 139
 140         if (state_high)
 141                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 142         else
 143                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 144                         GPIO_DATA_VAL_MASK;
 145
 146         I915_WRITE_NOTRACE(gpio->reg, reserved | data_bits);
 147         POSTING_READ(gpio->reg);
 148 }
 149
 150 static struct i2c_adapter *
 151 intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
 152 {
 153         static const int map_pin_to_reg[] = {
 154                 0,
 155                 GPIOB,
 156                 GPIOA,
 157                 GPIOC,
 158                 GPIOD,
 159                 GPIOE,
 160                 0,
 161                 GPIOF,
 162         };
 163         struct intel_gpio *gpio;
 164
 165         if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
 166                 return NULL;
 167
 168         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
 169         if (gpio == NULL)
 170                 return NULL;
 171
 172         gpio->reg = map_pin_to_reg[pin];
 173         if (HAS_PCH_SPLIT(dev_priv->dev))
 174                 gpio->reg += PCH_GPIOA - GPIOA;
 175         gpio->dev_priv = dev_priv;
 176
 177         snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
 178                  "i915 GPIO%c", "?BACDE?F"[pin]);
 179         gpio->adapter.owner = THIS_MODULE;
 180         gpio->adapter.algo_data = &gpio->algo;
 181         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
 182         gpio->algo.setsda = set_data;
 183         gpio->algo.setscl = set_clock;
 184         gpio->algo.getsda = get_data;
 185         gpio->algo.getscl = get_clock;
 186         gpio->algo.udelay = I2C_RISEFALL_TIME;
 187         gpio->algo.timeout = usecs_to_jiffies(2200);
 188         gpio->algo.data = gpio;
 189
 190         if (i2c_bit_add_bus(&gpio->adapter))
 191                 goto out_free;
 192
 193         return &gpio->adapter;
 194
 195 out_free:
 196         kfree(gpio);
 197         return NULL;
 198 }
 199
 200 static int
 201 intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
 202                      struct i2c_adapter *adapter,
 203                      struct i2c_msg *msgs,
 204                      int num)
 205 {
 206         struct intel_gpio *gpio = container_of(adapter,
 207                                                struct intel_gpio,
 208                                                adapter);
 209         int ret;
 210
 211         intel_i2c_reset(dev_priv->dev);
 212
 213         intel_i2c_quirk_set(dev_priv, true);
 214         set_data(gpio, 1);
 215         set_clock(gpio, 1);
 216         udelay(I2C_RISEFALL_TIME);
 217
 218         ret = adapter->algo->master_xfer(adapter, msgs, num);
 219
 220         set_data(gpio, 1);
 221         set_clock(gpio, 1);
 222         intel_i2c_quirk_set(dev_priv, false);
 223
 224         return ret;
 225 }
 226
 227 static int
 228 gmbus_xfer(struct i2c_adapter *adapter,
 229            struct i2c_msg *msgs,
 230            int num)
 231 {
 232         struct intel_gmbus *bus = container_of(adapter,
 233                                                struct intel_gmbus,
 234                                                adapter);
 235         struct drm_i915_private *dev_priv = adapter->algo_data;
 236         int i, reg_offset, ret;
 237
 238         mutex_lock(&dev_priv->gmbus_mutex);
 239
 240         if (bus->force_bit) {
 241                 ret = intel_i2c_quirk_xfer(dev_priv,
 242                                             bus->force_bit, msgs, num);
 243                 goto out;
 244         }
 245
 246         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
 247
 248         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
 249
 250         for (i = 0; i < num; i++) {
 251                 u16 len = msgs[i].len;
 252                 u8 *buf = msgs[i].buf;
 253
 254                 if (msgs[i].flags & I2C_M_RD) {
 255                         I915_WRITE(GMBUS1 + reg_offset,
 256                                    GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
 257                                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 258                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 259                                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 260                         POSTING_READ(GMBUS2+reg_offset);
 261                         do {
 262                                 u32 val, loop = 0;
 263
 264                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 265                                         goto timeout;
 266                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 267                                         goto clear_err;
 268
 269                                 val = I915_READ(GMBUS3 + reg_offset);
 270                                 do {
 271                                         *buf++ = val & 0xff;
 272                                         val >>= 8;
 273                                 } while (--len && ++loop < 4);
 274                         } while (len);
 275                 } else {
 276                         u32 val, loop;
 277
 278                         val = loop = 0;
 279                         do {
 280                                 val |= *buf++ << (8 * loop);
 281                         } while (--len && ++loop < 4);
 282
 283                         I915_WRITE(GMBUS3 + reg_offset, val);
 284                         I915_WRITE(GMBUS1 + reg_offset,
 285                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
 286                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 287                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 288                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 289                         POSTING_READ(GMBUS2+reg_offset);
 290
 291                         while (len) {
 292                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 293                                         goto timeout;
 294                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 295                                         goto clear_err;
 296
 297                                 val = loop = 0;
 298                                 do {
 299                                         val |= *buf++ << (8 * loop);
 300                                 } while (--len && ++loop < 4);
 301
 302                                 I915_WRITE(GMBUS3 + reg_offset, val);
 303                                 POSTING_READ(GMBUS2+reg_offset);
 304                         }
 305                 }
 306
 307                 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
 308                         goto timeout;
 309                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 310                         goto clear_err;
 311         }
 312
 313         goto done;
 314
 315 clear_err:
 316         /* Toggle the Software Clear Interrupt bit. This has the effect
 317          * of resetting the GMBUS controller and so clearing the
 318          * BUS_ERROR raised by the slave's NAK.
 319          */
 320         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 321         I915_WRITE(GMBUS1 + reg_offset, 0);
 322
 323 done:
 324         /* Mark the GMBUS interface as disabled. We will re-enable it at the
 325          * start of the next xfer, till then let it sleep.
 326          */
 327         I915_WRITE(GMBUS0 + reg_offset, 0);
 328         ret = i;
 329         goto out;
 330
 331 timeout:
 332         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
 333                  bus->reg0 & 0xff, bus->adapter.name);
 334         I915_WRITE(GMBUS0 + reg_offset, 0);
 335
 336         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 337         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
 338         if (!bus->force_bit)
 339                 ret = -ENOMEM;
 340         else
 341                 ret = intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
 342 out:
 343         mutex_unlock(&dev_priv->gmbus_mutex);
 344         return ret;
 345 }
 346
 347 static u32 gmbus_func(struct i2c_adapter *adapter)
 348 {
 349         struct intel_gmbus *bus = container_of(adapter,
 350                                                struct intel_gmbus,
 351                                                adapter);
 352
 353         if (bus->force_bit)
 354                 bus->force_bit->algo->functionality(bus->force_bit);
 355
 356         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 357                 /* I2C_FUNC_10BIT_ADDR | */
 358                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 359                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 360 }
 361
 362 static const struct i2c_algorithm gmbus_algorithm = {
 363         .master_xfer    = gmbus_xfer,
 364         .functionality  = gmbus_func
 365 };
 366
 367 /**
 368  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 369  * @dev: DRM device
 370  */
 371 int intel_setup_gmbus(struct drm_device *dev)
 372 {
 373         static const char *names[GMBUS_NUM_PORTS] = {
 374                 "disabled",
 375                 "ssc",
 376                 "vga",
 377                 "panel",
 378                 "dpc",
 379                 "dpb",
 380                 "reserved",
 381                 "dpd",
 382         };
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         int ret, i;
 385
 386         dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
 387                                   GFP_KERNEL);
 388         if (dev_priv->gmbus == NULL)
 389                 return -ENOMEM;
 390
 391         mutex_init(&dev_priv->gmbus_mutex);
 392
 393         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 394                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 395
 396                 bus->adapter.owner = THIS_MODULE;
 397                 bus->adapter.class = I2C_CLASS_DDC;
 398                 snprintf(bus->adapter.name,
 399                          sizeof(bus->adapter.name),
 400                          "i915 gmbus %s",
 401                          names[i]);
 402
 403                 bus->adapter.dev.parent = &dev->pdev->dev;
 404                 bus->adapter.algo_data  = dev_priv;
 405
 406                 bus->adapter.algo = &gmbus_algorithm;
 407                 ret = i2c_add_adapter(&bus->adapter);
 408                 if (ret)
 409                         goto err;
 410
 411                 /* By default use a conservative clock rate */
 412                 bus->reg0 = i | GMBUS_RATE_100KHZ;
 413
 414                 /* XXX force bit banging until GMBUS is fully debugged */
 415                 bus->force_bit = intel_gpio_create(dev_priv, i);
 416         }
 417
 418         intel_i2c_reset(dev_priv->dev);
 419
 420         return 0;
 421
 422 err:
 423         while (--i) {
 424                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 425                 i2c_del_adapter(&bus->adapter);
 426         }
 427         kfree(dev_priv->gmbus);
 428         dev_priv->gmbus = NULL;
 429         return ret;
 430 }
 431
 432 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 433 {
 434         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 435
 436         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 437 }
 438
 439 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 440 {
 441         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 442
 443         if (force_bit) {
 444                 if (bus->force_bit == NULL) {
 445                         struct drm_i915_private *dev_priv = adapter->algo_data;
 446                         bus->force_bit = intel_gpio_create(dev_priv,
 447                                                            bus->reg0 & 0xff);
 448                 }
 449         } else {
 450                 if (bus->force_bit) {
 451                         i2c_del_adapter(bus->force_bit);
 452                         kfree(bus->force_bit);
 453                         bus->force_bit = NULL;
 454                 }
 455         }
 456 }
 457
 458 void intel_teardown_gmbus(struct drm_device *dev)
 459 {
 460         struct drm_i915_private *dev_priv = dev->dev_private;
 461         int i;
 462
 463         if (dev_priv->gmbus == NULL)
 464                 return;
 465
 466         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 467                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 468                 if (bus->force_bit) {
 469                         i2c_del_adapter(bus->force_bit);
 470                         kfree(bus->force_bit);
 471                 }
 472                 i2c_del_adapter(&bus->adapter);
 473         }
 474
 475         kfree(dev_priv->gmbus);
 476         dev_priv->gmbus = NULL;
 477 }