drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36
  37 /* Intel GPIO access functions */
  38
  39 #define I2C_RISEFALL_TIME 20
  40
  41 struct intel_gpio {
  42         struct i2c_adapter adapter;
  43         struct i2c_algo_bit_data algo;
  44         struct drm_i915_private *dev_priv;
  45         u32 reg;
  46 };
  47
  48 void
  49 intel_i2c_reset(struct drm_device *dev)
  50 {
  51         struct drm_i915_private *dev_priv = dev->dev_private;
  52         if (HAS_PCH_SPLIT(dev))
  53                 I915_WRITE(PCH_GMBUS0, 0);
  54         else
  55                 I915_WRITE(GMBUS0, 0);
  56 }
  57
  58 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  59 {
  60         u32 val;
  61
  62         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  63         if (!IS_PINEVIEW(dev_priv->dev))
  64                 return;
  65
  66         val = I915_READ(DSPCLK_GATE_D);
  67         if (enable)
  68                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  69         else
  70                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  71         I915_WRITE(DSPCLK_GATE_D, val);
  72 }
  73
  74 static int get_clock(void *data)
  75 {
  76         struct intel_gpio *gpio = data;
  77         struct drm_i915_private *dev_priv = gpio->dev_priv;
  78         return (I915_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
  79 }
  80
  81 static int get_data(void *data)
  82 {
  83         struct intel_gpio *gpio = data;
  84         struct drm_i915_private *dev_priv = gpio->dev_priv;
  85         return (I915_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
  86 }
  87
  88 static void set_clock(void *data, int state_high)
  89 {
  90         struct intel_gpio *gpio = data;
  91         struct drm_i915_private *dev_priv = gpio->dev_priv;
  92         struct drm_device *dev = dev_priv->dev;
  93         u32 reserved = 0, clock_bits;
  94
  95         /* On most chips, these bits must be preserved in software. */
  96         if (!IS_I830(dev) && !IS_845G(dev))
  97                 reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
  98                                                    GPIO_CLOCK_PULLUP_DISABLE);
  99
 100         if (state_high)
 101                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 102         else
 103                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 104                         GPIO_CLOCK_VAL_MASK;
 105
 106         I915_WRITE(gpio->reg, reserved | clock_bits);
 107         POSTING_READ(gpio->reg);
 108 }
 109
 110 static void set_data(void *data, int state_high)
 111 {
 112         struct intel_gpio *gpio = data;
 113         struct drm_i915_private *dev_priv = gpio->dev_priv;
 114         struct drm_device *dev = dev_priv->dev;
 115         u32 reserved = 0, data_bits;
 116
 117         /* On most chips, these bits must be preserved in software. */
 118         if (!IS_I830(dev) && !IS_845G(dev))
 119                 reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
 120                                                    GPIO_CLOCK_PULLUP_DISABLE);
 121
 122         if (state_high)
 123                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 124         else
 125                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 126                         GPIO_DATA_VAL_MASK;
 127
 128         I915_WRITE(gpio->reg, reserved | data_bits);
 129         POSTING_READ(gpio->reg);
 130 }
 131
 132 static struct i2c_adapter *
 133 intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
 134 {
 135         static const int map_pin_to_reg[] = {
 136                 0,
 137                 GPIOB,
 138                 GPIOA,
 139                 GPIOC,
 140                 GPIOD,
 141                 GPIOE,
 142                 GPIOF,
 143         };
 144         struct intel_gpio *gpio;
 145
 146         if (pin < 1 || pin > 7)
 147                 return NULL;
 148
 149         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
 150         if (gpio == NULL)
 151                 return NULL;
 152
 153         gpio->reg = map_pin_to_reg[pin];
 154         if (HAS_PCH_SPLIT(dev_priv->dev))
 155                 gpio->reg += PCH_GPIOA - GPIOA;
 156         gpio->dev_priv = dev_priv;
 157
 158         snprintf(gpio->adapter.name, I2C_NAME_SIZE, "GPIO %d", pin);
 159         gpio->adapter.owner = THIS_MODULE;
 160         gpio->adapter.algo_data = &gpio->algo;
 161         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
 162         gpio->algo.setsda = set_data;
 163         gpio->algo.setscl = set_clock;
 164         gpio->algo.getsda = get_data;
 165         gpio->algo.getscl = get_clock;
 166         gpio->algo.udelay = I2C_RISEFALL_TIME;
 167         gpio->algo.timeout = usecs_to_jiffies(2200);
 168         gpio->algo.data = gpio;
 169
 170         if (i2c_bit_add_bus(&gpio->adapter))
 171                 goto out_free;
 172
 173         intel_i2c_reset(dev_priv->dev);
 174
 175         /* JJJ:  raise SCL and SDA? */
 176         intel_i2c_quirk_set(dev_priv, true);
 177         set_data(gpio, 1);
 178         udelay(I2C_RISEFALL_TIME);
 179         set_clock(gpio, 1);
 180         udelay(I2C_RISEFALL_TIME);
 181         intel_i2c_quirk_set(dev_priv, false);
 182
 183         return &gpio->adapter;
 184
 185 out_free:
 186         kfree(gpio);
 187         return NULL;
 188 }
 189
 190 static int
 191 quirk_i2c_transfer(struct drm_i915_private *dev_priv,
 192                    struct i2c_adapter *adapter,
 193                    struct i2c_msg *msgs,
 194                    int num)
 195 {
 196         int ret;
 197
 198         intel_i2c_reset(dev_priv->dev);
 199
 200         intel_i2c_quirk_set(dev_priv, true);
 201         ret = i2c_transfer(adapter, msgs, num);
 202         intel_i2c_quirk_set(dev_priv, false);
 203
 204         return ret;
 205 }
 206
 207 static int
 208 gmbus_xfer(struct i2c_adapter *adapter,
 209            struct i2c_msg *msgs,
 210            int num)
 211 {
 212         struct intel_gmbus *bus = container_of(adapter,
 213                                                struct intel_gmbus,
 214                                                adapter);
 215         struct drm_i915_private *dev_priv = adapter->algo_data;
 216         int i, speed, reg_offset;
 217
 218         if (bus->force_bitbanging)
 219                 return quirk_i2c_transfer(dev_priv, bus->force_bitbanging, msgs, num);
 220
 221         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
 222
 223         speed = GMBUS_RATE_100KHZ;
 224         if (INTEL_INFO(dev_priv->dev)->gen > 4 || IS_G4X(dev_priv->dev)) {
 225                 if (bus->pin == GMBUS_PORT_DPB) /* SDVO only? */
 226                         speed = GMBUS_RATE_1MHZ;
 227                 else
 228                         speed = GMBUS_RATE_400KHZ;
 229         }
 230         I915_WRITE(GMBUS0 + reg_offset, speed | bus->pin);
 231
 232         for (i = 0; i < num; i++) {
 233                 u16 len = msgs[i].len;
 234                 u8 *buf = msgs[i].buf;
 235
 236                 if (msgs[i].flags & I2C_M_RD) {
 237                         I915_WRITE(GMBUS1 + reg_offset,
 238                                    GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
 239                                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 240                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 241                                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 242                         do {
 243                                 u32 val, loop = 0;
 244
 245                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 246                                         goto timeout;
 247                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 248                                         return 0;
 249
 250                                 val = I915_READ(GMBUS3 + reg_offset);
 251                                 do {
 252                                         *buf++ = val & 0xff;
 253                                         val >>= 8;
 254                                 } while (--len && ++loop < 4);
 255                         } while (len);
 256                 } else {
 257                         u32 val = 0, loop = 0;
 258
 259                         BUG_ON(msgs[i].len > 4);
 260
 261                         do {
 262                                 val |= *buf++ << (loop*8);
 263                         } while (--len && +loop < 4);
 264
 265                         I915_WRITE(GMBUS3 + reg_offset, val);
 266                         I915_WRITE(GMBUS1 + reg_offset,
 267                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT ) |
 268                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 269                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 270                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 271                 }
 272
 273                 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
 274                         goto timeout;
 275                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 276                         return 0;
 277         }
 278
 279         return num;
 280
 281 timeout:
 282         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d\n", bus->pin);
 283         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 284         bus->force_bitbanging = intel_gpio_create(dev_priv, bus->pin);
 285         if (!bus->force_bitbanging)
 286                 return -ENOMEM;
 287
 288         return quirk_i2c_transfer(dev_priv, bus->force_bitbanging, msgs, num);
 289 }
 290
 291 static u32 gmbus_func(struct i2c_adapter *adapter)
 292 {
 293         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 294                 /* I2C_FUNC_10BIT_ADDR | */
 295                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 296                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 297 }
 298
 299 static const struct i2c_algorithm gmbus_algorithm = {
 300         .master_xfer    = gmbus_xfer,
 301         .functionality  = gmbus_func
 302 };
 303
 304 /**
 305  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 306  * @dev: DRM device
 307  */
 308 int intel_setup_gmbus(struct drm_device *dev)
 309 {
 310         static const char *names[] = {
 311                 "disabled",
 312                 "ssc",
 313                 "vga",
 314                 "panel",
 315                 "dpc",
 316                 "dpb",
 317                 "dpd",
 318                 "reserved"
 319         };
 320         struct drm_i915_private *dev_priv = dev->dev_private;
 321         int ret, i;
 322
 323         dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
 324                                   GFP_KERNEL);
 325         if (dev_priv->gmbus == NULL)
 326                 return -ENOMEM;
 327
 328         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 329                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 330
 331                 bus->adapter.owner = THIS_MODULE;
 332                 bus->adapter.class = I2C_CLASS_DDC;
 333                 snprintf(bus->adapter.name,
 334                          I2C_NAME_SIZE,
 335                          "gmbus %s",
 336                          names[i]);
 337
 338                 bus->adapter.dev.parent = &dev->pdev->dev;
 339                 bus->adapter.algo_data  = dev_priv;
 340
 341                 bus->adapter.algo = &gmbus_algorithm;
 342                 ret = i2c_add_adapter(&bus->adapter);
 343                 if (ret)
 344                         goto err;
 345
 346                 bus->pin = i;
 347         }
 348
 349         intel_i2c_reset(dev_priv->dev);
 350
 351         return 0;
 352
 353 err:
 354         while (--i) {
 355                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 356                 i2c_del_adapter(&bus->adapter);
 357         }
 358         kfree(dev_priv->gmbus);
 359         dev_priv->gmbus = NULL;
 360         return ret;
 361 }
 362
 363 void intel_teardown_gmbus(struct drm_device *dev)
 364 {
 365         struct drm_i915_private *dev_priv = dev->dev_private;
 366         int i;
 367
 368         if (dev_priv->gmbus == NULL)
 369                 return;
 370
 371         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 372                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 373                 if (bus->force_bitbanging) {
 374                         i2c_del_adapter(bus->force_bitbanging);
 375                         kfree(bus->force_bitbanging);
 376                 }
 377                 i2c_del_adapter(&bus->adapter);
 378         }
 379
 380         kfree(dev_priv->gmbus);
 381         dev_priv->gmbus = NULL;
 382 }