drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include <linux/export.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37
  38 struct gmbus_port {
  39         const char *name;
  40         int reg;
  41 };
  42
  43 static const struct gmbus_port gmbus_ports[] = {
  44         { "ssc", GPIOB },
  45         { "vga", GPIOA },
  46         { "panel", GPIOC },
  47         { "dpc", GPIOD },
  48         { "dpb", GPIOE },
  49         { "dpd", GPIOF },
  50 };
  51
  52 /* Intel GPIO access functions */
  53
  54 #define I2C_RISEFALL_TIME 10
  55
  56 static inline struct intel_gmbus *
  57 to_intel_gmbus(struct i2c_adapter *i2c)
  58 {
  59         return container_of(i2c, struct intel_gmbus, adapter);
  60 }
  61
  62 void
  63 intel_i2c_reset(struct drm_device *dev)
  64 {
  65         struct drm_i915_private *dev_priv = dev->dev_private;
  66         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
  67 }
  68
  69 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  70 {
  71         u32 val;
  72
  73         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  74         if (!IS_PINEVIEW(dev_priv->dev))
  75                 return;
  76
  77         val = I915_READ(DSPCLK_GATE_D);
  78         if (enable)
  79                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  80         else
  81                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  82         I915_WRITE(DSPCLK_GATE_D, val);
  83 }
  84
  85 static u32 get_reserved(struct intel_gmbus *bus)
  86 {
  87         struct drm_i915_private *dev_priv = bus->dev_priv;
  88         struct drm_device *dev = dev_priv->dev;
  89         u32 reserved = 0;
  90
  91         /* On most chips, these bits must be preserved in software. */
  92         if (!IS_I830(dev) && !IS_845G(dev))
  93                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
  94                                              (GPIO_DATA_PULLUP_DISABLE |
  95                                               GPIO_CLOCK_PULLUP_DISABLE);
  96
  97         return reserved;
  98 }
  99
 100 static int get_clock(void *data)
 101 {
 102         struct intel_gmbus *bus = data;
 103         struct drm_i915_private *dev_priv = bus->dev_priv;
 104         u32 reserved = get_reserved(bus);
 105         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
 106         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 107         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 108 }
 109
 110 static int get_data(void *data)
 111 {
 112         struct intel_gmbus *bus = data;
 113         struct drm_i915_private *dev_priv = bus->dev_priv;
 114         u32 reserved = get_reserved(bus);
 115         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
 116         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 117         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 118 }
 119
 120 static void set_clock(void *data, int state_high)
 121 {
 122         struct intel_gmbus *bus = data;
 123         struct drm_i915_private *dev_priv = bus->dev_priv;
 124         u32 reserved = get_reserved(bus);
 125         u32 clock_bits;
 126
 127         if (state_high)
 128                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 129         else
 130                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 131                         GPIO_CLOCK_VAL_MASK;
 132
 133         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
 134         POSTING_READ(bus->gpio_reg);
 135 }
 136
 137 static void set_data(void *data, int state_high)
 138 {
 139         struct intel_gmbus *bus = data;
 140         struct drm_i915_private *dev_priv = bus->dev_priv;
 141         u32 reserved = get_reserved(bus);
 142         u32 data_bits;
 143
 144         if (state_high)
 145                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 146         else
 147                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 148                         GPIO_DATA_VAL_MASK;
 149
 150         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
 151         POSTING_READ(bus->gpio_reg);
 152 }
 153
 154 static int
 155 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 156 {
 157         struct intel_gmbus *bus = container_of(adapter,
 158                                                struct intel_gmbus,
 159                                                adapter);
 160         struct drm_i915_private *dev_priv = bus->dev_priv;
 161
 162         intel_i2c_reset(dev_priv->dev);
 163         intel_i2c_quirk_set(dev_priv, true);
 164         set_data(bus, 1);
 165         set_clock(bus, 1);
 166         udelay(I2C_RISEFALL_TIME);
 167         return 0;
 168 }
 169
 170 static void
 171 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 172 {
 173         struct intel_gmbus *bus = container_of(adapter,
 174                                                struct intel_gmbus,
 175                                                adapter);
 176         struct drm_i915_private *dev_priv = bus->dev_priv;
 177
 178         set_data(bus, 1);
 179         set_clock(bus, 1);
 180         intel_i2c_quirk_set(dev_priv, false);
 181 }
 182
 183 static void
 184 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
 185 {
 186         struct drm_i915_private *dev_priv = bus->dev_priv;
 187         struct i2c_algo_bit_data *algo;
 188
 189         algo = &bus->bit_algo;
 190
 191         /* -1 to map pin pair to gmbus index */
 192         bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
 193
 194         bus->adapter.algo_data = algo;
 195         algo->setsda = set_data;
 196         algo->setscl = set_clock;
 197         algo->getsda = get_data;
 198         algo->getscl = get_clock;
 199         algo->pre_xfer = intel_gpio_pre_xfer;
 200         algo->post_xfer = intel_gpio_post_xfer;
 201         algo->udelay = I2C_RISEFALL_TIME;
 202         algo->timeout = usecs_to_jiffies(2200);
 203         algo->data = bus;
 204 }
 205
 206 static int
 207 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 208                 u32 gmbus1_index)
 209 {
 210         int reg_offset = dev_priv->gpio_mmio_base;
 211         u16 len = msg->len;
 212         u8 *buf = msg->buf;
 213
 214         I915_WRITE(GMBUS1 + reg_offset,
 215                    gmbus1_index |
 216                    GMBUS_CYCLE_WAIT |
 217                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 218                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 219                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 220         while (len) {
 221                 int ret;
 222                 u32 val, loop = 0;
 223                 u32 gmbus2;
 224
 225                 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
 226                                (GMBUS_SATOER | GMBUS_HW_RDY),
 227                                50);
 228                 if (ret)
 229                         return -ETIMEDOUT;
 230                 if (gmbus2 & GMBUS_SATOER)
 231                         return -ENXIO;
 232
 233                 val = I915_READ(GMBUS3 + reg_offset);
 234                 do {
 235                         *buf++ = val & 0xff;
 236                         val >>= 8;
 237                 } while (--len && ++loop < 4);
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int
 244 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 245 {
 246         int reg_offset = dev_priv->gpio_mmio_base;
 247         u16 len = msg->len;
 248         u8 *buf = msg->buf;
 249         u32 val, loop;
 250
 251         val = loop = 0;
 252         while (len && loop < 4) {
 253                 val |= *buf++ << (8 * loop++);
 254                 len -= 1;
 255         }
 256
 257         I915_WRITE(GMBUS3 + reg_offset, val);
 258         I915_WRITE(GMBUS1 + reg_offset,
 259                    GMBUS_CYCLE_WAIT |
 260                    (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
 261                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 262                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 263         while (len) {
 264                 int ret;
 265                 u32 gmbus2;
 266
 267                 val = loop = 0;
 268                 do {
 269                         val |= *buf++ << (8 * loop);
 270                 } while (--len && ++loop < 4);
 271
 272                 I915_WRITE(GMBUS3 + reg_offset, val);
 273
 274                 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
 275                                (GMBUS_SATOER | GMBUS_HW_RDY),
 276                                50);
 277                 if (ret)
 278                         return -ETIMEDOUT;
 279                 if (gmbus2 & GMBUS_SATOER)
 280                         return -ENXIO;
 281         }
 282         return 0;
 283 }
 284
 285 /*
 286  * The gmbus controller can combine a 1 or 2 byte write with a read that
 287  * immediately follows it by using an "INDEX" cycle.
 288  */
 289 static bool
 290 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 291 {
 292         return (i + 1 < num &&
 293                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
 294                 (msgs[i + 1].flags & I2C_M_RD));
 295 }
 296
 297 static int
 298 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 299 {
 300         int reg_offset = dev_priv->gpio_mmio_base;
 301         u32 gmbus1_index = 0;
 302         u32 gmbus5 = 0;
 303         int ret;
 304
 305         if (msgs[0].len == 2)
 306                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 307                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 308         if (msgs[0].len == 1)
 309                 gmbus1_index = GMBUS_CYCLE_INDEX |
 310                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 311
 312         /* GMBUS5 holds 16-bit index */
 313         if (gmbus5)
 314                 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
 315
 316         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 317
 318         /* Clear GMBUS5 after each index transfer */
 319         if (gmbus5)
 320                 I915_WRITE(GMBUS5 + reg_offset, 0);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 gmbus_xfer(struct i2c_adapter *adapter,
 327            struct i2c_msg *msgs,
 328            int num)
 329 {
 330         struct intel_gmbus *bus = container_of(adapter,
 331                                                struct intel_gmbus,
 332                                                adapter);
 333         struct drm_i915_private *dev_priv = bus->dev_priv;
 334         int i, reg_offset;
 335         int ret = 0;
 336
 337         mutex_lock(&dev_priv->gmbus_mutex);
 338
 339         if (bus->force_bit) {
 340                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 341                 goto out;
 342         }
 343
 344         reg_offset = dev_priv->gpio_mmio_base;
 345
 346         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
 347
 348         for (i = 0; i < num; i++) {
 349                 u32 gmbus2;
 350
 351                 if (gmbus_is_index_read(msgs, i, num)) {
 352                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
 353                         i += 1;  /* set i to the index of the read xfer */
 354                 } else if (msgs[i].flags & I2C_M_RD) {
 355                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
 356                 } else {
 357                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
 358                 }
 359
 360                 if (ret == -ETIMEDOUT)
 361                         goto timeout;
 362                 if (ret == -ENXIO)
 363                         goto clear_err;
 364
 365                 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
 366                                (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE),
 367                                50);
 368                 if (ret)
 369                         goto timeout;
 370                 if (gmbus2 & GMBUS_SATOER)
 371                         goto clear_err;
 372         }
 373
 374         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 375          * a STOP on the very first cycle. To simplify the code we
 376          * unconditionally generate the STOP condition with an additional gmbus
 377          * cycle. */
 378         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 379
 380         /* Mark the GMBUS interface as disabled after waiting for idle.
 381          * We will re-enable it at the start of the next xfer,
 382          * till then let it sleep.
 383          */
 384         if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
 385                      10)) {
 386                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 387                          adapter->name);
 388                 ret = -ETIMEDOUT;
 389         }
 390         I915_WRITE(GMBUS0 + reg_offset, 0);
 391         ret = ret ?: i;
 392         goto out;
 393
 394 clear_err:
 395         /*
 396          * Wait for bus to IDLE before clearing NAK.
 397          * If we clear the NAK while bus is still active, then it will stay
 398          * active and the next transaction may fail.
 399          *
 400          * If no ACK is received during the address phase of a transaction, the
 401          * adapter must report -ENXIO. It is not clear what to return if no ACK
 402          * is received at other times. But we have to be careful to not return
 403          * spurious -ENXIO because that will prevent i2c and drm edid functions
 404          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 405          * timing out seems to happen when there _is_ a ddc chip present, but
 406          * it's slow responding and only answers on the 2nd retry.
 407          */
 408         ret = -ENXIO;
 409         if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
 410                      10)) {
 411                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 412                               adapter->name);
 413                 ret = -ETIMEDOUT;
 414         }
 415
 416         /* Toggle the Software Clear Interrupt bit. This has the effect
 417          * of resetting the GMBUS controller and so clearing the
 418          * BUS_ERROR raised by the slave's NAK.
 419          */
 420         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 421         I915_WRITE(GMBUS1 + reg_offset, 0);
 422         I915_WRITE(GMBUS0 + reg_offset, 0);
 423
 424         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 425                          adapter->name, msgs[i].addr,
 426                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 427
 428         goto out;
 429
 430 timeout:
 431         DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 432                  bus->adapter.name, bus->reg0 & 0xff);
 433         I915_WRITE(GMBUS0 + reg_offset, 0);
 434
 435         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 436         bus->force_bit = true;
 437         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 438
 439 out:
 440         mutex_unlock(&dev_priv->gmbus_mutex);
 441         return ret;
 442 }
 443
 444 static u32 gmbus_func(struct i2c_adapter *adapter)
 445 {
 446         return i2c_bit_algo.functionality(adapter) &
 447                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 448                 /* I2C_FUNC_10BIT_ADDR | */
 449                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 450                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 451 }
 452
 453 static const struct i2c_algorithm gmbus_algorithm = {
 454         .master_xfer    = gmbus_xfer,
 455         .functionality  = gmbus_func
 456 };
 457
 458 /**
 459  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 460  * @dev: DRM device
 461  */
 462 int intel_setup_gmbus(struct drm_device *dev)
 463 {
 464         struct drm_i915_private *dev_priv = dev->dev_private;
 465         int ret, i;
 466
 467         if (HAS_PCH_SPLIT(dev))
 468                 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
 469         else
 470                 dev_priv->gpio_mmio_base = 0;
 471
 472         mutex_init(&dev_priv->gmbus_mutex);
 473
 474         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 475                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 476                 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
 477
 478                 bus->adapter.owner = THIS_MODULE;
 479                 bus->adapter.class = I2C_CLASS_DDC;
 480                 snprintf(bus->adapter.name,
 481                          sizeof(bus->adapter.name),
 482                          "i915 gmbus %s",
 483                          gmbus_ports[i].name);
 484
 485                 bus->adapter.dev.parent = &dev->pdev->dev;
 486                 bus->dev_priv = dev_priv;
 487
 488                 bus->adapter.algo = &gmbus_algorithm;
 489
 490                 /* By default use a conservative clock rate */
 491                 bus->reg0 = port | GMBUS_RATE_100KHZ;
 492
 493                 /* gmbus seems to be broken on i830 */
 494                 if (IS_I830(dev))
 495                         bus->force_bit = true;
 496
 497                 intel_gpio_setup(bus, port);
 498
 499                 ret = i2c_add_adapter(&bus->adapter);
 500                 if (ret)
 501                         goto err;
 502         }
 503
 504         intel_i2c_reset(dev_priv->dev);
 505
 506         return 0;
 507
 508 err:
 509         while (--i) {
 510                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 511                 i2c_del_adapter(&bus->adapter);
 512         }
 513         return ret;
 514 }
 515
 516 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 517                                             unsigned port)
 518 {
 519         WARN_ON(!intel_gmbus_is_port_valid(port));
 520         /* -1 to map pin pair to gmbus index */
 521         return (intel_gmbus_is_port_valid(port)) ?
 522                 &dev_priv->gmbus[port - 1].adapter : NULL;
 523 }
 524
 525 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 526 {
 527         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 528
 529         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 530 }
 531
 532 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 533 {
 534         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 535
 536         bus->force_bit = force_bit;
 537 }
 538
 539 void intel_teardown_gmbus(struct drm_device *dev)
 540 {
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542         int i;
 543
 544         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 545                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 546                 i2c_del_adapter(&bus->adapter);
 547         }
 548 }