2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT
= 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT
, /* Debug only */
224 FAULT_AND_CONTINUE
/* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
230 static int intel_lr_context_pin(struct intel_context
*ctx
,
231 struct intel_engine_cs
*engine
);
232 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*engine
,
233 struct drm_i915_gem_object
*default_ctx_obj
);
237 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
239 * @enable_execlists: value of i915.enable_execlists module parameter.
241 * Only certain platforms support Execlists (the prerequisites being
242 * support for Logical Ring Contexts and Aliasing PPGTT or better).
244 * Return: 1 if Execlists is supported and has to be enabled.
246 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
248 WARN_ON(i915
.enable_ppgtt
== -1);
250 /* On platforms with execlist available, vGPU will only
251 * support execlist mode, no ring buffer mode.
253 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
256 if (INTEL_INFO(dev
)->gen
>= 9)
259 if (enable_execlists
== 0)
262 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
263 i915
.use_mmio_flip
>= 0)
270 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
272 struct drm_device
*dev
= engine
->dev
;
274 if (IS_GEN8(dev
) || IS_GEN9(dev
))
275 engine
->idle_lite_restore_wa
= ~0;
277 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
278 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) &&
279 (engine
->id
== VCS
|| engine
->id
== VCS2
);
281 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
282 engine
->ctx_desc_template
|= GEN8_CTX_ADDRESSING_MODE(dev
) <<
283 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
285 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
286 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
288 /* TODO: WaDisableLiteRestore when we start using semaphore
289 * signalling between Command Streamers */
290 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
292 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
293 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
294 if (engine
->disable_lite_restore_wa
)
295 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
299 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
300 * descriptor for a pinned context
302 * @ctx: Context to work on
303 * @ring: Engine the descriptor will be used with
305 * The context descriptor encodes various attributes of a context,
306 * including its GTT address and some flags. Because it's fairly
307 * expensive to calculate, we'll just do it once and cache the result,
308 * which remains valid until the context is unpinned.
310 * This is what a descriptor looks like, from LSB to MSB:
311 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
312 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
313 * bits 32-51: ctx ID, a globally unique tag (the LRCA again!)
314 * bits 52-63: reserved, may encode the engine ID (for GuC)
317 intel_lr_context_descriptor_update(struct intel_context
*ctx
,
318 struct intel_engine_cs
*engine
)
322 lrca
= ctx
->engine
[engine
->id
].lrc_vma
->node
.start
+
323 LRC_PPHWSP_PN
* PAGE_SIZE
;
325 desc
= engine
->ctx_desc_template
; /* bits 0-11 */
326 desc
|= lrca
; /* bits 12-31 */
327 desc
|= (lrca
>> PAGE_SHIFT
) << GEN8_CTX_ID_SHIFT
; /* bits 32-51 */
329 ctx
->engine
[engine
->id
].lrc_desc
= desc
;
332 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
333 struct intel_engine_cs
*engine
)
335 return ctx
->engine
[engine
->id
].lrc_desc
;
339 * intel_execlists_ctx_id() - get the Execlists Context ID
340 * @ctx: Context to get the ID for
341 * @ring: Engine to get the ID for
343 * Do not confuse with ctx->id! Unfortunately we have a name overload
344 * here: the old context ID we pass to userspace as a handler so that
345 * they can refer to a context, and the new context ID we pass to the
346 * ELSP so that the GPU can inform us of the context status via
349 * The context ID is a portion of the context descriptor, so we can
350 * just extract the required part from the cached descriptor.
352 * Return: 20-bits globally unique context ID.
354 u32
intel_execlists_ctx_id(struct intel_context
*ctx
,
355 struct intel_engine_cs
*engine
)
357 return intel_lr_context_descriptor(ctx
, engine
) >> GEN8_CTX_ID_SHIFT
;
360 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
361 struct drm_i915_gem_request
*rq1
)
364 struct intel_engine_cs
*engine
= rq0
->engine
;
365 struct drm_device
*dev
= engine
->dev
;
366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
370 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
371 rq1
->elsp_submitted
++;
376 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
377 rq0
->elsp_submitted
++;
379 /* You must always write both descriptors in the order below. */
380 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
381 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
383 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
384 /* The context is automatically loaded after the following */
385 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
387 /* ELSP is a wo register, use another nearby reg for posting */
388 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
392 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
394 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
395 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
396 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
397 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
400 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
402 struct intel_engine_cs
*engine
= rq
->engine
;
403 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
404 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
406 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
408 /* True 32b PPGTT with dynamic page allocation: update PDP
409 * registers and point the unallocated PDPs to scratch page.
410 * PML4 is allocated during ppgtt init, so this is not needed
413 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
414 execlists_update_context_pdps(ppgtt
, reg_state
);
417 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
418 struct drm_i915_gem_request
*rq1
)
420 struct drm_i915_private
*dev_priv
= rq0
->i915
;
422 execlists_update_context(rq0
);
425 execlists_update_context(rq1
);
427 spin_lock_irq(&dev_priv
->uncore
.lock
);
428 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
430 execlists_elsp_write(rq0
, rq1
);
432 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
433 spin_unlock_irq(&dev_priv
->uncore
.lock
);
436 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
438 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
439 struct drm_i915_gem_request
*cursor
, *tmp
;
441 assert_spin_locked(&engine
->execlist_lock
);
444 * If irqs are not active generate a warning as batches that finish
445 * without the irqs may get lost and a GPU Hang may occur.
447 WARN_ON(!intel_irqs_enabled(engine
->dev
->dev_private
));
449 /* Try to read in pairs */
450 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
454 } else if (req0
->ctx
== cursor
->ctx
) {
455 /* Same ctx: ignore first request, as second request
456 * will update tail past first request's workload */
457 cursor
->elsp_submitted
= req0
->elsp_submitted
;
458 list_move_tail(&req0
->execlist_link
,
459 &engine
->execlist_retired_req_list
);
463 WARN_ON(req1
->elsp_submitted
);
471 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
473 * WaIdleLiteRestore: make sure we never cause a lite restore
476 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
477 * resubmit the request. See gen8_emit_request() for where we
478 * prepare the padding after the end of the request.
480 struct intel_ringbuffer
*ringbuf
;
482 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
484 req0
->tail
&= ringbuf
->size
- 1;
487 execlists_submit_requests(req0
, req1
);
491 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 request_id
)
493 struct drm_i915_gem_request
*head_req
;
495 assert_spin_locked(&engine
->execlist_lock
);
497 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
498 struct drm_i915_gem_request
,
504 if (unlikely(intel_execlists_ctx_id(head_req
->ctx
, engine
) != request_id
))
507 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
509 if (--head_req
->elsp_submitted
> 0)
512 list_move_tail(&head_req
->execlist_link
,
513 &engine
->execlist_retired_req_list
);
519 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
522 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
525 read_pointer
%= GEN8_CSB_ENTRIES
;
527 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
529 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
532 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
539 * intel_lrc_irq_handler() - handle Context Switch interrupts
540 * @engine: Engine Command Streamer to handle.
542 * Check the unread Context Status Buffers and manage the submission of new
543 * contexts to the ELSP accordingly.
545 static void intel_lrc_irq_handler(unsigned long data
)
547 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
548 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
550 unsigned int read_pointer
, write_pointer
;
551 u32 csb
[GEN8_CSB_ENTRIES
][2];
552 unsigned int csb_read
= 0, i
;
553 unsigned int submit_contexts
= 0;
555 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
557 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
559 read_pointer
= engine
->next_context_status_buffer
;
560 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
561 if (read_pointer
> write_pointer
)
562 write_pointer
+= GEN8_CSB_ENTRIES
;
564 while (read_pointer
< write_pointer
) {
565 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
567 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
572 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
574 /* Update the read pointer to the old write pointer. Manual ringbuffer
575 * management ftw </sarcasm> */
576 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
577 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
578 engine
->next_context_status_buffer
<< 8));
580 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
582 spin_lock(&engine
->execlist_lock
);
584 for (i
= 0; i
< csb_read
; i
++) {
585 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
586 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
587 if (execlists_check_remove_request(engine
, csb
[i
][1]))
588 WARN(1, "Lite Restored request removed from queue\n");
590 WARN(1, "Preemption without Lite Restore\n");
593 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
594 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
596 execlists_check_remove_request(engine
, csb
[i
][1]);
599 if (submit_contexts
) {
600 if (!engine
->disable_lite_restore_wa
||
601 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
602 execlists_context_unqueue(engine
);
605 spin_unlock(&engine
->execlist_lock
);
607 if (unlikely(submit_contexts
> 2))
608 DRM_ERROR("More than two context complete events?\n");
611 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
613 struct intel_engine_cs
*engine
= request
->engine
;
614 struct drm_i915_gem_request
*cursor
;
615 int num_elements
= 0;
617 if (request
->ctx
!= request
->i915
->kernel_context
)
618 intel_lr_context_pin(request
->ctx
, engine
);
620 i915_gem_request_reference(request
);
622 spin_lock_bh(&engine
->execlist_lock
);
624 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
625 if (++num_elements
> 2)
628 if (num_elements
> 2) {
629 struct drm_i915_gem_request
*tail_req
;
631 tail_req
= list_last_entry(&engine
->execlist_queue
,
632 struct drm_i915_gem_request
,
635 if (request
->ctx
== tail_req
->ctx
) {
636 WARN(tail_req
->elsp_submitted
!= 0,
637 "More than 2 already-submitted reqs queued\n");
638 list_move_tail(&tail_req
->execlist_link
,
639 &engine
->execlist_retired_req_list
);
643 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
644 if (num_elements
== 0)
645 execlists_context_unqueue(engine
);
647 spin_unlock_bh(&engine
->execlist_lock
);
650 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
652 struct intel_engine_cs
*engine
= req
->engine
;
653 uint32_t flush_domains
;
657 if (engine
->gpu_caches_dirty
)
658 flush_domains
= I915_GEM_GPU_DOMAINS
;
660 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
664 engine
->gpu_caches_dirty
= false;
668 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
669 struct list_head
*vmas
)
671 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
672 struct i915_vma
*vma
;
673 uint32_t flush_domains
= 0;
674 bool flush_chipset
= false;
677 list_for_each_entry(vma
, vmas
, exec_list
) {
678 struct drm_i915_gem_object
*obj
= vma
->obj
;
680 if (obj
->active
& other_rings
) {
681 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
686 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
687 flush_chipset
|= i915_gem_clflush_object(obj
, false);
689 flush_domains
|= obj
->base
.write_domain
;
692 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
695 /* Unconditionally invalidate gpu caches and ensure that we do flush
696 * any residual writes from the previous batch.
698 return logical_ring_invalidate_all_caches(req
);
701 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
705 request
->ringbuf
= request
->ctx
->engine
[request
->engine
->id
].ringbuf
;
707 if (i915
.enable_guc_submission
) {
709 * Check that the GuC has space for the request before
710 * going any further, as the i915_add_request() call
711 * later on mustn't fail ...
713 struct intel_guc
*guc
= &request
->i915
->guc
;
715 ret
= i915_guc_wq_check_space(guc
->execbuf_client
);
720 if (request
->ctx
!= request
->i915
->kernel_context
)
721 ret
= intel_lr_context_pin(request
->ctx
, request
->engine
);
726 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
729 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
730 struct intel_engine_cs
*engine
= req
->engine
;
731 struct drm_i915_gem_request
*target
;
735 if (intel_ring_space(ringbuf
) >= bytes
)
738 /* The whole point of reserving space is to not wait! */
739 WARN_ON(ringbuf
->reserved_in_use
);
741 list_for_each_entry(target
, &engine
->request_list
, list
) {
743 * The request queue is per-engine, so can contain requests
744 * from multiple ringbuffers. Here, we must ignore any that
745 * aren't from the ringbuffer we're considering.
747 if (target
->ringbuf
!= ringbuf
)
750 /* Would completion of this request free enough space? */
751 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
757 if (WARN_ON(&target
->list
== &engine
->request_list
))
760 ret
= i915_wait_request(target
);
764 ringbuf
->space
= space
;
769 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
770 * @request: Request to advance the logical ringbuffer of.
772 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
773 * really happens during submission is that the context and current tail will be placed
774 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
775 * point, the tail *inside* the context is updated and the ELSP written to.
778 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
780 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
781 struct drm_i915_private
*dev_priv
= request
->i915
;
782 struct intel_engine_cs
*engine
= request
->engine
;
784 intel_logical_ring_advance(ringbuf
);
785 request
->tail
= ringbuf
->tail
;
788 * Here we add two extra NOOPs as padding to avoid
789 * lite restore of a context with HEAD==TAIL.
791 * Caller must reserve WA_TAIL_DWORDS for us!
793 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
794 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
795 intel_logical_ring_advance(ringbuf
);
797 if (intel_engine_stopped(engine
))
800 if (engine
->last_context
!= request
->ctx
) {
801 if (engine
->last_context
)
802 intel_lr_context_unpin(engine
->last_context
, engine
);
803 if (request
->ctx
!= request
->i915
->kernel_context
) {
804 intel_lr_context_pin(request
->ctx
, engine
);
805 engine
->last_context
= request
->ctx
;
807 engine
->last_context
= NULL
;
811 if (dev_priv
->guc
.execbuf_client
)
812 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
814 execlists_context_queue(request
);
819 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
821 uint32_t __iomem
*virt
;
822 int rem
= ringbuf
->size
- ringbuf
->tail
;
824 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
827 iowrite32(MI_NOOP
, virt
++);
830 intel_ring_update_space(ringbuf
);
833 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
835 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
836 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
837 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
838 int ret
, total_bytes
, wait_bytes
= 0;
839 bool need_wrap
= false;
841 if (ringbuf
->reserved_in_use
)
844 total_bytes
= bytes
+ ringbuf
->reserved_size
;
846 if (unlikely(bytes
> remain_usable
)) {
848 * Not enough space for the basic request. So need to flush
849 * out the remainder and then wait for base + reserved.
851 wait_bytes
= remain_actual
+ total_bytes
;
854 if (unlikely(total_bytes
> remain_usable
)) {
856 * The base request will fit but the reserved space
857 * falls off the end. So don't need an immediate wrap
858 * and only need to effectively wait for the reserved
859 * size space from the start of ringbuffer.
861 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
862 } else if (total_bytes
> ringbuf
->space
) {
863 /* No wrapping required, just waiting. */
864 wait_bytes
= total_bytes
;
869 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
874 __wrap_ring_buffer(ringbuf
);
881 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
883 * @req: The request to start some new work for
884 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
886 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
887 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
888 * and also preallocates a request (every workload submission is still mediated through
889 * requests, same as it did with legacy ringbuffer submission).
891 * Return: non-zero if the ringbuffer is not ready to be written to.
893 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
895 struct drm_i915_private
*dev_priv
;
898 WARN_ON(req
== NULL
);
899 dev_priv
= req
->i915
;
901 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
902 dev_priv
->mm
.interruptible
);
906 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
910 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
914 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
917 * The first call merely notes the reserve request and is common for
918 * all back ends. The subsequent localised _begin() call actually
919 * ensures that the reservation is available. Without the begin, if
920 * the request creator immediately submitted the request without
921 * adding any commands to it then there might not actually be
922 * sufficient room for the submission commands.
924 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
926 return intel_logical_ring_begin(request
, 0);
930 * execlists_submission() - submit a batchbuffer for execution, Execlists style
933 * @ring: Engine Command Streamer to submit to.
934 * @ctx: Context to employ for this submission.
935 * @args: execbuffer call arguments.
936 * @vmas: list of vmas.
937 * @batch_obj: the batchbuffer to submit.
938 * @exec_start: batchbuffer start virtual address pointer.
939 * @dispatch_flags: translated execbuffer call flags.
941 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
942 * away the submission details of the execbuffer ioctl call.
944 * Return: non-zero if the submission fails.
946 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
947 struct drm_i915_gem_execbuffer2
*args
,
948 struct list_head
*vmas
)
950 struct drm_device
*dev
= params
->dev
;
951 struct intel_engine_cs
*engine
= params
->engine
;
952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
953 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
959 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
960 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
961 switch (instp_mode
) {
962 case I915_EXEC_CONSTANTS_REL_GENERAL
:
963 case I915_EXEC_CONSTANTS_ABSOLUTE
:
964 case I915_EXEC_CONSTANTS_REL_SURFACE
:
965 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
966 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
970 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
971 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
972 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
976 /* The HW changed the meaning on this bit on gen6 */
977 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
981 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
985 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
986 DRM_DEBUG("sol reset is gen7 only\n");
990 ret
= execlists_move_to_gpu(params
->request
, vmas
);
994 if (engine
== &dev_priv
->engine
[RCS
] &&
995 instp_mode
!= dev_priv
->relative_constants_mode
) {
996 ret
= intel_logical_ring_begin(params
->request
, 4);
1000 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1001 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
1002 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
1003 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
1004 intel_logical_ring_advance(ringbuf
);
1006 dev_priv
->relative_constants_mode
= instp_mode
;
1009 exec_start
= params
->batch_obj_vm_offset
+
1010 args
->batch_start_offset
;
1012 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
1016 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
1018 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
1019 i915_gem_execbuffer_retire_commands(params
);
1024 void intel_execlists_retire_requests(struct intel_engine_cs
*engine
)
1026 struct drm_i915_gem_request
*req
, *tmp
;
1027 struct list_head retired_list
;
1029 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
1030 if (list_empty(&engine
->execlist_retired_req_list
))
1033 INIT_LIST_HEAD(&retired_list
);
1034 spin_lock_bh(&engine
->execlist_lock
);
1035 list_replace_init(&engine
->execlist_retired_req_list
, &retired_list
);
1036 spin_unlock_bh(&engine
->execlist_lock
);
1038 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
1039 struct intel_context
*ctx
= req
->ctx
;
1040 struct drm_i915_gem_object
*ctx_obj
=
1041 ctx
->engine
[engine
->id
].state
;
1043 if (ctx_obj
&& (ctx
!= req
->i915
->kernel_context
))
1044 intel_lr_context_unpin(ctx
, engine
);
1046 list_del(&req
->execlist_link
);
1047 i915_gem_request_unreference(req
);
1051 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
1053 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
1056 if (!intel_engine_initialized(engine
))
1059 ret
= intel_engine_idle(engine
);
1060 if (ret
&& !i915_reset_in_progress(&to_i915(engine
->dev
)->gpu_error
))
1061 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1064 /* TODO: Is this correct with Execlists enabled? */
1065 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
1066 if (wait_for((I915_READ_MODE(engine
) & MODE_IDLE
) != 0, 1000)) {
1067 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
1070 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
1073 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
1075 struct intel_engine_cs
*engine
= req
->engine
;
1078 if (!engine
->gpu_caches_dirty
)
1081 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
1085 engine
->gpu_caches_dirty
= false;
1089 static int intel_lr_context_do_pin(struct intel_context
*ctx
,
1090 struct intel_engine_cs
*engine
)
1092 struct drm_device
*dev
= engine
->dev
;
1093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1094 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
1095 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[engine
->id
].ringbuf
;
1096 struct page
*lrc_state_page
;
1097 uint32_t *lrc_reg_state
;
1100 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
1102 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
1103 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
1107 lrc_state_page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
1108 if (WARN_ON(!lrc_state_page
)) {
1113 ret
= intel_pin_and_map_ringbuffer_obj(engine
->dev
, ringbuf
);
1117 ctx
->engine
[engine
->id
].lrc_vma
= i915_gem_obj_to_ggtt(ctx_obj
);
1118 intel_lr_context_descriptor_update(ctx
, engine
);
1119 lrc_reg_state
= kmap(lrc_state_page
);
1120 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ringbuf
->vma
->node
.start
;
1121 ctx
->engine
[engine
->id
].lrc_reg_state
= lrc_reg_state
;
1122 ctx_obj
->dirty
= true;
1124 /* Invalidate GuC TLB. */
1125 if (i915
.enable_guc_submission
)
1126 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1131 i915_gem_object_ggtt_unpin(ctx_obj
);
1136 static int intel_lr_context_pin(struct intel_context
*ctx
,
1137 struct intel_engine_cs
*engine
)
1141 if (ctx
->engine
[engine
->id
].pin_count
++ == 0) {
1142 ret
= intel_lr_context_do_pin(ctx
, engine
);
1144 goto reset_pin_count
;
1146 i915_gem_context_reference(ctx
);
1151 ctx
->engine
[engine
->id
].pin_count
= 0;
1155 void intel_lr_context_unpin(struct intel_context
*ctx
,
1156 struct intel_engine_cs
*engine
)
1158 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
1160 WARN_ON(!mutex_is_locked(&ctx
->i915
->dev
->struct_mutex
));
1161 if (--ctx
->engine
[engine
->id
].pin_count
== 0) {
1162 kunmap(kmap_to_page(ctx
->engine
[engine
->id
].lrc_reg_state
));
1163 intel_unpin_ringbuffer_obj(ctx
->engine
[engine
->id
].ringbuf
);
1164 i915_gem_object_ggtt_unpin(ctx_obj
);
1165 ctx
->engine
[engine
->id
].lrc_vma
= NULL
;
1166 ctx
->engine
[engine
->id
].lrc_desc
= 0;
1167 ctx
->engine
[engine
->id
].lrc_reg_state
= NULL
;
1169 i915_gem_context_unreference(ctx
);
1173 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1176 struct intel_engine_cs
*engine
= req
->engine
;
1177 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1178 struct drm_device
*dev
= engine
->dev
;
1179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1185 engine
->gpu_caches_dirty
= true;
1186 ret
= logical_ring_flush_all_caches(req
);
1190 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1194 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1195 for (i
= 0; i
< w
->count
; i
++) {
1196 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1197 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1199 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1201 intel_logical_ring_advance(ringbuf
);
1203 engine
->gpu_caches_dirty
= true;
1204 ret
= logical_ring_flush_all_caches(req
);
1211 #define wa_ctx_emit(batch, index, cmd) \
1213 int __index = (index)++; \
1214 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1217 batch[__index] = (cmd); \
1220 #define wa_ctx_emit_reg(batch, index, reg) \
1221 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1224 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1225 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1226 * but there is a slight complication as this is applied in WA batch where the
1227 * values are only initialized once so we cannot take register value at the
1228 * beginning and reuse it further; hence we save its value to memory, upload a
1229 * constant value with bit21 set and then we restore it back with the saved value.
1230 * To simplify the WA, a constant value is formed by using the default value
1231 * of this register. This shouldn't be a problem because we are only modifying
1232 * it for a short period and this batch in non-premptible. We can ofcourse
1233 * use additional instructions that read the actual value of the register
1234 * at that time and set our bit of interest but it makes the WA complicated.
1236 * This WA is also required for Gen9 so extracting as a function avoids
1239 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1240 uint32_t *const batch
,
1243 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1246 * WaDisableLSQCROPERFforOCL:skl
1247 * This WA is implemented in skl_init_clock_gating() but since
1248 * this batch updates GEN8_L3SQCREG4 with default value we need to
1249 * set this bit here to retain the WA during flush.
1251 if (IS_SKL_REVID(engine
->dev
, 0, SKL_REVID_E0
))
1252 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1254 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1255 MI_SRM_LRM_GLOBAL_GTT
));
1256 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1257 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1258 wa_ctx_emit(batch
, index
, 0);
1260 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1261 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1262 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1264 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1265 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1266 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1267 wa_ctx_emit(batch
, index
, 0);
1268 wa_ctx_emit(batch
, index
, 0);
1269 wa_ctx_emit(batch
, index
, 0);
1270 wa_ctx_emit(batch
, index
, 0);
1272 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1273 MI_SRM_LRM_GLOBAL_GTT
));
1274 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1275 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1276 wa_ctx_emit(batch
, index
, 0);
1281 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1283 uint32_t start_alignment
)
1285 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1288 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1290 uint32_t size_alignment
)
1292 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1294 WARN(wa_ctx
->size
% size_alignment
,
1295 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1296 wa_ctx
->size
, size_alignment
);
1301 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1303 * @ring: only applicable for RCS
1304 * @wa_ctx: structure representing wa_ctx
1305 * offset: specifies start of the batch, should be cache-aligned. This is updated
1306 * with the offset value received as input.
1307 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1308 * @batch: page in which WA are loaded
1309 * @offset: This field specifies the start of the batch, it should be
1310 * cache-aligned otherwise it is adjusted accordingly.
1311 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1312 * initialized at the beginning and shared across all contexts but this field
1313 * helps us to have multiple batches at different offsets and select them based
1314 * on a criteria. At the moment this batch always start at the beginning of the page
1315 * and at this point we don't have multiple wa_ctx batch buffers.
1317 * The number of WA applied are not known at the beginning; we use this field
1318 * to return the no of DWORDS written.
1320 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1321 * so it adds NOOPs as padding to make it cacheline aligned.
1322 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1323 * makes a complete batch buffer.
1325 * Return: non-zero if we exceed the PAGE_SIZE limit.
1328 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1329 struct i915_wa_ctx_bb
*wa_ctx
,
1330 uint32_t *const batch
,
1333 uint32_t scratch_addr
;
1334 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1336 /* WaDisableCtxRestoreArbitration:bdw,chv */
1337 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1339 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1340 if (IS_BROADWELL(engine
->dev
)) {
1341 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1347 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1348 /* Actual scratch location is at 128 bytes offset */
1349 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1351 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1352 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1353 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1354 PIPE_CONTROL_CS_STALL
|
1355 PIPE_CONTROL_QW_WRITE
));
1356 wa_ctx_emit(batch
, index
, scratch_addr
);
1357 wa_ctx_emit(batch
, index
, 0);
1358 wa_ctx_emit(batch
, index
, 0);
1359 wa_ctx_emit(batch
, index
, 0);
1361 /* Pad to end of cacheline */
1362 while (index
% CACHELINE_DWORDS
)
1363 wa_ctx_emit(batch
, index
, MI_NOOP
);
1366 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1367 * execution depends on the length specified in terms of cache lines
1368 * in the register CTX_RCS_INDIRECT_CTX
1371 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1375 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1377 * @ring: only applicable for RCS
1378 * @wa_ctx: structure representing wa_ctx
1379 * offset: specifies start of the batch, should be cache-aligned.
1380 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1381 * @batch: page in which WA are loaded
1382 * @offset: This field specifies the start of this batch.
1383 * This batch is started immediately after indirect_ctx batch. Since we ensure
1384 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1386 * The number of DWORDS written are returned using this field.
1388 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1389 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1391 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1392 struct i915_wa_ctx_bb
*wa_ctx
,
1393 uint32_t *const batch
,
1396 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1398 /* WaDisableCtxRestoreArbitration:bdw,chv */
1399 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1401 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1403 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1406 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1407 struct i915_wa_ctx_bb
*wa_ctx
,
1408 uint32_t *const batch
,
1412 struct drm_device
*dev
= engine
->dev
;
1413 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1415 /* WaDisableCtxRestoreArbitration:skl,bxt */
1416 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1417 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1418 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1420 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1421 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1426 /* Pad to end of cacheline */
1427 while (index
% CACHELINE_DWORDS
)
1428 wa_ctx_emit(batch
, index
, MI_NOOP
);
1430 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1433 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1434 struct i915_wa_ctx_bb
*wa_ctx
,
1435 uint32_t *const batch
,
1438 struct drm_device
*dev
= engine
->dev
;
1439 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1441 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1442 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
1443 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1444 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1445 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1446 wa_ctx_emit(batch
, index
,
1447 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1448 wa_ctx_emit(batch
, index
, MI_NOOP
);
1451 /* WaClearTdlStateAckDirtyBits:bxt */
1452 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1453 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1455 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1456 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1458 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1459 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1461 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1462 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1464 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1465 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1466 wa_ctx_emit(batch
, index
, 0x0);
1467 wa_ctx_emit(batch
, index
, MI_NOOP
);
1470 /* WaDisableCtxRestoreArbitration:skl,bxt */
1471 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1472 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1473 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1475 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1477 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1480 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1484 engine
->wa_ctx
.obj
= i915_gem_alloc_object(engine
->dev
,
1486 if (!engine
->wa_ctx
.obj
) {
1487 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1491 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1493 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1495 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1502 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1504 if (engine
->wa_ctx
.obj
) {
1505 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1506 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1507 engine
->wa_ctx
.obj
= NULL
;
1511 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1517 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1519 WARN_ON(engine
->id
!= RCS
);
1521 /* update this when WA for higher Gen are added */
1522 if (INTEL_INFO(engine
->dev
)->gen
> 9) {
1523 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1524 INTEL_INFO(engine
->dev
)->gen
);
1528 /* some WA perform writes to scratch page, ensure it is valid */
1529 if (engine
->scratch
.obj
== NULL
) {
1530 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1534 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1536 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1540 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1541 batch
= kmap_atomic(page
);
1544 if (INTEL_INFO(engine
->dev
)->gen
== 8) {
1545 ret
= gen8_init_indirectctx_bb(engine
,
1546 &wa_ctx
->indirect_ctx
,
1552 ret
= gen8_init_perctx_bb(engine
,
1558 } else if (INTEL_INFO(engine
->dev
)->gen
== 9) {
1559 ret
= gen9_init_indirectctx_bb(engine
,
1560 &wa_ctx
->indirect_ctx
,
1566 ret
= gen9_init_perctx_bb(engine
,
1575 kunmap_atomic(batch
);
1577 lrc_destroy_wa_ctx_obj(engine
);
1582 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1584 struct drm_device
*dev
= engine
->dev
;
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1586 unsigned int next_context_status_buffer_hw
;
1588 lrc_setup_hardware_status_page(engine
,
1589 dev_priv
->kernel_context
->engine
[engine
->id
].state
);
1591 I915_WRITE_IMR(engine
,
1592 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1593 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1595 I915_WRITE(RING_MODE_GEN7(engine
),
1596 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1597 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1598 POSTING_READ(RING_MODE_GEN7(engine
));
1601 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1602 * zero, we need to read the write pointer from hardware and use its
1603 * value because "this register is power context save restored".
1604 * Effectively, these states have been observed:
1606 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1607 * BDW | CSB regs not reset | CSB regs reset |
1608 * CHT | CSB regs not reset | CSB regs not reset |
1612 next_context_status_buffer_hw
=
1613 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1616 * When the CSB registers are reset (also after power-up / gpu reset),
1617 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1618 * this special case, so the first element read is CSB[0].
1620 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1621 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1623 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1624 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1626 intel_engine_init_hangcheck(engine
);
1631 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1633 struct drm_device
*dev
= engine
->dev
;
1634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1637 ret
= gen8_init_common_ring(engine
);
1641 /* We need to disable the AsyncFlip performance optimisations in order
1642 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1643 * programmed to '1' on all products.
1645 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1647 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1649 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1651 return init_workarounds_ring(engine
);
1654 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1658 ret
= gen8_init_common_ring(engine
);
1662 return init_workarounds_ring(engine
);
1665 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1667 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1668 struct intel_engine_cs
*engine
= req
->engine
;
1669 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1670 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1673 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1677 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1678 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1679 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1681 intel_logical_ring_emit_reg(ringbuf
,
1682 GEN8_RING_PDP_UDW(engine
, i
));
1683 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1684 intel_logical_ring_emit_reg(ringbuf
,
1685 GEN8_RING_PDP_LDW(engine
, i
));
1686 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1689 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1690 intel_logical_ring_advance(ringbuf
);
1695 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1696 u64 offset
, unsigned dispatch_flags
)
1698 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1699 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1702 /* Don't rely in hw updating PDPs, specially in lite-restore.
1703 * Ideally, we should set Force PD Restore in ctx descriptor,
1704 * but we can't. Force Restore would be a second option, but
1705 * it is unsafe in case of lite-restore (because the ctx is
1706 * not idle). PML4 is allocated during ppgtt init so this is
1707 * not needed in 48-bit.*/
1708 if (req
->ctx
->ppgtt
&&
1709 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1710 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1711 !intel_vgpu_active(req
->i915
->dev
)) {
1712 ret
= intel_logical_ring_emit_pdps(req
);
1717 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1720 ret
= intel_logical_ring_begin(req
, 4);
1724 /* FIXME(BDW): Address space and security selectors. */
1725 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1727 (dispatch_flags
& I915_DISPATCH_RS
?
1728 MI_BATCH_RESOURCE_STREAMER
: 0));
1729 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1730 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1731 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1732 intel_logical_ring_advance(ringbuf
);
1737 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*engine
)
1739 struct drm_device
*dev
= engine
->dev
;
1740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1741 unsigned long flags
;
1743 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1746 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1747 if (engine
->irq_refcount
++ == 0) {
1748 I915_WRITE_IMR(engine
,
1749 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1750 POSTING_READ(RING_IMR(engine
->mmio_base
));
1752 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1757 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*engine
)
1759 struct drm_device
*dev
= engine
->dev
;
1760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1761 unsigned long flags
;
1763 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1764 if (--engine
->irq_refcount
== 0) {
1765 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1766 POSTING_READ(RING_IMR(engine
->mmio_base
));
1768 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1771 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1772 u32 invalidate_domains
,
1775 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1776 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1777 struct drm_device
*dev
= engine
->dev
;
1778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1782 ret
= intel_logical_ring_begin(request
, 4);
1786 cmd
= MI_FLUSH_DW
+ 1;
1788 /* We always require a command barrier so that subsequent
1789 * commands, such as breadcrumb interrupts, are strictly ordered
1790 * wrt the contents of the write cache being flushed to memory
1791 * (and thus being coherent from the CPU).
1793 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1795 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1796 cmd
|= MI_INVALIDATE_TLB
;
1797 if (engine
== &dev_priv
->engine
[VCS
])
1798 cmd
|= MI_INVALIDATE_BSD
;
1801 intel_logical_ring_emit(ringbuf
, cmd
);
1802 intel_logical_ring_emit(ringbuf
,
1803 I915_GEM_HWS_SCRATCH_ADDR
|
1804 MI_FLUSH_DW_USE_GTT
);
1805 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1806 intel_logical_ring_emit(ringbuf
, 0); /* value */
1807 intel_logical_ring_advance(ringbuf
);
1812 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1813 u32 invalidate_domains
,
1816 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1817 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1818 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1819 bool vf_flush_wa
= false;
1823 flags
|= PIPE_CONTROL_CS_STALL
;
1825 if (flush_domains
) {
1826 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1827 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1828 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1829 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1832 if (invalidate_domains
) {
1833 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1834 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1835 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1836 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1837 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1838 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1839 flags
|= PIPE_CONTROL_QW_WRITE
;
1840 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1843 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1846 if (IS_GEN9(engine
->dev
))
1850 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1855 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1856 intel_logical_ring_emit(ringbuf
, 0);
1857 intel_logical_ring_emit(ringbuf
, 0);
1858 intel_logical_ring_emit(ringbuf
, 0);
1859 intel_logical_ring_emit(ringbuf
, 0);
1860 intel_logical_ring_emit(ringbuf
, 0);
1863 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1864 intel_logical_ring_emit(ringbuf
, flags
);
1865 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1866 intel_logical_ring_emit(ringbuf
, 0);
1867 intel_logical_ring_emit(ringbuf
, 0);
1868 intel_logical_ring_emit(ringbuf
, 0);
1869 intel_logical_ring_advance(ringbuf
);
1874 static u32
gen8_get_seqno(struct intel_engine_cs
*engine
)
1876 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1879 static void gen8_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1881 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1884 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1887 * On BXT A steppings there is a HW coherency issue whereby the
1888 * MI_STORE_DATA_IMM storing the completed request's seqno
1889 * occasionally doesn't invalidate the CPU cache. Work around this by
1890 * clflushing the corresponding cacheline whenever the caller wants
1891 * the coherency to be guaranteed. Note that this cacheline is known
1892 * to be clean at this point, since we only write it in
1893 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1894 * this clflush in practice becomes an invalidate operation.
1896 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1899 static void bxt_a_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1901 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1903 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1904 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1908 * Reserve space for 2 NOOPs at the end of each request to be
1909 * used as a workaround for not being allowed to do lite
1910 * restore with HEAD==TAIL (WaIdleLiteRestore).
1912 #define WA_TAIL_DWORDS 2
1914 static inline u32
hws_seqno_address(struct intel_engine_cs
*engine
)
1916 return engine
->status_page
.gfx_addr
+ I915_GEM_HWS_INDEX_ADDR
;
1919 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1921 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1924 ret
= intel_logical_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1928 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1929 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1931 intel_logical_ring_emit(ringbuf
,
1932 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1933 intel_logical_ring_emit(ringbuf
,
1934 hws_seqno_address(request
->engine
) |
1935 MI_FLUSH_DW_USE_GTT
);
1936 intel_logical_ring_emit(ringbuf
, 0);
1937 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1938 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1939 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1940 return intel_logical_ring_advance_and_submit(request
);
1943 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1945 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1948 ret
= intel_logical_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1952 /* w/a for post sync ops following a GPGPU operation we
1953 * need a prior CS_STALL, which is emitted by the flush
1954 * following the batch.
1956 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(5));
1957 intel_logical_ring_emit(ringbuf
,
1958 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1959 PIPE_CONTROL_CS_STALL
|
1960 PIPE_CONTROL_QW_WRITE
));
1961 intel_logical_ring_emit(ringbuf
, hws_seqno_address(request
->engine
));
1962 intel_logical_ring_emit(ringbuf
, 0);
1963 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1964 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1965 return intel_logical_ring_advance_and_submit(request
);
1968 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1970 struct render_state so
;
1973 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1977 if (so
.rodata
== NULL
)
1980 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1981 I915_DISPATCH_SECURE
);
1985 ret
= req
->engine
->emit_bb_start(req
,
1986 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1987 I915_DISPATCH_SECURE
);
1991 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1994 i915_gem_render_state_fini(&so
);
1998 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
2002 ret
= intel_logical_ring_workarounds_emit(req
);
2006 ret
= intel_rcs_context_init_mocs(req
);
2008 * Failing to program the MOCS is non-fatal.The system will not
2009 * run at peak performance. So generate an error and carry on.
2012 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2014 return intel_lr_context_render_state_init(req
);
2018 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2020 * @ring: Engine Command Streamer.
2023 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
2025 struct drm_i915_private
*dev_priv
;
2027 if (!intel_engine_initialized(engine
))
2031 * Tasklet cannot be active at this point due intel_mark_active/idle
2032 * so this is just for documentation.
2034 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
2035 tasklet_kill(&engine
->irq_tasklet
);
2037 dev_priv
= engine
->dev
->dev_private
;
2039 if (engine
->buffer
) {
2040 intel_logical_ring_stop(engine
);
2041 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2044 if (engine
->cleanup
)
2045 engine
->cleanup(engine
);
2047 i915_cmd_parser_fini_ring(engine
);
2048 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2050 if (engine
->status_page
.obj
) {
2051 kunmap(sg_page(engine
->status_page
.obj
->pages
->sgl
));
2052 engine
->status_page
.obj
= NULL
;
2055 engine
->idle_lite_restore_wa
= 0;
2056 engine
->disable_lite_restore_wa
= false;
2057 engine
->ctx_desc_template
= 0;
2059 lrc_destroy_wa_ctx_obj(engine
);
2064 logical_ring_default_vfuncs(struct drm_device
*dev
,
2065 struct intel_engine_cs
*engine
)
2067 /* Default vfuncs which can be overriden by each engine. */
2068 engine
->init_hw
= gen8_init_common_ring
;
2069 engine
->emit_request
= gen8_emit_request
;
2070 engine
->emit_flush
= gen8_emit_flush
;
2071 engine
->irq_get
= gen8_logical_ring_get_irq
;
2072 engine
->irq_put
= gen8_logical_ring_put_irq
;
2073 engine
->emit_bb_start
= gen8_emit_bb_start
;
2074 engine
->get_seqno
= gen8_get_seqno
;
2075 engine
->set_seqno
= gen8_set_seqno
;
2076 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
2077 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
2078 engine
->set_seqno
= bxt_a_set_seqno
;
2083 logical_ring_default_irqs(struct intel_engine_cs
*engine
, unsigned shift
)
2085 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
2086 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
2090 logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*engine
)
2092 struct intel_context
*dctx
= to_i915(dev
)->kernel_context
;
2095 /* Intentionally left blank. */
2096 engine
->buffer
= NULL
;
2099 INIT_LIST_HEAD(&engine
->active_list
);
2100 INIT_LIST_HEAD(&engine
->request_list
);
2101 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2102 init_waitqueue_head(&engine
->irq_queue
);
2104 INIT_LIST_HEAD(&engine
->buffers
);
2105 INIT_LIST_HEAD(&engine
->execlist_queue
);
2106 INIT_LIST_HEAD(&engine
->execlist_retired_req_list
);
2107 spin_lock_init(&engine
->execlist_lock
);
2109 tasklet_init(&engine
->irq_tasklet
,
2110 intel_lrc_irq_handler
, (unsigned long)engine
);
2112 logical_ring_init_platform_invariants(engine
);
2114 ret
= i915_cmd_parser_init_ring(engine
);
2118 ret
= intel_lr_context_deferred_alloc(dctx
, engine
);
2122 /* As this is the default context, always pin it */
2123 ret
= intel_lr_context_do_pin(dctx
, engine
);
2126 "Failed to pin and map ringbuffer %s: %d\n",
2134 intel_logical_ring_cleanup(engine
);
2138 static int logical_render_ring_init(struct drm_device
*dev
)
2140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2141 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2144 engine
->name
= "render ring";
2146 engine
->exec_id
= I915_EXEC_RENDER
;
2147 engine
->guc_id
= GUC_RENDER_ENGINE
;
2148 engine
->mmio_base
= RENDER_RING_BASE
;
2150 logical_ring_default_irqs(engine
, GEN8_RCS_IRQ_SHIFT
);
2151 if (HAS_L3_DPF(dev
))
2152 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2154 logical_ring_default_vfuncs(dev
, engine
);
2156 /* Override some for render ring. */
2157 if (INTEL_INFO(dev
)->gen
>= 9)
2158 engine
->init_hw
= gen9_init_render_ring
;
2160 engine
->init_hw
= gen8_init_render_ring
;
2161 engine
->init_context
= gen8_init_rcs_context
;
2162 engine
->cleanup
= intel_fini_pipe_control
;
2163 engine
->emit_flush
= gen8_emit_flush_render
;
2164 engine
->emit_request
= gen8_emit_request_render
;
2168 ret
= intel_init_pipe_control(engine
);
2172 ret
= intel_init_workaround_bb(engine
);
2175 * We continue even if we fail to initialize WA batch
2176 * because we only expect rare glitches but nothing
2177 * critical to prevent us from using GPU
2179 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2183 ret
= logical_ring_init(dev
, engine
);
2185 lrc_destroy_wa_ctx_obj(engine
);
2191 static int logical_bsd_ring_init(struct drm_device
*dev
)
2193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2194 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2196 engine
->name
= "bsd ring";
2198 engine
->exec_id
= I915_EXEC_BSD
;
2199 engine
->guc_id
= GUC_VIDEO_ENGINE
;
2200 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2202 logical_ring_default_irqs(engine
, GEN8_VCS1_IRQ_SHIFT
);
2203 logical_ring_default_vfuncs(dev
, engine
);
2205 return logical_ring_init(dev
, engine
);
2208 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2211 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
2213 engine
->name
= "bsd2 ring";
2215 engine
->exec_id
= I915_EXEC_BSD
;
2216 engine
->guc_id
= GUC_VIDEO_ENGINE2
;
2217 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
2219 logical_ring_default_irqs(engine
, GEN8_VCS2_IRQ_SHIFT
);
2220 logical_ring_default_vfuncs(dev
, engine
);
2222 return logical_ring_init(dev
, engine
);
2225 static int logical_blt_ring_init(struct drm_device
*dev
)
2227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2228 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
2230 engine
->name
= "blitter ring";
2232 engine
->exec_id
= I915_EXEC_BLT
;
2233 engine
->guc_id
= GUC_BLITTER_ENGINE
;
2234 engine
->mmio_base
= BLT_RING_BASE
;
2236 logical_ring_default_irqs(engine
, GEN8_BCS_IRQ_SHIFT
);
2237 logical_ring_default_vfuncs(dev
, engine
);
2239 return logical_ring_init(dev
, engine
);
2242 static int logical_vebox_ring_init(struct drm_device
*dev
)
2244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2245 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
2247 engine
->name
= "video enhancement ring";
2249 engine
->exec_id
= I915_EXEC_VEBOX
;
2250 engine
->guc_id
= GUC_VIDEOENHANCE_ENGINE
;
2251 engine
->mmio_base
= VEBOX_RING_BASE
;
2253 logical_ring_default_irqs(engine
, GEN8_VECS_IRQ_SHIFT
);
2254 logical_ring_default_vfuncs(dev
, engine
);
2256 return logical_ring_init(dev
, engine
);
2260 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2263 * This function inits the engines for an Execlists submission style (the equivalent in the
2264 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2265 * those engines that are present in the hardware.
2267 * Return: non-zero if the initialization failed.
2269 int intel_logical_rings_init(struct drm_device
*dev
)
2271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2274 ret
= logical_render_ring_init(dev
);
2279 ret
= logical_bsd_ring_init(dev
);
2281 goto cleanup_render_ring
;
2285 ret
= logical_blt_ring_init(dev
);
2287 goto cleanup_bsd_ring
;
2290 if (HAS_VEBOX(dev
)) {
2291 ret
= logical_vebox_ring_init(dev
);
2293 goto cleanup_blt_ring
;
2296 if (HAS_BSD2(dev
)) {
2297 ret
= logical_bsd2_ring_init(dev
);
2299 goto cleanup_vebox_ring
;
2305 intel_logical_ring_cleanup(&dev_priv
->engine
[VECS
]);
2307 intel_logical_ring_cleanup(&dev_priv
->engine
[BCS
]);
2309 intel_logical_ring_cleanup(&dev_priv
->engine
[VCS
]);
2310 cleanup_render_ring
:
2311 intel_logical_ring_cleanup(&dev_priv
->engine
[RCS
]);
2317 make_rpcs(struct drm_device
*dev
)
2322 * No explicit RPCS request is needed to ensure full
2323 * slice/subslice/EU enablement prior to Gen9.
2325 if (INTEL_INFO(dev
)->gen
< 9)
2329 * Starting in Gen9, render power gating can leave
2330 * slice/subslice/EU in a partially enabled state. We
2331 * must make an explicit request through RPCS for full
2334 if (INTEL_INFO(dev
)->has_slice_pg
) {
2335 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2336 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2337 GEN8_RPCS_S_CNT_SHIFT
;
2338 rpcs
|= GEN8_RPCS_ENABLE
;
2341 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2342 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2343 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2344 GEN8_RPCS_SS_CNT_SHIFT
;
2345 rpcs
|= GEN8_RPCS_ENABLE
;
2348 if (INTEL_INFO(dev
)->has_eu_pg
) {
2349 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2350 GEN8_RPCS_EU_MIN_SHIFT
;
2351 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2352 GEN8_RPCS_EU_MAX_SHIFT
;
2353 rpcs
|= GEN8_RPCS_ENABLE
;
2359 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2361 u32 indirect_ctx_offset
;
2363 switch (INTEL_INFO(engine
->dev
)->gen
) {
2365 MISSING_CASE(INTEL_INFO(engine
->dev
)->gen
);
2368 indirect_ctx_offset
=
2369 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2372 indirect_ctx_offset
=
2373 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2377 return indirect_ctx_offset
;
2381 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2382 struct intel_engine_cs
*engine
,
2383 struct intel_ringbuffer
*ringbuf
)
2385 struct drm_device
*dev
= engine
->dev
;
2386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2387 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2389 uint32_t *reg_state
;
2393 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2395 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2397 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2401 ret
= i915_gem_object_get_pages(ctx_obj
);
2403 DRM_DEBUG_DRIVER("Could not get object pages\n");
2407 i915_gem_object_pin_pages(ctx_obj
);
2409 /* The second page of the context object contains some fields which must
2410 * be set up prior to the first execution. */
2411 page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
2412 reg_state
= kmap_atomic(page
);
2414 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2415 * commands followed by (reg, value) pairs. The values we are setting here are
2416 * only for the first context restore: on a subsequent save, the GPU will
2417 * recreate this batchbuffer with new values (including all the missing
2418 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2419 reg_state
[CTX_LRI_HEADER_0
] =
2420 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2421 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2422 RING_CONTEXT_CONTROL(engine
),
2423 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2424 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2425 (HAS_RESOURCE_STREAMER(dev
) ?
2426 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2427 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2429 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2431 /* Ring buffer start address is not known until the buffer is pinned.
2432 * It is written to the context image in execlists_update_context()
2434 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2435 RING_START(engine
->mmio_base
), 0);
2436 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2437 RING_CTL(engine
->mmio_base
),
2438 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2439 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2440 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2441 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2442 RING_BBADDR(engine
->mmio_base
), 0);
2443 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2444 RING_BBSTATE(engine
->mmio_base
),
2446 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2447 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2448 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2449 RING_SBBADDR(engine
->mmio_base
), 0);
2450 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2451 RING_SBBSTATE(engine
->mmio_base
), 0);
2452 if (engine
->id
== RCS
) {
2453 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2454 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2455 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2456 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2457 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2458 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2459 if (engine
->wa_ctx
.obj
) {
2460 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2461 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2463 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2464 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2465 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2467 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2468 intel_lr_indirect_ctx_offset(engine
) << 6;
2470 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2471 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2475 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2476 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2477 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2478 /* PDP values well be assigned later if needed */
2479 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2481 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2483 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2485 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2487 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2489 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2491 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2493 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2496 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2497 /* 64b PPGTT (48bit canonical)
2498 * PDP0_DESCRIPTOR contains the base address to PML4 and
2499 * other PDP Descriptors are ignored.
2501 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2504 * PDP*_DESCRIPTOR contains the base address of space supported.
2505 * With dynamic page allocation, PDPs may not be allocated at
2506 * this point. Point the unallocated PDPs to the scratch page
2508 execlists_update_context_pdps(ppgtt
, reg_state
);
2511 if (engine
->id
== RCS
) {
2512 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2513 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2517 kunmap_atomic(reg_state
);
2518 i915_gem_object_unpin_pages(ctx_obj
);
2524 * intel_lr_context_free() - free the LRC specific bits of a context
2525 * @ctx: the LR context to free.
2527 * The real context freeing is done in i915_gem_context_free: this only
2528 * takes care of the bits that are LRC related: the per-engine backing
2529 * objects and the logical ringbuffer.
2531 void intel_lr_context_free(struct intel_context
*ctx
)
2535 for (i
= I915_NUM_ENGINES
; --i
>= 0; ) {
2536 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
2537 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2542 if (ctx
== ctx
->i915
->kernel_context
) {
2543 intel_unpin_ringbuffer_obj(ringbuf
);
2544 i915_gem_object_ggtt_unpin(ctx_obj
);
2547 WARN_ON(ctx
->engine
[i
].pin_count
);
2548 intel_ringbuffer_free(ringbuf
);
2549 drm_gem_object_unreference(&ctx_obj
->base
);
2554 * intel_lr_context_size() - return the size of the context for an engine
2555 * @ring: which engine to find the context size for
2557 * Each engine may require a different amount of space for a context image,
2558 * so when allocating (or copying) an image, this function can be used to
2559 * find the right size for the specific engine.
2561 * Return: size (in bytes) of an engine-specific context image
2563 * Note: this size includes the HWSP, which is part of the context image
2564 * in LRC mode, but does not include the "shared data page" used with
2565 * GuC submission. The caller should account for this if using the GuC.
2567 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2571 WARN_ON(INTEL_INFO(engine
->dev
)->gen
< 8);
2573 switch (engine
->id
) {
2575 if (INTEL_INFO(engine
->dev
)->gen
>= 9)
2576 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2578 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2584 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2591 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*engine
,
2592 struct drm_i915_gem_object
*default_ctx_obj
)
2594 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2597 /* The HWSP is part of the default context object in LRC mode. */
2598 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
)
2599 + LRC_PPHWSP_PN
* PAGE_SIZE
;
2600 page
= i915_gem_object_get_page(default_ctx_obj
, LRC_PPHWSP_PN
);
2601 engine
->status_page
.page_addr
= kmap(page
);
2602 engine
->status_page
.obj
= default_ctx_obj
;
2604 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
2605 (u32
)engine
->status_page
.gfx_addr
);
2606 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
2610 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2611 * @ctx: LR context to create.
2612 * @ring: engine to be used with the context.
2614 * This function can be called more than once, with different engines, if we plan
2615 * to use the context with them. The context backing objects and the ringbuffers
2616 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2617 * the creation is a deferred call: it's better to make sure first that we need to use
2618 * a given ring with the context.
2620 * Return: non-zero on error.
2623 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
2624 struct intel_engine_cs
*engine
)
2626 struct drm_device
*dev
= engine
->dev
;
2627 struct drm_i915_gem_object
*ctx_obj
;
2628 uint32_t context_size
;
2629 struct intel_ringbuffer
*ringbuf
;
2632 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2633 WARN_ON(ctx
->engine
[engine
->id
].state
);
2635 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2637 /* One extra page as the sharing data between driver and GuC */
2638 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2640 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2642 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2646 ringbuf
= intel_engine_create_ringbuffer(engine
, 4 * PAGE_SIZE
);
2647 if (IS_ERR(ringbuf
)) {
2648 ret
= PTR_ERR(ringbuf
);
2649 goto error_deref_obj
;
2652 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2654 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2658 ctx
->engine
[engine
->id
].ringbuf
= ringbuf
;
2659 ctx
->engine
[engine
->id
].state
= ctx_obj
;
2661 if (ctx
!= ctx
->i915
->kernel_context
&& engine
->init_context
) {
2662 struct drm_i915_gem_request
*req
;
2664 req
= i915_gem_request_alloc(engine
, ctx
);
2667 DRM_ERROR("ring create req: %d\n", ret
);
2671 ret
= engine
->init_context(req
);
2673 DRM_ERROR("ring init context: %d\n",
2675 i915_gem_request_cancel(req
);
2678 i915_add_request_no_flush(req
);
2683 intel_ringbuffer_free(ringbuf
);
2685 drm_gem_object_unreference(&ctx_obj
->base
);
2686 ctx
->engine
[engine
->id
].ringbuf
= NULL
;
2687 ctx
->engine
[engine
->id
].state
= NULL
;
2691 void intel_lr_context_reset(struct drm_device
*dev
,
2692 struct intel_context
*ctx
)
2694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2695 struct intel_engine_cs
*engine
;
2697 for_each_engine(engine
, dev_priv
) {
2698 struct drm_i915_gem_object
*ctx_obj
=
2699 ctx
->engine
[engine
->id
].state
;
2700 struct intel_ringbuffer
*ringbuf
=
2701 ctx
->engine
[engine
->id
].ringbuf
;
2702 uint32_t *reg_state
;
2708 if (i915_gem_object_get_pages(ctx_obj
)) {
2709 WARN(1, "Failed get_pages for context obj\n");
2712 page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
2713 reg_state
= kmap_atomic(page
);
2715 reg_state
[CTX_RING_HEAD
+1] = 0;
2716 reg_state
[CTX_RING_TAIL
+1] = 0;
2718 kunmap_atomic(reg_state
);