2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT
= 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT
, /* Debug only */
224 FAULT_AND_CONTINUE
/* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_ID_WIDTH 21
228 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
229 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
231 static int intel_lr_context_pin(struct intel_context
*ctx
,
232 struct intel_engine_cs
*engine
);
235 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
237 * @enable_execlists: value of i915.enable_execlists module parameter.
239 * Only certain platforms support Execlists (the prerequisites being
240 * support for Logical Ring Contexts and Aliasing PPGTT or better).
242 * Return: 1 if Execlists is supported and has to be enabled.
244 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
246 WARN_ON(i915
.enable_ppgtt
== -1);
248 /* On platforms with execlist available, vGPU will only
249 * support execlist mode, no ring buffer mode.
251 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
254 if (INTEL_INFO(dev
)->gen
>= 9)
257 if (enable_execlists
== 0)
260 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
261 i915
.use_mmio_flip
>= 0)
268 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
270 struct drm_device
*dev
= engine
->dev
;
272 if (IS_GEN8(dev
) || IS_GEN9(dev
))
273 engine
->idle_lite_restore_wa
= ~0;
275 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
276 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) &&
277 (engine
->id
== VCS
|| engine
->id
== VCS2
);
279 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
280 engine
->ctx_desc_template
|= GEN8_CTX_ADDRESSING_MODE(dev
) <<
281 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
283 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
284 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
286 /* TODO: WaDisableLiteRestore when we start using semaphore
287 * signalling between Command Streamers */
288 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
290 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
291 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
292 if (engine
->disable_lite_restore_wa
)
293 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
297 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
298 * descriptor for a pinned context
300 * @ctx: Context to work on
301 * @ring: Engine the descriptor will be used with
303 * The context descriptor encodes various attributes of a context,
304 * including its GTT address and some flags. Because it's fairly
305 * expensive to calculate, we'll just do it once and cache the result,
306 * which remains valid until the context is unpinned.
308 * This is what a descriptor looks like, from LSB to MSB:
309 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
310 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
311 * bits 32-52: ctx ID, a globally unique tag
312 * bits 53-54: mbz, reserved for use by hardware
313 * bits 55-63: group ID, currently unused and set to 0
316 intel_lr_context_descriptor_update(struct intel_context
*ctx
,
317 struct intel_engine_cs
*engine
)
321 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
323 desc
= engine
->ctx_desc_template
; /* bits 0-11 */
324 desc
|= ctx
->engine
[engine
->id
].lrc_vma
->node
.start
+ /* bits 12-31 */
325 LRC_PPHWSP_PN
* PAGE_SIZE
;
326 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
328 ctx
->engine
[engine
->id
].lrc_desc
= desc
;
331 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
332 struct intel_engine_cs
*engine
)
334 return ctx
->engine
[engine
->id
].lrc_desc
;
337 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
338 struct drm_i915_gem_request
*rq1
)
341 struct intel_engine_cs
*engine
= rq0
->engine
;
342 struct drm_device
*dev
= engine
->dev
;
343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
347 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
348 rq1
->elsp_submitted
++;
353 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
354 rq0
->elsp_submitted
++;
356 /* You must always write both descriptors in the order below. */
357 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
358 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
360 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
361 /* The context is automatically loaded after the following */
362 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
364 /* ELSP is a wo register, use another nearby reg for posting */
365 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
369 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
371 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
372 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
373 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
374 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
377 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
379 struct intel_engine_cs
*engine
= rq
->engine
;
380 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
381 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
383 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
385 /* True 32b PPGTT with dynamic page allocation: update PDP
386 * registers and point the unallocated PDPs to scratch page.
387 * PML4 is allocated during ppgtt init, so this is not needed
390 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
391 execlists_update_context_pdps(ppgtt
, reg_state
);
394 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
395 struct drm_i915_gem_request
*rq1
)
397 struct drm_i915_private
*dev_priv
= rq0
->i915
;
398 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
400 execlists_update_context(rq0
);
403 execlists_update_context(rq1
);
405 spin_lock_irq(&dev_priv
->uncore
.lock
);
406 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
408 execlists_elsp_write(rq0
, rq1
);
410 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
411 spin_unlock_irq(&dev_priv
->uncore
.lock
);
414 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
416 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
417 struct drm_i915_gem_request
*cursor
, *tmp
;
419 assert_spin_locked(&engine
->execlist_lock
);
422 * If irqs are not active generate a warning as batches that finish
423 * without the irqs may get lost and a GPU Hang may occur.
425 WARN_ON(!intel_irqs_enabled(engine
->dev
->dev_private
));
427 /* Try to read in pairs */
428 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
432 } else if (req0
->ctx
== cursor
->ctx
) {
433 /* Same ctx: ignore first request, as second request
434 * will update tail past first request's workload */
435 cursor
->elsp_submitted
= req0
->elsp_submitted
;
436 list_move_tail(&req0
->execlist_link
,
437 &engine
->execlist_retired_req_list
);
441 WARN_ON(req1
->elsp_submitted
);
449 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
451 * WaIdleLiteRestore: make sure we never cause a lite restore
454 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
455 * resubmit the request. See gen8_emit_request() for where we
456 * prepare the padding after the end of the request.
458 struct intel_ringbuffer
*ringbuf
;
460 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
462 req0
->tail
&= ringbuf
->size
- 1;
465 execlists_submit_requests(req0
, req1
);
469 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 request_id
)
471 struct drm_i915_gem_request
*head_req
;
473 assert_spin_locked(&engine
->execlist_lock
);
475 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
476 struct drm_i915_gem_request
,
482 if (unlikely(head_req
->ctx
->hw_id
!= request_id
))
485 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
487 if (--head_req
->elsp_submitted
> 0)
490 list_move_tail(&head_req
->execlist_link
,
491 &engine
->execlist_retired_req_list
);
497 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
500 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
503 read_pointer
%= GEN8_CSB_ENTRIES
;
505 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
507 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
510 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
517 * intel_lrc_irq_handler() - handle Context Switch interrupts
518 * @engine: Engine Command Streamer to handle.
520 * Check the unread Context Status Buffers and manage the submission of new
521 * contexts to the ELSP accordingly.
523 static void intel_lrc_irq_handler(unsigned long data
)
525 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
526 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
528 unsigned int read_pointer
, write_pointer
;
529 u32 csb
[GEN8_CSB_ENTRIES
][2];
530 unsigned int csb_read
= 0, i
;
531 unsigned int submit_contexts
= 0;
533 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
535 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
537 read_pointer
= engine
->next_context_status_buffer
;
538 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
539 if (read_pointer
> write_pointer
)
540 write_pointer
+= GEN8_CSB_ENTRIES
;
542 while (read_pointer
< write_pointer
) {
543 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
545 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
550 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
552 /* Update the read pointer to the old write pointer. Manual ringbuffer
553 * management ftw </sarcasm> */
554 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
555 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
556 engine
->next_context_status_buffer
<< 8));
558 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
560 spin_lock(&engine
->execlist_lock
);
562 for (i
= 0; i
< csb_read
; i
++) {
563 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
564 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
565 if (execlists_check_remove_request(engine
, csb
[i
][1]))
566 WARN(1, "Lite Restored request removed from queue\n");
568 WARN(1, "Preemption without Lite Restore\n");
571 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
572 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
574 execlists_check_remove_request(engine
, csb
[i
][1]);
577 if (submit_contexts
) {
578 if (!engine
->disable_lite_restore_wa
||
579 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
580 execlists_context_unqueue(engine
);
583 spin_unlock(&engine
->execlist_lock
);
585 if (unlikely(submit_contexts
> 2))
586 DRM_ERROR("More than two context complete events?\n");
589 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
591 struct intel_engine_cs
*engine
= request
->engine
;
592 struct drm_i915_gem_request
*cursor
;
593 int num_elements
= 0;
595 if (request
->ctx
!= request
->i915
->kernel_context
)
596 intel_lr_context_pin(request
->ctx
, engine
);
598 i915_gem_request_reference(request
);
600 spin_lock_bh(&engine
->execlist_lock
);
602 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
603 if (++num_elements
> 2)
606 if (num_elements
> 2) {
607 struct drm_i915_gem_request
*tail_req
;
609 tail_req
= list_last_entry(&engine
->execlist_queue
,
610 struct drm_i915_gem_request
,
613 if (request
->ctx
== tail_req
->ctx
) {
614 WARN(tail_req
->elsp_submitted
!= 0,
615 "More than 2 already-submitted reqs queued\n");
616 list_move_tail(&tail_req
->execlist_link
,
617 &engine
->execlist_retired_req_list
);
621 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
622 if (num_elements
== 0)
623 execlists_context_unqueue(engine
);
625 spin_unlock_bh(&engine
->execlist_lock
);
628 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
630 struct intel_engine_cs
*engine
= req
->engine
;
631 uint32_t flush_domains
;
635 if (engine
->gpu_caches_dirty
)
636 flush_domains
= I915_GEM_GPU_DOMAINS
;
638 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
642 engine
->gpu_caches_dirty
= false;
646 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
647 struct list_head
*vmas
)
649 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
650 struct i915_vma
*vma
;
651 uint32_t flush_domains
= 0;
652 bool flush_chipset
= false;
655 list_for_each_entry(vma
, vmas
, exec_list
) {
656 struct drm_i915_gem_object
*obj
= vma
->obj
;
658 if (obj
->active
& other_rings
) {
659 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
664 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
665 flush_chipset
|= i915_gem_clflush_object(obj
, false);
667 flush_domains
|= obj
->base
.write_domain
;
670 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
673 /* Unconditionally invalidate gpu caches and ensure that we do flush
674 * any residual writes from the previous batch.
676 return logical_ring_invalidate_all_caches(req
);
679 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
683 /* Flush enough space to reduce the likelihood of waiting after
684 * we start building the request - in which case we will just
685 * have to repeat work.
687 request
->reserved_space
+= MIN_SPACE_FOR_ADD_REQUEST
;
689 request
->ringbuf
= request
->ctx
->engine
[request
->engine
->id
].ringbuf
;
691 if (i915
.enable_guc_submission
) {
693 * Check that the GuC has space for the request before
694 * going any further, as the i915_add_request() call
695 * later on mustn't fail ...
697 struct intel_guc
*guc
= &request
->i915
->guc
;
699 ret
= i915_guc_wq_check_space(guc
->execbuf_client
);
704 if (request
->ctx
!= request
->i915
->kernel_context
) {
705 ret
= intel_lr_context_pin(request
->ctx
, request
->engine
);
710 ret
= intel_ring_begin(request
, 0);
714 request
->reserved_space
-= MIN_SPACE_FOR_ADD_REQUEST
;
718 if (request
->ctx
!= request
->i915
->kernel_context
)
719 intel_lr_context_unpin(request
->ctx
, request
->engine
);
724 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
725 * @request: Request to advance the logical ringbuffer of.
727 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
728 * really happens during submission is that the context and current tail will be placed
729 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
730 * point, the tail *inside* the context is updated and the ELSP written to.
733 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
735 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
736 struct drm_i915_private
*dev_priv
= request
->i915
;
737 struct intel_engine_cs
*engine
= request
->engine
;
739 intel_logical_ring_advance(ringbuf
);
740 request
->tail
= ringbuf
->tail
;
743 * Here we add two extra NOOPs as padding to avoid
744 * lite restore of a context with HEAD==TAIL.
746 * Caller must reserve WA_TAIL_DWORDS for us!
748 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
749 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
750 intel_logical_ring_advance(ringbuf
);
752 if (intel_engine_stopped(engine
))
755 if (engine
->last_context
!= request
->ctx
) {
756 if (engine
->last_context
)
757 intel_lr_context_unpin(engine
->last_context
, engine
);
758 if (request
->ctx
!= request
->i915
->kernel_context
) {
759 intel_lr_context_pin(request
->ctx
, engine
);
760 engine
->last_context
= request
->ctx
;
762 engine
->last_context
= NULL
;
766 if (dev_priv
->guc
.execbuf_client
)
767 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
769 execlists_context_queue(request
);
775 * execlists_submission() - submit a batchbuffer for execution, Execlists style
778 * @ring: Engine Command Streamer to submit to.
779 * @ctx: Context to employ for this submission.
780 * @args: execbuffer call arguments.
781 * @vmas: list of vmas.
782 * @batch_obj: the batchbuffer to submit.
783 * @exec_start: batchbuffer start virtual address pointer.
784 * @dispatch_flags: translated execbuffer call flags.
786 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
787 * away the submission details of the execbuffer ioctl call.
789 * Return: non-zero if the submission fails.
791 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
792 struct drm_i915_gem_execbuffer2
*args
,
793 struct list_head
*vmas
)
795 struct drm_device
*dev
= params
->dev
;
796 struct intel_engine_cs
*engine
= params
->engine
;
797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
798 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
804 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
805 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
806 switch (instp_mode
) {
807 case I915_EXEC_CONSTANTS_REL_GENERAL
:
808 case I915_EXEC_CONSTANTS_ABSOLUTE
:
809 case I915_EXEC_CONSTANTS_REL_SURFACE
:
810 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
811 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
815 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
816 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
817 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
821 /* The HW changed the meaning on this bit on gen6 */
822 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
826 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
830 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
831 DRM_DEBUG("sol reset is gen7 only\n");
835 ret
= execlists_move_to_gpu(params
->request
, vmas
);
839 if (engine
== &dev_priv
->engine
[RCS
] &&
840 instp_mode
!= dev_priv
->relative_constants_mode
) {
841 ret
= intel_ring_begin(params
->request
, 4);
845 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
846 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
847 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
848 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
849 intel_logical_ring_advance(ringbuf
);
851 dev_priv
->relative_constants_mode
= instp_mode
;
854 exec_start
= params
->batch_obj_vm_offset
+
855 args
->batch_start_offset
;
857 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
861 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
863 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
868 void intel_execlists_retire_requests(struct intel_engine_cs
*engine
)
870 struct drm_i915_gem_request
*req
, *tmp
;
871 struct list_head retired_list
;
873 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
874 if (list_empty(&engine
->execlist_retired_req_list
))
877 INIT_LIST_HEAD(&retired_list
);
878 spin_lock_bh(&engine
->execlist_lock
);
879 list_replace_init(&engine
->execlist_retired_req_list
, &retired_list
);
880 spin_unlock_bh(&engine
->execlist_lock
);
882 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
883 struct intel_context
*ctx
= req
->ctx
;
884 struct drm_i915_gem_object
*ctx_obj
=
885 ctx
->engine
[engine
->id
].state
;
887 if (ctx_obj
&& (ctx
!= req
->i915
->kernel_context
))
888 intel_lr_context_unpin(ctx
, engine
);
890 list_del(&req
->execlist_link
);
891 i915_gem_request_unreference(req
);
895 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
897 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
900 if (!intel_engine_initialized(engine
))
903 ret
= intel_engine_idle(engine
);
905 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
908 /* TODO: Is this correct with Execlists enabled? */
909 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
910 if (wait_for((I915_READ_MODE(engine
) & MODE_IDLE
) != 0, 1000)) {
911 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
914 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
917 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
919 struct intel_engine_cs
*engine
= req
->engine
;
922 if (!engine
->gpu_caches_dirty
)
925 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
929 engine
->gpu_caches_dirty
= false;
933 static int intel_lr_context_do_pin(struct intel_context
*ctx
,
934 struct intel_engine_cs
*engine
)
936 struct drm_device
*dev
= engine
->dev
;
937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
938 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
939 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[engine
->id
].ringbuf
;
944 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
946 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
947 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
951 vaddr
= i915_gem_object_pin_map(ctx_obj
);
953 ret
= PTR_ERR(vaddr
);
957 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
959 ret
= intel_pin_and_map_ringbuffer_obj(engine
->dev
, ringbuf
);
963 ctx
->engine
[engine
->id
].lrc_vma
= i915_gem_obj_to_ggtt(ctx_obj
);
964 intel_lr_context_descriptor_update(ctx
, engine
);
965 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ringbuf
->vma
->node
.start
;
966 ctx
->engine
[engine
->id
].lrc_reg_state
= lrc_reg_state
;
967 ctx_obj
->dirty
= true;
969 /* Invalidate GuC TLB. */
970 if (i915
.enable_guc_submission
)
971 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
976 i915_gem_object_unpin_map(ctx_obj
);
978 i915_gem_object_ggtt_unpin(ctx_obj
);
983 static int intel_lr_context_pin(struct intel_context
*ctx
,
984 struct intel_engine_cs
*engine
)
988 if (ctx
->engine
[engine
->id
].pin_count
++ == 0) {
989 ret
= intel_lr_context_do_pin(ctx
, engine
);
991 goto reset_pin_count
;
993 i915_gem_context_reference(ctx
);
998 ctx
->engine
[engine
->id
].pin_count
= 0;
1002 void intel_lr_context_unpin(struct intel_context
*ctx
,
1003 struct intel_engine_cs
*engine
)
1005 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
1007 WARN_ON(!mutex_is_locked(&ctx
->i915
->dev
->struct_mutex
));
1008 if (--ctx
->engine
[engine
->id
].pin_count
== 0) {
1009 i915_gem_object_unpin_map(ctx_obj
);
1010 intel_unpin_ringbuffer_obj(ctx
->engine
[engine
->id
].ringbuf
);
1011 i915_gem_object_ggtt_unpin(ctx_obj
);
1012 ctx
->engine
[engine
->id
].lrc_vma
= NULL
;
1013 ctx
->engine
[engine
->id
].lrc_desc
= 0;
1014 ctx
->engine
[engine
->id
].lrc_reg_state
= NULL
;
1016 i915_gem_context_unreference(ctx
);
1020 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1023 struct intel_engine_cs
*engine
= req
->engine
;
1024 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1025 struct drm_device
*dev
= engine
->dev
;
1026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1027 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1032 engine
->gpu_caches_dirty
= true;
1033 ret
= logical_ring_flush_all_caches(req
);
1037 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
1041 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1042 for (i
= 0; i
< w
->count
; i
++) {
1043 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1044 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1046 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1048 intel_logical_ring_advance(ringbuf
);
1050 engine
->gpu_caches_dirty
= true;
1051 ret
= logical_ring_flush_all_caches(req
);
1058 #define wa_ctx_emit(batch, index, cmd) \
1060 int __index = (index)++; \
1061 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1064 batch[__index] = (cmd); \
1067 #define wa_ctx_emit_reg(batch, index, reg) \
1068 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1071 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1072 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1073 * but there is a slight complication as this is applied in WA batch where the
1074 * values are only initialized once so we cannot take register value at the
1075 * beginning and reuse it further; hence we save its value to memory, upload a
1076 * constant value with bit21 set and then we restore it back with the saved value.
1077 * To simplify the WA, a constant value is formed by using the default value
1078 * of this register. This shouldn't be a problem because we are only modifying
1079 * it for a short period and this batch in non-premptible. We can ofcourse
1080 * use additional instructions that read the actual value of the register
1081 * at that time and set our bit of interest but it makes the WA complicated.
1083 * This WA is also required for Gen9 so extracting as a function avoids
1086 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1087 uint32_t *const batch
,
1090 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1093 * WaDisableLSQCROPERFforOCL:skl
1094 * This WA is implemented in skl_init_clock_gating() but since
1095 * this batch updates GEN8_L3SQCREG4 with default value we need to
1096 * set this bit here to retain the WA during flush.
1098 if (IS_SKL_REVID(engine
->dev
, 0, SKL_REVID_E0
))
1099 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1101 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1102 MI_SRM_LRM_GLOBAL_GTT
));
1103 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1104 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1105 wa_ctx_emit(batch
, index
, 0);
1107 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1108 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1109 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1111 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1112 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1113 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1114 wa_ctx_emit(batch
, index
, 0);
1115 wa_ctx_emit(batch
, index
, 0);
1116 wa_ctx_emit(batch
, index
, 0);
1117 wa_ctx_emit(batch
, index
, 0);
1119 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1120 MI_SRM_LRM_GLOBAL_GTT
));
1121 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1122 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1123 wa_ctx_emit(batch
, index
, 0);
1128 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1130 uint32_t start_alignment
)
1132 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1135 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1137 uint32_t size_alignment
)
1139 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1141 WARN(wa_ctx
->size
% size_alignment
,
1142 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1143 wa_ctx
->size
, size_alignment
);
1148 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1150 * @ring: only applicable for RCS
1151 * @wa_ctx: structure representing wa_ctx
1152 * offset: specifies start of the batch, should be cache-aligned. This is updated
1153 * with the offset value received as input.
1154 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1155 * @batch: page in which WA are loaded
1156 * @offset: This field specifies the start of the batch, it should be
1157 * cache-aligned otherwise it is adjusted accordingly.
1158 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1159 * initialized at the beginning and shared across all contexts but this field
1160 * helps us to have multiple batches at different offsets and select them based
1161 * on a criteria. At the moment this batch always start at the beginning of the page
1162 * and at this point we don't have multiple wa_ctx batch buffers.
1164 * The number of WA applied are not known at the beginning; we use this field
1165 * to return the no of DWORDS written.
1167 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1168 * so it adds NOOPs as padding to make it cacheline aligned.
1169 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1170 * makes a complete batch buffer.
1172 * Return: non-zero if we exceed the PAGE_SIZE limit.
1175 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1176 struct i915_wa_ctx_bb
*wa_ctx
,
1177 uint32_t *const batch
,
1180 uint32_t scratch_addr
;
1181 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1183 /* WaDisableCtxRestoreArbitration:bdw,chv */
1184 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1186 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1187 if (IS_BROADWELL(engine
->dev
)) {
1188 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1194 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1195 /* Actual scratch location is at 128 bytes offset */
1196 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1198 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1199 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1200 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1201 PIPE_CONTROL_CS_STALL
|
1202 PIPE_CONTROL_QW_WRITE
));
1203 wa_ctx_emit(batch
, index
, scratch_addr
);
1204 wa_ctx_emit(batch
, index
, 0);
1205 wa_ctx_emit(batch
, index
, 0);
1206 wa_ctx_emit(batch
, index
, 0);
1208 /* Pad to end of cacheline */
1209 while (index
% CACHELINE_DWORDS
)
1210 wa_ctx_emit(batch
, index
, MI_NOOP
);
1213 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1214 * execution depends on the length specified in terms of cache lines
1215 * in the register CTX_RCS_INDIRECT_CTX
1218 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1222 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1224 * @ring: only applicable for RCS
1225 * @wa_ctx: structure representing wa_ctx
1226 * offset: specifies start of the batch, should be cache-aligned.
1227 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1228 * @batch: page in which WA are loaded
1229 * @offset: This field specifies the start of this batch.
1230 * This batch is started immediately after indirect_ctx batch. Since we ensure
1231 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1233 * The number of DWORDS written are returned using this field.
1235 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1236 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1238 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1239 struct i915_wa_ctx_bb
*wa_ctx
,
1240 uint32_t *const batch
,
1243 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1245 /* WaDisableCtxRestoreArbitration:bdw,chv */
1246 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1248 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1250 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1253 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1254 struct i915_wa_ctx_bb
*wa_ctx
,
1255 uint32_t *const batch
,
1259 struct drm_device
*dev
= engine
->dev
;
1260 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1262 /* WaDisableCtxRestoreArbitration:skl,bxt */
1263 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1264 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1265 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1267 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1268 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1273 /* Pad to end of cacheline */
1274 while (index
% CACHELINE_DWORDS
)
1275 wa_ctx_emit(batch
, index
, MI_NOOP
);
1277 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1280 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1281 struct i915_wa_ctx_bb
*wa_ctx
,
1282 uint32_t *const batch
,
1285 struct drm_device
*dev
= engine
->dev
;
1286 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1288 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1289 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
1290 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1291 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1292 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1293 wa_ctx_emit(batch
, index
,
1294 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1295 wa_ctx_emit(batch
, index
, MI_NOOP
);
1298 /* WaClearTdlStateAckDirtyBits:bxt */
1299 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1300 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1302 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1303 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1305 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1306 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1308 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1309 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1311 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1312 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1313 wa_ctx_emit(batch
, index
, 0x0);
1314 wa_ctx_emit(batch
, index
, MI_NOOP
);
1317 /* WaDisableCtxRestoreArbitration:skl,bxt */
1318 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1319 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1320 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1322 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1324 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1327 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1331 engine
->wa_ctx
.obj
= i915_gem_object_create(engine
->dev
,
1333 if (IS_ERR(engine
->wa_ctx
.obj
)) {
1334 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1335 ret
= PTR_ERR(engine
->wa_ctx
.obj
);
1336 engine
->wa_ctx
.obj
= NULL
;
1340 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1342 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1344 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1351 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1353 if (engine
->wa_ctx
.obj
) {
1354 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1355 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1356 engine
->wa_ctx
.obj
= NULL
;
1360 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1366 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1368 WARN_ON(engine
->id
!= RCS
);
1370 /* update this when WA for higher Gen are added */
1371 if (INTEL_INFO(engine
->dev
)->gen
> 9) {
1372 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1373 INTEL_INFO(engine
->dev
)->gen
);
1377 /* some WA perform writes to scratch page, ensure it is valid */
1378 if (engine
->scratch
.obj
== NULL
) {
1379 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1383 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1385 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1389 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1390 batch
= kmap_atomic(page
);
1393 if (INTEL_INFO(engine
->dev
)->gen
== 8) {
1394 ret
= gen8_init_indirectctx_bb(engine
,
1395 &wa_ctx
->indirect_ctx
,
1401 ret
= gen8_init_perctx_bb(engine
,
1407 } else if (INTEL_INFO(engine
->dev
)->gen
== 9) {
1408 ret
= gen9_init_indirectctx_bb(engine
,
1409 &wa_ctx
->indirect_ctx
,
1415 ret
= gen9_init_perctx_bb(engine
,
1424 kunmap_atomic(batch
);
1426 lrc_destroy_wa_ctx_obj(engine
);
1431 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1433 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
1435 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1436 (u32
)engine
->status_page
.gfx_addr
);
1437 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1440 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1442 struct drm_device
*dev
= engine
->dev
;
1443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 unsigned int next_context_status_buffer_hw
;
1446 lrc_init_hws(engine
);
1448 I915_WRITE_IMR(engine
,
1449 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1450 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1452 I915_WRITE(RING_MODE_GEN7(engine
),
1453 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1454 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1455 POSTING_READ(RING_MODE_GEN7(engine
));
1458 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1459 * zero, we need to read the write pointer from hardware and use its
1460 * value because "this register is power context save restored".
1461 * Effectively, these states have been observed:
1463 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1464 * BDW | CSB regs not reset | CSB regs reset |
1465 * CHT | CSB regs not reset | CSB regs not reset |
1469 next_context_status_buffer_hw
=
1470 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1473 * When the CSB registers are reset (also after power-up / gpu reset),
1474 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1475 * this special case, so the first element read is CSB[0].
1477 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1478 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1480 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1481 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1483 intel_engine_init_hangcheck(engine
);
1485 return intel_mocs_init_engine(engine
);
1488 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1490 struct drm_device
*dev
= engine
->dev
;
1491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1494 ret
= gen8_init_common_ring(engine
);
1498 /* We need to disable the AsyncFlip performance optimisations in order
1499 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1500 * programmed to '1' on all products.
1502 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1504 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1506 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1508 return init_workarounds_ring(engine
);
1511 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1515 ret
= gen8_init_common_ring(engine
);
1519 return init_workarounds_ring(engine
);
1522 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1524 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1525 struct intel_engine_cs
*engine
= req
->engine
;
1526 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1527 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1530 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1534 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1535 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1536 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1538 intel_logical_ring_emit_reg(ringbuf
,
1539 GEN8_RING_PDP_UDW(engine
, i
));
1540 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1541 intel_logical_ring_emit_reg(ringbuf
,
1542 GEN8_RING_PDP_LDW(engine
, i
));
1543 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1546 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1547 intel_logical_ring_advance(ringbuf
);
1552 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1553 u64 offset
, unsigned dispatch_flags
)
1555 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1556 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1559 /* Don't rely in hw updating PDPs, specially in lite-restore.
1560 * Ideally, we should set Force PD Restore in ctx descriptor,
1561 * but we can't. Force Restore would be a second option, but
1562 * it is unsafe in case of lite-restore (because the ctx is
1563 * not idle). PML4 is allocated during ppgtt init so this is
1564 * not needed in 48-bit.*/
1565 if (req
->ctx
->ppgtt
&&
1566 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1567 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1568 !intel_vgpu_active(req
->i915
->dev
)) {
1569 ret
= intel_logical_ring_emit_pdps(req
);
1574 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1577 ret
= intel_ring_begin(req
, 4);
1581 /* FIXME(BDW): Address space and security selectors. */
1582 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1584 (dispatch_flags
& I915_DISPATCH_RS
?
1585 MI_BATCH_RESOURCE_STREAMER
: 0));
1586 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1587 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1588 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1589 intel_logical_ring_advance(ringbuf
);
1594 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*engine
)
1596 struct drm_device
*dev
= engine
->dev
;
1597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1598 unsigned long flags
;
1600 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1603 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1604 if (engine
->irq_refcount
++ == 0) {
1605 I915_WRITE_IMR(engine
,
1606 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1607 POSTING_READ(RING_IMR(engine
->mmio_base
));
1609 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1614 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*engine
)
1616 struct drm_device
*dev
= engine
->dev
;
1617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1618 unsigned long flags
;
1620 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1621 if (--engine
->irq_refcount
== 0) {
1622 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1623 POSTING_READ(RING_IMR(engine
->mmio_base
));
1625 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1628 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1629 u32 invalidate_domains
,
1632 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1633 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1634 struct drm_device
*dev
= engine
->dev
;
1635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 ret
= intel_ring_begin(request
, 4);
1643 cmd
= MI_FLUSH_DW
+ 1;
1645 /* We always require a command barrier so that subsequent
1646 * commands, such as breadcrumb interrupts, are strictly ordered
1647 * wrt the contents of the write cache being flushed to memory
1648 * (and thus being coherent from the CPU).
1650 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1652 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1653 cmd
|= MI_INVALIDATE_TLB
;
1654 if (engine
== &dev_priv
->engine
[VCS
])
1655 cmd
|= MI_INVALIDATE_BSD
;
1658 intel_logical_ring_emit(ringbuf
, cmd
);
1659 intel_logical_ring_emit(ringbuf
,
1660 I915_GEM_HWS_SCRATCH_ADDR
|
1661 MI_FLUSH_DW_USE_GTT
);
1662 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1663 intel_logical_ring_emit(ringbuf
, 0); /* value */
1664 intel_logical_ring_advance(ringbuf
);
1669 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1670 u32 invalidate_domains
,
1673 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1674 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1675 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1676 bool vf_flush_wa
= false;
1680 flags
|= PIPE_CONTROL_CS_STALL
;
1682 if (flush_domains
) {
1683 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1684 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1685 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1686 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1689 if (invalidate_domains
) {
1690 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1691 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1692 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1693 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1694 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1695 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1696 flags
|= PIPE_CONTROL_QW_WRITE
;
1697 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1700 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1703 if (IS_GEN9(engine
->dev
))
1707 ret
= intel_ring_begin(request
, vf_flush_wa
? 12 : 6);
1712 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1713 intel_logical_ring_emit(ringbuf
, 0);
1714 intel_logical_ring_emit(ringbuf
, 0);
1715 intel_logical_ring_emit(ringbuf
, 0);
1716 intel_logical_ring_emit(ringbuf
, 0);
1717 intel_logical_ring_emit(ringbuf
, 0);
1720 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1721 intel_logical_ring_emit(ringbuf
, flags
);
1722 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1723 intel_logical_ring_emit(ringbuf
, 0);
1724 intel_logical_ring_emit(ringbuf
, 0);
1725 intel_logical_ring_emit(ringbuf
, 0);
1726 intel_logical_ring_advance(ringbuf
);
1731 static u32
gen8_get_seqno(struct intel_engine_cs
*engine
)
1733 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1736 static void gen8_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1738 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1741 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1744 * On BXT A steppings there is a HW coherency issue whereby the
1745 * MI_STORE_DATA_IMM storing the completed request's seqno
1746 * occasionally doesn't invalidate the CPU cache. Work around this by
1747 * clflushing the corresponding cacheline whenever the caller wants
1748 * the coherency to be guaranteed. Note that this cacheline is known
1749 * to be clean at this point, since we only write it in
1750 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1751 * this clflush in practice becomes an invalidate operation.
1753 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1756 static void bxt_a_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1758 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1760 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1761 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1765 * Reserve space for 2 NOOPs at the end of each request to be
1766 * used as a workaround for not being allowed to do lite
1767 * restore with HEAD==TAIL (WaIdleLiteRestore).
1769 #define WA_TAIL_DWORDS 2
1771 static inline u32
hws_seqno_address(struct intel_engine_cs
*engine
)
1773 return engine
->status_page
.gfx_addr
+ I915_GEM_HWS_INDEX_ADDR
;
1776 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1778 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1781 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1785 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1786 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1788 intel_logical_ring_emit(ringbuf
,
1789 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1790 intel_logical_ring_emit(ringbuf
,
1791 hws_seqno_address(request
->engine
) |
1792 MI_FLUSH_DW_USE_GTT
);
1793 intel_logical_ring_emit(ringbuf
, 0);
1794 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1795 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1796 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1797 return intel_logical_ring_advance_and_submit(request
);
1800 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1802 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1805 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1809 /* We're using qword write, seqno should be aligned to 8 bytes. */
1810 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1812 /* w/a for post sync ops following a GPGPU operation we
1813 * need a prior CS_STALL, which is emitted by the flush
1814 * following the batch.
1816 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1817 intel_logical_ring_emit(ringbuf
,
1818 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1819 PIPE_CONTROL_CS_STALL
|
1820 PIPE_CONTROL_QW_WRITE
));
1821 intel_logical_ring_emit(ringbuf
, hws_seqno_address(request
->engine
));
1822 intel_logical_ring_emit(ringbuf
, 0);
1823 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1824 /* We're thrashing one dword of HWS. */
1825 intel_logical_ring_emit(ringbuf
, 0);
1826 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1827 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1828 return intel_logical_ring_advance_and_submit(request
);
1831 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1833 struct render_state so
;
1836 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1840 if (so
.rodata
== NULL
)
1843 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1844 I915_DISPATCH_SECURE
);
1848 ret
= req
->engine
->emit_bb_start(req
,
1849 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1850 I915_DISPATCH_SECURE
);
1854 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1857 i915_gem_render_state_fini(&so
);
1861 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1865 ret
= intel_logical_ring_workarounds_emit(req
);
1869 ret
= intel_rcs_context_init_mocs(req
);
1871 * Failing to program the MOCS is non-fatal.The system will not
1872 * run at peak performance. So generate an error and carry on.
1875 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1877 return intel_lr_context_render_state_init(req
);
1881 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1883 * @ring: Engine Command Streamer.
1886 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1888 struct drm_i915_private
*dev_priv
;
1890 if (!intel_engine_initialized(engine
))
1894 * Tasklet cannot be active at this point due intel_mark_active/idle
1895 * so this is just for documentation.
1897 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1898 tasklet_kill(&engine
->irq_tasklet
);
1900 dev_priv
= engine
->dev
->dev_private
;
1902 if (engine
->buffer
) {
1903 intel_logical_ring_stop(engine
);
1904 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1907 if (engine
->cleanup
)
1908 engine
->cleanup(engine
);
1910 i915_cmd_parser_fini_ring(engine
);
1911 i915_gem_batch_pool_fini(&engine
->batch_pool
);
1913 if (engine
->status_page
.obj
) {
1914 i915_gem_object_unpin_map(engine
->status_page
.obj
);
1915 engine
->status_page
.obj
= NULL
;
1918 engine
->idle_lite_restore_wa
= 0;
1919 engine
->disable_lite_restore_wa
= false;
1920 engine
->ctx_desc_template
= 0;
1922 lrc_destroy_wa_ctx_obj(engine
);
1927 logical_ring_default_vfuncs(struct drm_device
*dev
,
1928 struct intel_engine_cs
*engine
)
1930 /* Default vfuncs which can be overriden by each engine. */
1931 engine
->init_hw
= gen8_init_common_ring
;
1932 engine
->emit_request
= gen8_emit_request
;
1933 engine
->emit_flush
= gen8_emit_flush
;
1934 engine
->irq_get
= gen8_logical_ring_get_irq
;
1935 engine
->irq_put
= gen8_logical_ring_put_irq
;
1936 engine
->emit_bb_start
= gen8_emit_bb_start
;
1937 engine
->get_seqno
= gen8_get_seqno
;
1938 engine
->set_seqno
= gen8_set_seqno
;
1939 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1940 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1941 engine
->set_seqno
= bxt_a_set_seqno
;
1946 logical_ring_default_irqs(struct intel_engine_cs
*engine
, unsigned shift
)
1948 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1949 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1953 lrc_setup_hws(struct intel_engine_cs
*engine
,
1954 struct drm_i915_gem_object
*dctx_obj
)
1958 /* The HWSP is part of the default context object in LRC mode. */
1959 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
) +
1960 LRC_PPHWSP_PN
* PAGE_SIZE
;
1961 hws
= i915_gem_object_pin_map(dctx_obj
);
1963 return PTR_ERR(hws
);
1964 engine
->status_page
.page_addr
= hws
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
1965 engine
->status_page
.obj
= dctx_obj
;
1971 logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*engine
)
1973 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1974 struct intel_context
*dctx
= dev_priv
->kernel_context
;
1975 enum forcewake_domains fw_domains
;
1978 /* Intentionally left blank. */
1979 engine
->buffer
= NULL
;
1982 INIT_LIST_HEAD(&engine
->active_list
);
1983 INIT_LIST_HEAD(&engine
->request_list
);
1984 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
1985 init_waitqueue_head(&engine
->irq_queue
);
1987 INIT_LIST_HEAD(&engine
->buffers
);
1988 INIT_LIST_HEAD(&engine
->execlist_queue
);
1989 INIT_LIST_HEAD(&engine
->execlist_retired_req_list
);
1990 spin_lock_init(&engine
->execlist_lock
);
1992 tasklet_init(&engine
->irq_tasklet
,
1993 intel_lrc_irq_handler
, (unsigned long)engine
);
1995 logical_ring_init_platform_invariants(engine
);
1997 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
2001 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2002 RING_CONTEXT_STATUS_PTR(engine
),
2003 FW_REG_READ
| FW_REG_WRITE
);
2005 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2006 RING_CONTEXT_STATUS_BUF_BASE(engine
),
2009 engine
->fw_domains
= fw_domains
;
2011 ret
= i915_cmd_parser_init_ring(engine
);
2015 ret
= intel_lr_context_deferred_alloc(dctx
, engine
);
2019 /* As this is the default context, always pin it */
2020 ret
= intel_lr_context_do_pin(dctx
, engine
);
2023 "Failed to pin and map ringbuffer %s: %d\n",
2028 /* And setup the hardware status page. */
2029 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
2031 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
2038 intel_logical_ring_cleanup(engine
);
2042 static int logical_render_ring_init(struct drm_device
*dev
)
2044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2045 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2048 engine
->name
= "render ring";
2050 engine
->exec_id
= I915_EXEC_RENDER
;
2051 engine
->guc_id
= GUC_RENDER_ENGINE
;
2052 engine
->mmio_base
= RENDER_RING_BASE
;
2054 logical_ring_default_irqs(engine
, GEN8_RCS_IRQ_SHIFT
);
2055 if (HAS_L3_DPF(dev
))
2056 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2058 logical_ring_default_vfuncs(dev
, engine
);
2060 /* Override some for render ring. */
2061 if (INTEL_INFO(dev
)->gen
>= 9)
2062 engine
->init_hw
= gen9_init_render_ring
;
2064 engine
->init_hw
= gen8_init_render_ring
;
2065 engine
->init_context
= gen8_init_rcs_context
;
2066 engine
->cleanup
= intel_fini_pipe_control
;
2067 engine
->emit_flush
= gen8_emit_flush_render
;
2068 engine
->emit_request
= gen8_emit_request_render
;
2072 ret
= intel_init_pipe_control(engine
);
2076 ret
= intel_init_workaround_bb(engine
);
2079 * We continue even if we fail to initialize WA batch
2080 * because we only expect rare glitches but nothing
2081 * critical to prevent us from using GPU
2083 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2087 ret
= logical_ring_init(dev
, engine
);
2089 lrc_destroy_wa_ctx_obj(engine
);
2095 static int logical_bsd_ring_init(struct drm_device
*dev
)
2097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2098 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2100 engine
->name
= "bsd ring";
2102 engine
->exec_id
= I915_EXEC_BSD
;
2103 engine
->guc_id
= GUC_VIDEO_ENGINE
;
2104 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2106 logical_ring_default_irqs(engine
, GEN8_VCS1_IRQ_SHIFT
);
2107 logical_ring_default_vfuncs(dev
, engine
);
2109 return logical_ring_init(dev
, engine
);
2112 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2115 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
2117 engine
->name
= "bsd2 ring";
2119 engine
->exec_id
= I915_EXEC_BSD
;
2120 engine
->guc_id
= GUC_VIDEO_ENGINE2
;
2121 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
2123 logical_ring_default_irqs(engine
, GEN8_VCS2_IRQ_SHIFT
);
2124 logical_ring_default_vfuncs(dev
, engine
);
2126 return logical_ring_init(dev
, engine
);
2129 static int logical_blt_ring_init(struct drm_device
*dev
)
2131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2132 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
2134 engine
->name
= "blitter ring";
2136 engine
->exec_id
= I915_EXEC_BLT
;
2137 engine
->guc_id
= GUC_BLITTER_ENGINE
;
2138 engine
->mmio_base
= BLT_RING_BASE
;
2140 logical_ring_default_irqs(engine
, GEN8_BCS_IRQ_SHIFT
);
2141 logical_ring_default_vfuncs(dev
, engine
);
2143 return logical_ring_init(dev
, engine
);
2146 static int logical_vebox_ring_init(struct drm_device
*dev
)
2148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2149 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
2151 engine
->name
= "video enhancement ring";
2153 engine
->exec_id
= I915_EXEC_VEBOX
;
2154 engine
->guc_id
= GUC_VIDEOENHANCE_ENGINE
;
2155 engine
->mmio_base
= VEBOX_RING_BASE
;
2157 logical_ring_default_irqs(engine
, GEN8_VECS_IRQ_SHIFT
);
2158 logical_ring_default_vfuncs(dev
, engine
);
2160 return logical_ring_init(dev
, engine
);
2164 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2167 * This function inits the engines for an Execlists submission style (the equivalent in the
2168 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2169 * those engines that are present in the hardware.
2171 * Return: non-zero if the initialization failed.
2173 int intel_logical_rings_init(struct drm_device
*dev
)
2175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2178 ret
= logical_render_ring_init(dev
);
2183 ret
= logical_bsd_ring_init(dev
);
2185 goto cleanup_render_ring
;
2189 ret
= logical_blt_ring_init(dev
);
2191 goto cleanup_bsd_ring
;
2194 if (HAS_VEBOX(dev
)) {
2195 ret
= logical_vebox_ring_init(dev
);
2197 goto cleanup_blt_ring
;
2200 if (HAS_BSD2(dev
)) {
2201 ret
= logical_bsd2_ring_init(dev
);
2203 goto cleanup_vebox_ring
;
2209 intel_logical_ring_cleanup(&dev_priv
->engine
[VECS
]);
2211 intel_logical_ring_cleanup(&dev_priv
->engine
[BCS
]);
2213 intel_logical_ring_cleanup(&dev_priv
->engine
[VCS
]);
2214 cleanup_render_ring
:
2215 intel_logical_ring_cleanup(&dev_priv
->engine
[RCS
]);
2221 make_rpcs(struct drm_device
*dev
)
2226 * No explicit RPCS request is needed to ensure full
2227 * slice/subslice/EU enablement prior to Gen9.
2229 if (INTEL_INFO(dev
)->gen
< 9)
2233 * Starting in Gen9, render power gating can leave
2234 * slice/subslice/EU in a partially enabled state. We
2235 * must make an explicit request through RPCS for full
2238 if (INTEL_INFO(dev
)->has_slice_pg
) {
2239 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2240 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2241 GEN8_RPCS_S_CNT_SHIFT
;
2242 rpcs
|= GEN8_RPCS_ENABLE
;
2245 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2246 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2247 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2248 GEN8_RPCS_SS_CNT_SHIFT
;
2249 rpcs
|= GEN8_RPCS_ENABLE
;
2252 if (INTEL_INFO(dev
)->has_eu_pg
) {
2253 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2254 GEN8_RPCS_EU_MIN_SHIFT
;
2255 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2256 GEN8_RPCS_EU_MAX_SHIFT
;
2257 rpcs
|= GEN8_RPCS_ENABLE
;
2263 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2265 u32 indirect_ctx_offset
;
2267 switch (INTEL_INFO(engine
->dev
)->gen
) {
2269 MISSING_CASE(INTEL_INFO(engine
->dev
)->gen
);
2272 indirect_ctx_offset
=
2273 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2276 indirect_ctx_offset
=
2277 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2281 return indirect_ctx_offset
;
2285 populate_lr_context(struct intel_context
*ctx
,
2286 struct drm_i915_gem_object
*ctx_obj
,
2287 struct intel_engine_cs
*engine
,
2288 struct intel_ringbuffer
*ringbuf
)
2290 struct drm_device
*dev
= engine
->dev
;
2291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2292 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2298 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2300 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2302 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2306 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2307 if (IS_ERR(vaddr
)) {
2308 ret
= PTR_ERR(vaddr
);
2309 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2312 ctx_obj
->dirty
= true;
2314 /* The second page of the context object contains some fields which must
2315 * be set up prior to the first execution. */
2316 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2318 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2319 * commands followed by (reg, value) pairs. The values we are setting here are
2320 * only for the first context restore: on a subsequent save, the GPU will
2321 * recreate this batchbuffer with new values (including all the missing
2322 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2323 reg_state
[CTX_LRI_HEADER_0
] =
2324 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2325 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2326 RING_CONTEXT_CONTROL(engine
),
2327 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2328 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2329 (HAS_RESOURCE_STREAMER(dev
) ?
2330 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2331 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2333 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2335 /* Ring buffer start address is not known until the buffer is pinned.
2336 * It is written to the context image in execlists_update_context()
2338 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2339 RING_START(engine
->mmio_base
), 0);
2340 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2341 RING_CTL(engine
->mmio_base
),
2342 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2343 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2344 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2345 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2346 RING_BBADDR(engine
->mmio_base
), 0);
2347 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2348 RING_BBSTATE(engine
->mmio_base
),
2350 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2351 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2352 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2353 RING_SBBADDR(engine
->mmio_base
), 0);
2354 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2355 RING_SBBSTATE(engine
->mmio_base
), 0);
2356 if (engine
->id
== RCS
) {
2357 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2358 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2359 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2360 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2361 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2362 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2363 if (engine
->wa_ctx
.obj
) {
2364 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2365 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2367 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2368 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2369 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2371 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2372 intel_lr_indirect_ctx_offset(engine
) << 6;
2374 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2375 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2379 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2380 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2381 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2382 /* PDP values well be assigned later if needed */
2383 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2385 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2387 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2389 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2391 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2393 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2395 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2397 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2400 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2401 /* 64b PPGTT (48bit canonical)
2402 * PDP0_DESCRIPTOR contains the base address to PML4 and
2403 * other PDP Descriptors are ignored.
2405 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2408 * PDP*_DESCRIPTOR contains the base address of space supported.
2409 * With dynamic page allocation, PDPs may not be allocated at
2410 * this point. Point the unallocated PDPs to the scratch page
2412 execlists_update_context_pdps(ppgtt
, reg_state
);
2415 if (engine
->id
== RCS
) {
2416 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2417 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2421 i915_gem_object_unpin_map(ctx_obj
);
2427 * intel_lr_context_free() - free the LRC specific bits of a context
2428 * @ctx: the LR context to free.
2430 * The real context freeing is done in i915_gem_context_free: this only
2431 * takes care of the bits that are LRC related: the per-engine backing
2432 * objects and the logical ringbuffer.
2434 void intel_lr_context_free(struct intel_context
*ctx
)
2438 for (i
= I915_NUM_ENGINES
; --i
>= 0; ) {
2439 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
2440 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2445 if (ctx
== ctx
->i915
->kernel_context
) {
2446 intel_unpin_ringbuffer_obj(ringbuf
);
2447 i915_gem_object_ggtt_unpin(ctx_obj
);
2448 i915_gem_object_unpin_map(ctx_obj
);
2451 WARN_ON(ctx
->engine
[i
].pin_count
);
2452 intel_ringbuffer_free(ringbuf
);
2453 drm_gem_object_unreference(&ctx_obj
->base
);
2458 * intel_lr_context_size() - return the size of the context for an engine
2459 * @ring: which engine to find the context size for
2461 * Each engine may require a different amount of space for a context image,
2462 * so when allocating (or copying) an image, this function can be used to
2463 * find the right size for the specific engine.
2465 * Return: size (in bytes) of an engine-specific context image
2467 * Note: this size includes the HWSP, which is part of the context image
2468 * in LRC mode, but does not include the "shared data page" used with
2469 * GuC submission. The caller should account for this if using the GuC.
2471 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2475 WARN_ON(INTEL_INFO(engine
->dev
)->gen
< 8);
2477 switch (engine
->id
) {
2479 if (INTEL_INFO(engine
->dev
)->gen
>= 9)
2480 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2482 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2488 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2496 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2497 * @ctx: LR context to create.
2498 * @ring: engine to be used with the context.
2500 * This function can be called more than once, with different engines, if we plan
2501 * to use the context with them. The context backing objects and the ringbuffers
2502 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2503 * the creation is a deferred call: it's better to make sure first that we need to use
2504 * a given ring with the context.
2506 * Return: non-zero on error.
2509 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
2510 struct intel_engine_cs
*engine
)
2512 struct drm_device
*dev
= engine
->dev
;
2513 struct drm_i915_gem_object
*ctx_obj
;
2514 uint32_t context_size
;
2515 struct intel_ringbuffer
*ringbuf
;
2518 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2519 WARN_ON(ctx
->engine
[engine
->id
].state
);
2521 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2523 /* One extra page as the sharing data between driver and GuC */
2524 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2526 ctx_obj
= i915_gem_object_create(dev
, context_size
);
2527 if (IS_ERR(ctx_obj
)) {
2528 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2529 return PTR_ERR(ctx_obj
);
2532 ringbuf
= intel_engine_create_ringbuffer(engine
, 4 * PAGE_SIZE
);
2533 if (IS_ERR(ringbuf
)) {
2534 ret
= PTR_ERR(ringbuf
);
2535 goto error_deref_obj
;
2538 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2540 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2544 ctx
->engine
[engine
->id
].ringbuf
= ringbuf
;
2545 ctx
->engine
[engine
->id
].state
= ctx_obj
;
2547 if (ctx
!= ctx
->i915
->kernel_context
&& engine
->init_context
) {
2548 struct drm_i915_gem_request
*req
;
2550 req
= i915_gem_request_alloc(engine
, ctx
);
2553 DRM_ERROR("ring create req: %d\n", ret
);
2557 ret
= engine
->init_context(req
);
2558 i915_add_request_no_flush(req
);
2560 DRM_ERROR("ring init context: %d\n",
2568 intel_ringbuffer_free(ringbuf
);
2570 drm_gem_object_unreference(&ctx_obj
->base
);
2571 ctx
->engine
[engine
->id
].ringbuf
= NULL
;
2572 ctx
->engine
[engine
->id
].state
= NULL
;
2576 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2577 struct intel_context
*ctx
)
2579 struct intel_engine_cs
*engine
;
2581 for_each_engine(engine
, dev_priv
) {
2582 struct drm_i915_gem_object
*ctx_obj
=
2583 ctx
->engine
[engine
->id
].state
;
2584 struct intel_ringbuffer
*ringbuf
=
2585 ctx
->engine
[engine
->id
].ringbuf
;
2587 uint32_t *reg_state
;
2592 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2593 if (WARN_ON(IS_ERR(vaddr
)))
2596 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2597 ctx_obj
->dirty
= true;
2599 reg_state
[CTX_RING_HEAD
+1] = 0;
2600 reg_state
[CTX_RING_TAIL
+1] = 0;
2602 i915_gem_object_unpin_map(ctx_obj
);