2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT
= 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT
, /* Debug only */
224 FAULT_AND_CONTINUE
/* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_ID_WIDTH 21
228 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
229 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
231 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
232 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
234 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
235 struct intel_engine_cs
*engine
);
236 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
237 struct intel_engine_cs
*engine
);
240 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
241 * @dev_priv: i915 device private
242 * @enable_execlists: value of i915.enable_execlists module parameter.
244 * Only certain platforms support Execlists (the prerequisites being
245 * support for Logical Ring Contexts and Aliasing PPGTT or better).
247 * Return: 1 if Execlists is supported and has to be enabled.
249 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
251 /* On platforms with execlist available, vGPU will only
252 * support execlist mode, no ring buffer mode.
254 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
257 if (INTEL_GEN(dev_priv
) >= 9)
260 if (enable_execlists
== 0)
263 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
264 USES_PPGTT(dev_priv
) &&
265 i915
.use_mmio_flip
>= 0)
272 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
274 struct drm_i915_private
*dev_priv
= engine
->i915
;
276 if (IS_GEN8(dev_priv
) || IS_GEN9(dev_priv
))
277 engine
->idle_lite_restore_wa
= ~0;
279 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
280 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) &&
281 (engine
->id
== VCS
|| engine
->id
== VCS2
);
283 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
284 engine
->ctx_desc_template
|= GEN8_CTX_ADDRESSING_MODE(dev_priv
) <<
285 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
286 if (IS_GEN8(dev_priv
))
287 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
288 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
290 /* TODO: WaDisableLiteRestore when we start using semaphore
291 * signalling between Command Streamers */
292 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
294 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
295 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
296 if (engine
->disable_lite_restore_wa
)
297 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
301 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
302 * descriptor for a pinned context
304 * @ctx: Context to work on
305 * @engine: Engine the descriptor will be used with
307 * The context descriptor encodes various attributes of a context,
308 * including its GTT address and some flags. Because it's fairly
309 * expensive to calculate, we'll just do it once and cache the result,
310 * which remains valid until the context is unpinned.
312 * This is what a descriptor looks like, from LSB to MSB:
313 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
314 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
315 * bits 32-52: ctx ID, a globally unique tag
316 * bits 53-54: mbz, reserved for use by hardware
317 * bits 55-63: group ID, currently unused and set to 0
320 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
321 struct intel_engine_cs
*engine
)
323 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
326 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
328 desc
= engine
->ctx_desc_template
; /* bits 0-11 */
329 desc
|= ce
->lrc_vma
->node
.start
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
331 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
336 uint64_t intel_lr_context_descriptor(struct i915_gem_context
*ctx
,
337 struct intel_engine_cs
*engine
)
339 return ctx
->engine
[engine
->id
].lrc_desc
;
342 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
343 struct drm_i915_gem_request
*rq1
)
346 struct intel_engine_cs
*engine
= rq0
->engine
;
347 struct drm_i915_private
*dev_priv
= rq0
->i915
;
351 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
352 rq1
->elsp_submitted
++;
357 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
358 rq0
->elsp_submitted
++;
360 /* You must always write both descriptors in the order below. */
361 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
362 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
364 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
365 /* The context is automatically loaded after the following */
366 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
368 /* ELSP is a wo register, use another nearby reg for posting */
369 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
373 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
375 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
376 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
377 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
378 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
381 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
383 struct intel_engine_cs
*engine
= rq
->engine
;
384 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
385 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
387 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
389 /* True 32b PPGTT with dynamic page allocation: update PDP
390 * registers and point the unallocated PDPs to scratch page.
391 * PML4 is allocated during ppgtt init, so this is not needed
394 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
395 execlists_update_context_pdps(ppgtt
, reg_state
);
398 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
399 struct drm_i915_gem_request
*rq1
)
401 struct drm_i915_private
*dev_priv
= rq0
->i915
;
402 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
404 execlists_update_context(rq0
);
407 execlists_update_context(rq1
);
409 spin_lock_irq(&dev_priv
->uncore
.lock
);
410 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
412 execlists_elsp_write(rq0
, rq1
);
414 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
415 spin_unlock_irq(&dev_priv
->uncore
.lock
);
418 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
420 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
421 struct drm_i915_gem_request
*cursor
, *tmp
;
423 assert_spin_locked(&engine
->execlist_lock
);
426 * If irqs are not active generate a warning as batches that finish
427 * without the irqs may get lost and a GPU Hang may occur.
429 WARN_ON(!intel_irqs_enabled(engine
->i915
));
431 /* Try to read in pairs */
432 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
436 } else if (req0
->ctx
== cursor
->ctx
) {
437 /* Same ctx: ignore first request, as second request
438 * will update tail past first request's workload */
439 cursor
->elsp_submitted
= req0
->elsp_submitted
;
440 list_del(&req0
->execlist_link
);
441 i915_gem_request_unreference(req0
);
445 WARN_ON(req1
->elsp_submitted
);
453 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
455 * WaIdleLiteRestore: make sure we never cause a lite restore
458 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
459 * resubmit the request. See gen8_emit_request() for where we
460 * prepare the padding after the end of the request.
462 struct intel_ringbuffer
*ringbuf
;
464 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
466 req0
->tail
&= ringbuf
->size
- 1;
469 execlists_submit_requests(req0
, req1
);
473 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 ctx_id
)
475 struct drm_i915_gem_request
*head_req
;
477 assert_spin_locked(&engine
->execlist_lock
);
479 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
480 struct drm_i915_gem_request
,
483 if (WARN_ON(!head_req
|| (head_req
->ctx_hw_id
!= ctx_id
)))
486 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
488 if (--head_req
->elsp_submitted
> 0)
491 list_del(&head_req
->execlist_link
);
492 i915_gem_request_unreference(head_req
);
498 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
501 struct drm_i915_private
*dev_priv
= engine
->i915
;
504 read_pointer
%= GEN8_CSB_ENTRIES
;
506 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
508 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
511 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
518 * intel_lrc_irq_handler() - handle Context Switch interrupts
519 * @data: tasklet handler passed in unsigned long
521 * Check the unread Context Status Buffers and manage the submission of new
522 * contexts to the ELSP accordingly.
524 static void intel_lrc_irq_handler(unsigned long data
)
526 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
527 struct drm_i915_private
*dev_priv
= engine
->i915
;
529 unsigned int read_pointer
, write_pointer
;
530 u32 csb
[GEN8_CSB_ENTRIES
][2];
531 unsigned int csb_read
= 0, i
;
532 unsigned int submit_contexts
= 0;
534 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
536 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
538 read_pointer
= engine
->next_context_status_buffer
;
539 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
540 if (read_pointer
> write_pointer
)
541 write_pointer
+= GEN8_CSB_ENTRIES
;
543 while (read_pointer
< write_pointer
) {
544 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
546 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
551 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
553 /* Update the read pointer to the old write pointer. Manual ringbuffer
554 * management ftw </sarcasm> */
555 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
556 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
557 engine
->next_context_status_buffer
<< 8));
559 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
561 spin_lock(&engine
->execlist_lock
);
563 for (i
= 0; i
< csb_read
; i
++) {
564 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
565 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
566 if (execlists_check_remove_request(engine
, csb
[i
][1]))
567 WARN(1, "Lite Restored request removed from queue\n");
569 WARN(1, "Preemption without Lite Restore\n");
572 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
573 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
575 execlists_check_remove_request(engine
, csb
[i
][1]);
578 if (submit_contexts
) {
579 if (!engine
->disable_lite_restore_wa
||
580 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
581 execlists_context_unqueue(engine
);
584 spin_unlock(&engine
->execlist_lock
);
586 if (unlikely(submit_contexts
> 2))
587 DRM_ERROR("More than two context complete events?\n");
590 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
592 struct intel_engine_cs
*engine
= request
->engine
;
593 struct drm_i915_gem_request
*cursor
;
594 int num_elements
= 0;
596 spin_lock_bh(&engine
->execlist_lock
);
598 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
599 if (++num_elements
> 2)
602 if (num_elements
> 2) {
603 struct drm_i915_gem_request
*tail_req
;
605 tail_req
= list_last_entry(&engine
->execlist_queue
,
606 struct drm_i915_gem_request
,
609 if (request
->ctx
== tail_req
->ctx
) {
610 WARN(tail_req
->elsp_submitted
!= 0,
611 "More than 2 already-submitted reqs queued\n");
612 list_del(&tail_req
->execlist_link
);
613 i915_gem_request_unreference(tail_req
);
617 i915_gem_request_reference(request
);
618 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
619 request
->ctx_hw_id
= request
->ctx
->hw_id
;
620 if (num_elements
== 0)
621 execlists_context_unqueue(engine
);
623 spin_unlock_bh(&engine
->execlist_lock
);
626 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
628 struct intel_engine_cs
*engine
= req
->engine
;
629 uint32_t flush_domains
;
633 if (engine
->gpu_caches_dirty
)
634 flush_domains
= I915_GEM_GPU_DOMAINS
;
636 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
640 engine
->gpu_caches_dirty
= false;
644 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
645 struct list_head
*vmas
)
647 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
648 struct i915_vma
*vma
;
649 uint32_t flush_domains
= 0;
650 bool flush_chipset
= false;
653 list_for_each_entry(vma
, vmas
, exec_list
) {
654 struct drm_i915_gem_object
*obj
= vma
->obj
;
656 if (obj
->active
& other_rings
) {
657 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
662 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
663 flush_chipset
|= i915_gem_clflush_object(obj
, false);
665 flush_domains
|= obj
->base
.write_domain
;
668 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
671 /* Unconditionally invalidate gpu caches and ensure that we do flush
672 * any residual writes from the previous batch.
674 return logical_ring_invalidate_all_caches(req
);
677 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
679 struct intel_engine_cs
*engine
= request
->engine
;
680 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
683 /* Flush enough space to reduce the likelihood of waiting after
684 * we start building the request - in which case we will just
685 * have to repeat work.
687 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
690 ret
= execlists_context_deferred_alloc(request
->ctx
, engine
);
695 request
->ringbuf
= ce
->ringbuf
;
697 if (i915
.enable_guc_submission
) {
699 * Check that the GuC has space for the request before
700 * going any further, as the i915_add_request() call
701 * later on mustn't fail ...
703 ret
= i915_guc_wq_check_space(request
);
708 ret
= intel_lr_context_pin(request
->ctx
, engine
);
712 ret
= intel_ring_begin(request
, 0);
716 if (!ce
->initialised
) {
717 ret
= engine
->init_context(request
);
721 ce
->initialised
= true;
724 /* Note that after this point, we have committed to using
725 * this request as it is being used to both track the
726 * state of engine initialisation and liveness of the
727 * golden renderstate above. Think twice before you try
728 * to cancel/unwind this request now.
731 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
735 intel_lr_context_unpin(request
->ctx
, engine
);
740 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
741 * @request: Request to advance the logical ringbuffer of.
743 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
744 * really happens during submission is that the context and current tail will be placed
745 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
746 * point, the tail *inside* the context is updated and the ELSP written to.
749 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
751 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
752 struct intel_engine_cs
*engine
= request
->engine
;
754 intel_logical_ring_advance(ringbuf
);
755 request
->tail
= ringbuf
->tail
;
758 * Here we add two extra NOOPs as padding to avoid
759 * lite restore of a context with HEAD==TAIL.
761 * Caller must reserve WA_TAIL_DWORDS for us!
763 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
764 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
765 intel_logical_ring_advance(ringbuf
);
767 if (intel_engine_stopped(engine
))
770 /* We keep the previous context alive until we retire the following
771 * request. This ensures that any the context object is still pinned
772 * for any residual writes the HW makes into it on the context switch
773 * into the next object following the breadcrumb. Otherwise, we may
774 * retire the context too early.
776 request
->previous_context
= engine
->last_context
;
777 engine
->last_context
= request
->ctx
;
779 if (i915
.enable_guc_submission
)
780 i915_guc_submit(request
);
782 execlists_context_queue(request
);
788 * execlists_submission() - submit a batchbuffer for execution, Execlists style
789 * @params: execbuffer call parameters.
790 * @args: execbuffer call arguments.
791 * @vmas: list of vmas.
793 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
794 * away the submission details of the execbuffer ioctl call.
796 * Return: non-zero if the submission fails.
798 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
799 struct drm_i915_gem_execbuffer2
*args
,
800 struct list_head
*vmas
)
802 struct drm_device
*dev
= params
->dev
;
803 struct intel_engine_cs
*engine
= params
->engine
;
804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
805 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
811 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
812 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
813 switch (instp_mode
) {
814 case I915_EXEC_CONSTANTS_REL_GENERAL
:
815 case I915_EXEC_CONSTANTS_ABSOLUTE
:
816 case I915_EXEC_CONSTANTS_REL_SURFACE
:
817 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
818 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
822 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
823 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
824 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
828 /* The HW changed the meaning on this bit on gen6 */
829 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
833 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
837 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
838 DRM_DEBUG("sol reset is gen7 only\n");
842 ret
= execlists_move_to_gpu(params
->request
, vmas
);
846 if (engine
== &dev_priv
->engine
[RCS
] &&
847 instp_mode
!= dev_priv
->relative_constants_mode
) {
848 ret
= intel_ring_begin(params
->request
, 4);
852 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
853 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
854 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
855 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
856 intel_logical_ring_advance(ringbuf
);
858 dev_priv
->relative_constants_mode
= instp_mode
;
861 exec_start
= params
->batch_obj_vm_offset
+
862 args
->batch_start_offset
;
864 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
868 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
870 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
875 void intel_execlists_cancel_requests(struct intel_engine_cs
*engine
)
877 struct drm_i915_gem_request
*req
, *tmp
;
878 LIST_HEAD(cancel_list
);
880 WARN_ON(!mutex_is_locked(&engine
->i915
->dev
->struct_mutex
));
882 spin_lock_bh(&engine
->execlist_lock
);
883 list_replace_init(&engine
->execlist_queue
, &cancel_list
);
884 spin_unlock_bh(&engine
->execlist_lock
);
886 list_for_each_entry_safe(req
, tmp
, &cancel_list
, execlist_link
) {
887 list_del(&req
->execlist_link
);
888 i915_gem_request_unreference(req
);
892 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
894 struct drm_i915_private
*dev_priv
= engine
->i915
;
897 if (!intel_engine_initialized(engine
))
900 ret
= intel_engine_idle(engine
);
902 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
905 /* TODO: Is this correct with Execlists enabled? */
906 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
907 if (wait_for((I915_READ_MODE(engine
) & MODE_IDLE
) != 0, 1000)) {
908 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
911 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
914 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
916 struct intel_engine_cs
*engine
= req
->engine
;
919 if (!engine
->gpu_caches_dirty
)
922 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
926 engine
->gpu_caches_dirty
= false;
930 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
931 struct intel_engine_cs
*engine
)
933 struct drm_i915_private
*dev_priv
= ctx
->i915
;
934 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
939 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
944 ret
= i915_gem_obj_ggtt_pin(ce
->state
, GEN8_LR_CONTEXT_ALIGN
,
945 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
949 vaddr
= i915_gem_object_pin_map(ce
->state
);
951 ret
= PTR_ERR(vaddr
);
955 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
957 ret
= intel_pin_and_map_ringbuffer_obj(dev_priv
, ce
->ringbuf
);
961 i915_gem_context_reference(ctx
);
962 ce
->lrc_vma
= i915_gem_obj_to_ggtt(ce
->state
);
963 intel_lr_context_descriptor_update(ctx
, engine
);
965 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ce
->ringbuf
->vma
->node
.start
;
966 ce
->lrc_reg_state
= lrc_reg_state
;
967 ce
->state
->dirty
= true;
969 /* Invalidate GuC TLB. */
970 if (i915
.enable_guc_submission
)
971 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
976 i915_gem_object_unpin_map(ce
->state
);
978 i915_gem_object_ggtt_unpin(ce
->state
);
984 void intel_lr_context_unpin(struct i915_gem_context
*ctx
,
985 struct intel_engine_cs
*engine
)
987 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
989 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
990 GEM_BUG_ON(ce
->pin_count
== 0);
995 intel_unpin_ringbuffer_obj(ce
->ringbuf
);
997 i915_gem_object_unpin_map(ce
->state
);
998 i915_gem_object_ggtt_unpin(ce
->state
);
1002 ce
->lrc_reg_state
= NULL
;
1004 i915_gem_context_unreference(ctx
);
1007 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1010 struct intel_engine_cs
*engine
= req
->engine
;
1011 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1012 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
1017 engine
->gpu_caches_dirty
= true;
1018 ret
= logical_ring_flush_all_caches(req
);
1022 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
1026 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1027 for (i
= 0; i
< w
->count
; i
++) {
1028 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1029 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1031 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1033 intel_logical_ring_advance(ringbuf
);
1035 engine
->gpu_caches_dirty
= true;
1036 ret
= logical_ring_flush_all_caches(req
);
1043 #define wa_ctx_emit(batch, index, cmd) \
1045 int __index = (index)++; \
1046 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1049 batch[__index] = (cmd); \
1052 #define wa_ctx_emit_reg(batch, index, reg) \
1053 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1056 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1057 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1058 * but there is a slight complication as this is applied in WA batch where the
1059 * values are only initialized once so we cannot take register value at the
1060 * beginning and reuse it further; hence we save its value to memory, upload a
1061 * constant value with bit21 set and then we restore it back with the saved value.
1062 * To simplify the WA, a constant value is formed by using the default value
1063 * of this register. This shouldn't be a problem because we are only modifying
1064 * it for a short period and this batch in non-premptible. We can ofcourse
1065 * use additional instructions that read the actual value of the register
1066 * at that time and set our bit of interest but it makes the WA complicated.
1068 * This WA is also required for Gen9 so extracting as a function avoids
1071 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1072 uint32_t *const batch
,
1075 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1078 * WaDisableLSQCROPERFforOCL:skl,kbl
1079 * This WA is implemented in skl_init_clock_gating() but since
1080 * this batch updates GEN8_L3SQCREG4 with default value we need to
1081 * set this bit here to retain the WA during flush.
1083 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_E0
) ||
1084 IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_E0
))
1085 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1087 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1088 MI_SRM_LRM_GLOBAL_GTT
));
1089 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1090 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1091 wa_ctx_emit(batch
, index
, 0);
1093 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1094 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1095 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1097 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1098 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1099 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1100 wa_ctx_emit(batch
, index
, 0);
1101 wa_ctx_emit(batch
, index
, 0);
1102 wa_ctx_emit(batch
, index
, 0);
1103 wa_ctx_emit(batch
, index
, 0);
1105 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1106 MI_SRM_LRM_GLOBAL_GTT
));
1107 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1108 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1109 wa_ctx_emit(batch
, index
, 0);
1114 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1116 uint32_t start_alignment
)
1118 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1121 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1123 uint32_t size_alignment
)
1125 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1127 WARN(wa_ctx
->size
% size_alignment
,
1128 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1129 wa_ctx
->size
, size_alignment
);
1134 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1136 * @engine: only applicable for RCS
1137 * @wa_ctx: structure representing wa_ctx
1138 * offset: specifies start of the batch, should be cache-aligned. This is updated
1139 * with the offset value received as input.
1140 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1141 * @batch: page in which WA are loaded
1142 * @offset: This field specifies the start of the batch, it should be
1143 * cache-aligned otherwise it is adjusted accordingly.
1144 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1145 * initialized at the beginning and shared across all contexts but this field
1146 * helps us to have multiple batches at different offsets and select them based
1147 * on a criteria. At the moment this batch always start at the beginning of the page
1148 * and at this point we don't have multiple wa_ctx batch buffers.
1150 * The number of WA applied are not known at the beginning; we use this field
1151 * to return the no of DWORDS written.
1153 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1154 * so it adds NOOPs as padding to make it cacheline aligned.
1155 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1156 * makes a complete batch buffer.
1158 * Return: non-zero if we exceed the PAGE_SIZE limit.
1161 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1162 struct i915_wa_ctx_bb
*wa_ctx
,
1163 uint32_t *const batch
,
1166 uint32_t scratch_addr
;
1167 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1169 /* WaDisableCtxRestoreArbitration:bdw,chv */
1170 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1172 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1173 if (IS_BROADWELL(engine
->i915
)) {
1174 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1180 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1181 /* Actual scratch location is at 128 bytes offset */
1182 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1184 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1185 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1186 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1187 PIPE_CONTROL_CS_STALL
|
1188 PIPE_CONTROL_QW_WRITE
));
1189 wa_ctx_emit(batch
, index
, scratch_addr
);
1190 wa_ctx_emit(batch
, index
, 0);
1191 wa_ctx_emit(batch
, index
, 0);
1192 wa_ctx_emit(batch
, index
, 0);
1194 /* Pad to end of cacheline */
1195 while (index
% CACHELINE_DWORDS
)
1196 wa_ctx_emit(batch
, index
, MI_NOOP
);
1199 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1200 * execution depends on the length specified in terms of cache lines
1201 * in the register CTX_RCS_INDIRECT_CTX
1204 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1208 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1210 * @engine: only applicable for RCS
1211 * @wa_ctx: structure representing wa_ctx
1212 * offset: specifies start of the batch, should be cache-aligned.
1213 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1214 * @batch: page in which WA are loaded
1215 * @offset: This field specifies the start of this batch.
1216 * This batch is started immediately after indirect_ctx batch. Since we ensure
1217 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1219 * The number of DWORDS written are returned using this field.
1221 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1222 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1224 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1225 struct i915_wa_ctx_bb
*wa_ctx
,
1226 uint32_t *const batch
,
1229 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1231 /* WaDisableCtxRestoreArbitration:bdw,chv */
1232 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1234 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1236 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1239 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1240 struct i915_wa_ctx_bb
*wa_ctx
,
1241 uint32_t *const batch
,
1245 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1247 /* WaDisableCtxRestoreArbitration:skl,bxt */
1248 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1249 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1250 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1252 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1253 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1258 /* WaClearSlmSpaceAtContextSwitch:kbl */
1259 /* Actual scratch location is at 128 bytes offset */
1260 if (IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_A0
)) {
1261 uint32_t scratch_addr
1262 = engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1264 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1265 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1266 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1267 PIPE_CONTROL_CS_STALL
|
1268 PIPE_CONTROL_QW_WRITE
));
1269 wa_ctx_emit(batch
, index
, scratch_addr
);
1270 wa_ctx_emit(batch
, index
, 0);
1271 wa_ctx_emit(batch
, index
, 0);
1272 wa_ctx_emit(batch
, index
, 0);
1274 /* Pad to end of cacheline */
1275 while (index
% CACHELINE_DWORDS
)
1276 wa_ctx_emit(batch
, index
, MI_NOOP
);
1278 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1281 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1282 struct i915_wa_ctx_bb
*wa_ctx
,
1283 uint32_t *const batch
,
1286 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1288 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1289 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_B0
) ||
1290 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
)) {
1291 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1292 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1293 wa_ctx_emit(batch
, index
,
1294 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1295 wa_ctx_emit(batch
, index
, MI_NOOP
);
1298 /* WaClearTdlStateAckDirtyBits:bxt */
1299 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_B0
)) {
1300 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1302 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1303 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1305 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1306 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1308 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1309 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1311 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1312 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1313 wa_ctx_emit(batch
, index
, 0x0);
1314 wa_ctx_emit(batch
, index
, MI_NOOP
);
1317 /* WaDisableCtxRestoreArbitration:skl,bxt */
1318 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1319 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1320 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1322 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1324 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1327 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1331 engine
->wa_ctx
.obj
= i915_gem_object_create(engine
->i915
->dev
,
1333 if (IS_ERR(engine
->wa_ctx
.obj
)) {
1334 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1335 ret
= PTR_ERR(engine
->wa_ctx
.obj
);
1336 engine
->wa_ctx
.obj
= NULL
;
1340 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1342 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1344 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1351 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1353 if (engine
->wa_ctx
.obj
) {
1354 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1355 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1356 engine
->wa_ctx
.obj
= NULL
;
1360 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1366 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1368 WARN_ON(engine
->id
!= RCS
);
1370 /* update this when WA for higher Gen are added */
1371 if (INTEL_GEN(engine
->i915
) > 9) {
1372 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1373 INTEL_GEN(engine
->i915
));
1377 /* some WA perform writes to scratch page, ensure it is valid */
1378 if (engine
->scratch
.obj
== NULL
) {
1379 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1383 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1385 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1389 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1390 batch
= kmap_atomic(page
);
1393 if (IS_GEN8(engine
->i915
)) {
1394 ret
= gen8_init_indirectctx_bb(engine
,
1395 &wa_ctx
->indirect_ctx
,
1401 ret
= gen8_init_perctx_bb(engine
,
1407 } else if (IS_GEN9(engine
->i915
)) {
1408 ret
= gen9_init_indirectctx_bb(engine
,
1409 &wa_ctx
->indirect_ctx
,
1415 ret
= gen9_init_perctx_bb(engine
,
1424 kunmap_atomic(batch
);
1426 lrc_destroy_wa_ctx_obj(engine
);
1431 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1433 struct drm_i915_private
*dev_priv
= engine
->i915
;
1435 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1436 (u32
)engine
->status_page
.gfx_addr
);
1437 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1440 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1442 struct drm_i915_private
*dev_priv
= engine
->i915
;
1443 unsigned int next_context_status_buffer_hw
;
1445 lrc_init_hws(engine
);
1447 I915_WRITE_IMR(engine
,
1448 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1449 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1451 I915_WRITE(RING_MODE_GEN7(engine
),
1452 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1453 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1454 POSTING_READ(RING_MODE_GEN7(engine
));
1457 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1458 * zero, we need to read the write pointer from hardware and use its
1459 * value because "this register is power context save restored".
1460 * Effectively, these states have been observed:
1462 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1463 * BDW | CSB regs not reset | CSB regs reset |
1464 * CHT | CSB regs not reset | CSB regs not reset |
1468 next_context_status_buffer_hw
=
1469 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1472 * When the CSB registers are reset (also after power-up / gpu reset),
1473 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1474 * this special case, so the first element read is CSB[0].
1476 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1477 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1479 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1480 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1482 intel_engine_init_hangcheck(engine
);
1484 return intel_mocs_init_engine(engine
);
1487 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1489 struct drm_i915_private
*dev_priv
= engine
->i915
;
1492 ret
= gen8_init_common_ring(engine
);
1496 /* We need to disable the AsyncFlip performance optimisations in order
1497 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1498 * programmed to '1' on all products.
1500 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1502 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1504 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1506 return init_workarounds_ring(engine
);
1509 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1513 ret
= gen8_init_common_ring(engine
);
1517 return init_workarounds_ring(engine
);
1520 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1522 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1523 struct intel_engine_cs
*engine
= req
->engine
;
1524 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1525 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1528 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1532 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1533 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1534 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1536 intel_logical_ring_emit_reg(ringbuf
,
1537 GEN8_RING_PDP_UDW(engine
, i
));
1538 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1539 intel_logical_ring_emit_reg(ringbuf
,
1540 GEN8_RING_PDP_LDW(engine
, i
));
1541 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1544 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1545 intel_logical_ring_advance(ringbuf
);
1550 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1551 u64 offset
, unsigned dispatch_flags
)
1553 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1554 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1557 /* Don't rely in hw updating PDPs, specially in lite-restore.
1558 * Ideally, we should set Force PD Restore in ctx descriptor,
1559 * but we can't. Force Restore would be a second option, but
1560 * it is unsafe in case of lite-restore (because the ctx is
1561 * not idle). PML4 is allocated during ppgtt init so this is
1562 * not needed in 48-bit.*/
1563 if (req
->ctx
->ppgtt
&&
1564 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1565 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1566 !intel_vgpu_active(req
->i915
)) {
1567 ret
= intel_logical_ring_emit_pdps(req
);
1572 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1575 ret
= intel_ring_begin(req
, 4);
1579 /* FIXME(BDW): Address space and security selectors. */
1580 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1582 (dispatch_flags
& I915_DISPATCH_RS
?
1583 MI_BATCH_RESOURCE_STREAMER
: 0));
1584 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1585 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1586 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1587 intel_logical_ring_advance(ringbuf
);
1592 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*engine
)
1594 struct drm_i915_private
*dev_priv
= engine
->i915
;
1595 unsigned long flags
;
1597 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1600 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1601 if (engine
->irq_refcount
++ == 0) {
1602 I915_WRITE_IMR(engine
,
1603 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1604 POSTING_READ(RING_IMR(engine
->mmio_base
));
1606 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1611 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*engine
)
1613 struct drm_i915_private
*dev_priv
= engine
->i915
;
1614 unsigned long flags
;
1616 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1617 if (--engine
->irq_refcount
== 0) {
1618 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1619 POSTING_READ(RING_IMR(engine
->mmio_base
));
1621 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1624 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1625 u32 invalidate_domains
,
1628 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1629 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1630 struct drm_i915_private
*dev_priv
= request
->i915
;
1634 ret
= intel_ring_begin(request
, 4);
1638 cmd
= MI_FLUSH_DW
+ 1;
1640 /* We always require a command barrier so that subsequent
1641 * commands, such as breadcrumb interrupts, are strictly ordered
1642 * wrt the contents of the write cache being flushed to memory
1643 * (and thus being coherent from the CPU).
1645 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1647 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1648 cmd
|= MI_INVALIDATE_TLB
;
1649 if (engine
== &dev_priv
->engine
[VCS
])
1650 cmd
|= MI_INVALIDATE_BSD
;
1653 intel_logical_ring_emit(ringbuf
, cmd
);
1654 intel_logical_ring_emit(ringbuf
,
1655 I915_GEM_HWS_SCRATCH_ADDR
|
1656 MI_FLUSH_DW_USE_GTT
);
1657 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1658 intel_logical_ring_emit(ringbuf
, 0); /* value */
1659 intel_logical_ring_advance(ringbuf
);
1664 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1665 u32 invalidate_domains
,
1668 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1669 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1670 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1671 bool vf_flush_wa
= false, dc_flush_wa
= false;
1676 flags
|= PIPE_CONTROL_CS_STALL
;
1678 if (flush_domains
) {
1679 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1680 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1681 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1682 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1685 if (invalidate_domains
) {
1686 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1687 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1688 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1689 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1690 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1691 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1692 flags
|= PIPE_CONTROL_QW_WRITE
;
1693 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1696 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1699 if (IS_GEN9(request
->i915
))
1702 /* WaForGAMHang:kbl */
1703 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1715 ret
= intel_ring_begin(request
, len
);
1720 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1721 intel_logical_ring_emit(ringbuf
, 0);
1722 intel_logical_ring_emit(ringbuf
, 0);
1723 intel_logical_ring_emit(ringbuf
, 0);
1724 intel_logical_ring_emit(ringbuf
, 0);
1725 intel_logical_ring_emit(ringbuf
, 0);
1729 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1730 intel_logical_ring_emit(ringbuf
, PIPE_CONTROL_DC_FLUSH_ENABLE
);
1731 intel_logical_ring_emit(ringbuf
, 0);
1732 intel_logical_ring_emit(ringbuf
, 0);
1733 intel_logical_ring_emit(ringbuf
, 0);
1734 intel_logical_ring_emit(ringbuf
, 0);
1737 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1738 intel_logical_ring_emit(ringbuf
, flags
);
1739 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1740 intel_logical_ring_emit(ringbuf
, 0);
1741 intel_logical_ring_emit(ringbuf
, 0);
1742 intel_logical_ring_emit(ringbuf
, 0);
1745 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1746 intel_logical_ring_emit(ringbuf
, PIPE_CONTROL_CS_STALL
);
1747 intel_logical_ring_emit(ringbuf
, 0);
1748 intel_logical_ring_emit(ringbuf
, 0);
1749 intel_logical_ring_emit(ringbuf
, 0);
1750 intel_logical_ring_emit(ringbuf
, 0);
1753 intel_logical_ring_advance(ringbuf
);
1758 static u32
gen8_get_seqno(struct intel_engine_cs
*engine
)
1760 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1763 static void gen8_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1765 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1768 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1771 * On BXT A steppings there is a HW coherency issue whereby the
1772 * MI_STORE_DATA_IMM storing the completed request's seqno
1773 * occasionally doesn't invalidate the CPU cache. Work around this by
1774 * clflushing the corresponding cacheline whenever the caller wants
1775 * the coherency to be guaranteed. Note that this cacheline is known
1776 * to be clean at this point, since we only write it in
1777 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1778 * this clflush in practice becomes an invalidate operation.
1780 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1783 static void bxt_a_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1785 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1787 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1788 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1792 * Reserve space for 2 NOOPs at the end of each request to be
1793 * used as a workaround for not being allowed to do lite
1794 * restore with HEAD==TAIL (WaIdleLiteRestore).
1796 #define WA_TAIL_DWORDS 2
1798 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1800 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1803 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1807 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1808 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1810 intel_logical_ring_emit(ringbuf
,
1811 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1812 intel_logical_ring_emit(ringbuf
,
1813 intel_hws_seqno_address(request
->engine
) |
1814 MI_FLUSH_DW_USE_GTT
);
1815 intel_logical_ring_emit(ringbuf
, 0);
1816 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1817 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1818 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1819 return intel_logical_ring_advance_and_submit(request
);
1822 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1824 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1827 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1831 /* We're using qword write, seqno should be aligned to 8 bytes. */
1832 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1834 /* w/a for post sync ops following a GPGPU operation we
1835 * need a prior CS_STALL, which is emitted by the flush
1836 * following the batch.
1838 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1839 intel_logical_ring_emit(ringbuf
,
1840 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1841 PIPE_CONTROL_CS_STALL
|
1842 PIPE_CONTROL_QW_WRITE
));
1843 intel_logical_ring_emit(ringbuf
,
1844 intel_hws_seqno_address(request
->engine
));
1845 intel_logical_ring_emit(ringbuf
, 0);
1846 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1847 /* We're thrashing one dword of HWS. */
1848 intel_logical_ring_emit(ringbuf
, 0);
1849 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1850 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1851 return intel_logical_ring_advance_and_submit(request
);
1854 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1856 struct render_state so
;
1859 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1863 if (so
.rodata
== NULL
)
1866 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1867 I915_DISPATCH_SECURE
);
1871 ret
= req
->engine
->emit_bb_start(req
,
1872 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1873 I915_DISPATCH_SECURE
);
1877 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1880 i915_gem_render_state_fini(&so
);
1884 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1888 ret
= intel_logical_ring_workarounds_emit(req
);
1892 ret
= intel_rcs_context_init_mocs(req
);
1894 * Failing to program the MOCS is non-fatal.The system will not
1895 * run at peak performance. So generate an error and carry on.
1898 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1900 return intel_lr_context_render_state_init(req
);
1904 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1906 * @engine: Engine Command Streamer.
1909 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1911 struct drm_i915_private
*dev_priv
;
1913 if (!intel_engine_initialized(engine
))
1917 * Tasklet cannot be active at this point due intel_mark_active/idle
1918 * so this is just for documentation.
1920 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1921 tasklet_kill(&engine
->irq_tasklet
);
1923 dev_priv
= engine
->i915
;
1925 if (engine
->buffer
) {
1926 intel_logical_ring_stop(engine
);
1927 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1930 if (engine
->cleanup
)
1931 engine
->cleanup(engine
);
1933 i915_cmd_parser_fini_ring(engine
);
1934 i915_gem_batch_pool_fini(&engine
->batch_pool
);
1936 if (engine
->status_page
.obj
) {
1937 i915_gem_object_unpin_map(engine
->status_page
.obj
);
1938 engine
->status_page
.obj
= NULL
;
1940 intel_lr_context_unpin(dev_priv
->kernel_context
, engine
);
1942 engine
->idle_lite_restore_wa
= 0;
1943 engine
->disable_lite_restore_wa
= false;
1944 engine
->ctx_desc_template
= 0;
1946 lrc_destroy_wa_ctx_obj(engine
);
1947 engine
->i915
= NULL
;
1951 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1953 /* Default vfuncs which can be overriden by each engine. */
1954 engine
->init_hw
= gen8_init_common_ring
;
1955 engine
->emit_request
= gen8_emit_request
;
1956 engine
->emit_flush
= gen8_emit_flush
;
1957 engine
->irq_get
= gen8_logical_ring_get_irq
;
1958 engine
->irq_put
= gen8_logical_ring_put_irq
;
1959 engine
->emit_bb_start
= gen8_emit_bb_start
;
1960 engine
->get_seqno
= gen8_get_seqno
;
1961 engine
->set_seqno
= gen8_set_seqno
;
1962 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
)) {
1963 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1964 engine
->set_seqno
= bxt_a_set_seqno
;
1969 logical_ring_default_irqs(struct intel_engine_cs
*engine
, unsigned shift
)
1971 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1972 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1973 init_waitqueue_head(&engine
->irq_queue
);
1977 lrc_setup_hws(struct intel_engine_cs
*engine
,
1978 struct drm_i915_gem_object
*dctx_obj
)
1982 /* The HWSP is part of the default context object in LRC mode. */
1983 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
) +
1984 LRC_PPHWSP_PN
* PAGE_SIZE
;
1985 hws
= i915_gem_object_pin_map(dctx_obj
);
1987 return PTR_ERR(hws
);
1988 engine
->status_page
.page_addr
= hws
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
1989 engine
->status_page
.obj
= dctx_obj
;
1994 static const struct logical_ring_info
{
2000 } logical_rings
[] = {
2002 .name
= "render ring",
2003 .exec_id
= I915_EXEC_RENDER
,
2004 .guc_id
= GUC_RENDER_ENGINE
,
2005 .mmio_base
= RENDER_RING_BASE
,
2006 .irq_shift
= GEN8_RCS_IRQ_SHIFT
,
2009 .name
= "blitter ring",
2010 .exec_id
= I915_EXEC_BLT
,
2011 .guc_id
= GUC_BLITTER_ENGINE
,
2012 .mmio_base
= BLT_RING_BASE
,
2013 .irq_shift
= GEN8_BCS_IRQ_SHIFT
,
2017 .exec_id
= I915_EXEC_BSD
,
2018 .guc_id
= GUC_VIDEO_ENGINE
,
2019 .mmio_base
= GEN6_BSD_RING_BASE
,
2020 .irq_shift
= GEN8_VCS1_IRQ_SHIFT
,
2023 .name
= "bsd2 ring",
2024 .exec_id
= I915_EXEC_BSD
,
2025 .guc_id
= GUC_VIDEO_ENGINE2
,
2026 .mmio_base
= GEN8_BSD2_RING_BASE
,
2027 .irq_shift
= GEN8_VCS2_IRQ_SHIFT
,
2030 .name
= "video enhancement ring",
2031 .exec_id
= I915_EXEC_VEBOX
,
2032 .guc_id
= GUC_VIDEOENHANCE_ENGINE
,
2033 .mmio_base
= VEBOX_RING_BASE
,
2034 .irq_shift
= GEN8_VECS_IRQ_SHIFT
,
2038 static struct intel_engine_cs
*
2039 logical_ring_setup(struct drm_device
*dev
, enum intel_engine_id id
)
2041 const struct logical_ring_info
*info
= &logical_rings
[id
];
2042 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2043 struct intel_engine_cs
*engine
= &dev_priv
->engine
[id
];
2044 enum forcewake_domains fw_domains
;
2047 engine
->name
= info
->name
;
2048 engine
->exec_id
= info
->exec_id
;
2049 engine
->guc_id
= info
->guc_id
;
2050 engine
->mmio_base
= info
->mmio_base
;
2052 engine
->i915
= dev_priv
;
2054 /* Intentionally left blank. */
2055 engine
->buffer
= NULL
;
2057 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
2061 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2062 RING_CONTEXT_STATUS_PTR(engine
),
2063 FW_REG_READ
| FW_REG_WRITE
);
2065 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2066 RING_CONTEXT_STATUS_BUF_BASE(engine
),
2069 engine
->fw_domains
= fw_domains
;
2071 INIT_LIST_HEAD(&engine
->active_list
);
2072 INIT_LIST_HEAD(&engine
->request_list
);
2073 INIT_LIST_HEAD(&engine
->buffers
);
2074 INIT_LIST_HEAD(&engine
->execlist_queue
);
2075 spin_lock_init(&engine
->execlist_lock
);
2077 tasklet_init(&engine
->irq_tasklet
,
2078 intel_lrc_irq_handler
, (unsigned long)engine
);
2080 logical_ring_init_platform_invariants(engine
);
2081 logical_ring_default_vfuncs(engine
);
2082 logical_ring_default_irqs(engine
, info
->irq_shift
);
2084 intel_engine_init_hangcheck(engine
);
2085 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2091 logical_ring_init(struct intel_engine_cs
*engine
)
2093 struct i915_gem_context
*dctx
= engine
->i915
->kernel_context
;
2096 ret
= i915_cmd_parser_init_ring(engine
);
2100 ret
= execlists_context_deferred_alloc(dctx
, engine
);
2104 /* As this is the default context, always pin it */
2105 ret
= intel_lr_context_pin(dctx
, engine
);
2107 DRM_ERROR("Failed to pin context for %s: %d\n",
2112 /* And setup the hardware status page. */
2113 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
2115 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
2122 intel_logical_ring_cleanup(engine
);
2126 static int logical_render_ring_init(struct drm_device
*dev
)
2128 struct intel_engine_cs
*engine
= logical_ring_setup(dev
, RCS
);
2131 if (HAS_L3_DPF(dev
))
2132 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2134 /* Override some for render ring. */
2135 if (INTEL_INFO(dev
)->gen
>= 9)
2136 engine
->init_hw
= gen9_init_render_ring
;
2138 engine
->init_hw
= gen8_init_render_ring
;
2139 engine
->init_context
= gen8_init_rcs_context
;
2140 engine
->cleanup
= intel_fini_pipe_control
;
2141 engine
->emit_flush
= gen8_emit_flush_render
;
2142 engine
->emit_request
= gen8_emit_request_render
;
2144 ret
= intel_init_pipe_control(engine
);
2148 ret
= intel_init_workaround_bb(engine
);
2151 * We continue even if we fail to initialize WA batch
2152 * because we only expect rare glitches but nothing
2153 * critical to prevent us from using GPU
2155 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2159 ret
= logical_ring_init(engine
);
2161 lrc_destroy_wa_ctx_obj(engine
);
2167 static int logical_bsd_ring_init(struct drm_device
*dev
)
2169 struct intel_engine_cs
*engine
= logical_ring_setup(dev
, VCS
);
2171 return logical_ring_init(engine
);
2174 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2176 struct intel_engine_cs
*engine
= logical_ring_setup(dev
, VCS2
);
2178 return logical_ring_init(engine
);
2181 static int logical_blt_ring_init(struct drm_device
*dev
)
2183 struct intel_engine_cs
*engine
= logical_ring_setup(dev
, BCS
);
2185 return logical_ring_init(engine
);
2188 static int logical_vebox_ring_init(struct drm_device
*dev
)
2190 struct intel_engine_cs
*engine
= logical_ring_setup(dev
, VECS
);
2192 return logical_ring_init(engine
);
2196 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2199 * This function inits the engines for an Execlists submission style (the equivalent in the
2200 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2201 * those engines that are present in the hardware.
2203 * Return: non-zero if the initialization failed.
2205 int intel_logical_rings_init(struct drm_device
*dev
)
2207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2210 ret
= logical_render_ring_init(dev
);
2215 ret
= logical_bsd_ring_init(dev
);
2217 goto cleanup_render_ring
;
2221 ret
= logical_blt_ring_init(dev
);
2223 goto cleanup_bsd_ring
;
2226 if (HAS_VEBOX(dev
)) {
2227 ret
= logical_vebox_ring_init(dev
);
2229 goto cleanup_blt_ring
;
2232 if (HAS_BSD2(dev
)) {
2233 ret
= logical_bsd2_ring_init(dev
);
2235 goto cleanup_vebox_ring
;
2241 intel_logical_ring_cleanup(&dev_priv
->engine
[VECS
]);
2243 intel_logical_ring_cleanup(&dev_priv
->engine
[BCS
]);
2245 intel_logical_ring_cleanup(&dev_priv
->engine
[VCS
]);
2246 cleanup_render_ring
:
2247 intel_logical_ring_cleanup(&dev_priv
->engine
[RCS
]);
2253 make_rpcs(struct drm_i915_private
*dev_priv
)
2258 * No explicit RPCS request is needed to ensure full
2259 * slice/subslice/EU enablement prior to Gen9.
2261 if (INTEL_GEN(dev_priv
) < 9)
2265 * Starting in Gen9, render power gating can leave
2266 * slice/subslice/EU in a partially enabled state. We
2267 * must make an explicit request through RPCS for full
2270 if (INTEL_INFO(dev_priv
)->has_slice_pg
) {
2271 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2272 rpcs
|= INTEL_INFO(dev_priv
)->slice_total
<<
2273 GEN8_RPCS_S_CNT_SHIFT
;
2274 rpcs
|= GEN8_RPCS_ENABLE
;
2277 if (INTEL_INFO(dev_priv
)->has_subslice_pg
) {
2278 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2279 rpcs
|= INTEL_INFO(dev_priv
)->subslice_per_slice
<<
2280 GEN8_RPCS_SS_CNT_SHIFT
;
2281 rpcs
|= GEN8_RPCS_ENABLE
;
2284 if (INTEL_INFO(dev_priv
)->has_eu_pg
) {
2285 rpcs
|= INTEL_INFO(dev_priv
)->eu_per_subslice
<<
2286 GEN8_RPCS_EU_MIN_SHIFT
;
2287 rpcs
|= INTEL_INFO(dev_priv
)->eu_per_subslice
<<
2288 GEN8_RPCS_EU_MAX_SHIFT
;
2289 rpcs
|= GEN8_RPCS_ENABLE
;
2295 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2297 u32 indirect_ctx_offset
;
2299 switch (INTEL_GEN(engine
->i915
)) {
2301 MISSING_CASE(INTEL_GEN(engine
->i915
));
2304 indirect_ctx_offset
=
2305 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2308 indirect_ctx_offset
=
2309 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2313 return indirect_ctx_offset
;
2317 populate_lr_context(struct i915_gem_context
*ctx
,
2318 struct drm_i915_gem_object
*ctx_obj
,
2319 struct intel_engine_cs
*engine
,
2320 struct intel_ringbuffer
*ringbuf
)
2322 struct drm_i915_private
*dev_priv
= ctx
->i915
;
2323 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2329 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2331 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2333 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2337 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2338 if (IS_ERR(vaddr
)) {
2339 ret
= PTR_ERR(vaddr
);
2340 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2343 ctx_obj
->dirty
= true;
2345 /* The second page of the context object contains some fields which must
2346 * be set up prior to the first execution. */
2347 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2349 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2350 * commands followed by (reg, value) pairs. The values we are setting here are
2351 * only for the first context restore: on a subsequent save, the GPU will
2352 * recreate this batchbuffer with new values (including all the missing
2353 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2354 reg_state
[CTX_LRI_HEADER_0
] =
2355 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2356 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2357 RING_CONTEXT_CONTROL(engine
),
2358 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2359 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2360 (HAS_RESOURCE_STREAMER(dev_priv
) ?
2361 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2362 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2364 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2366 /* Ring buffer start address is not known until the buffer is pinned.
2367 * It is written to the context image in execlists_update_context()
2369 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2370 RING_START(engine
->mmio_base
), 0);
2371 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2372 RING_CTL(engine
->mmio_base
),
2373 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2374 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2375 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2376 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2377 RING_BBADDR(engine
->mmio_base
), 0);
2378 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2379 RING_BBSTATE(engine
->mmio_base
),
2381 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2382 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2383 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2384 RING_SBBADDR(engine
->mmio_base
), 0);
2385 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2386 RING_SBBSTATE(engine
->mmio_base
), 0);
2387 if (engine
->id
== RCS
) {
2388 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2389 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2390 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2391 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2392 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2393 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2394 if (engine
->wa_ctx
.obj
) {
2395 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2396 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2398 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2399 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2400 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2402 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2403 intel_lr_indirect_ctx_offset(engine
) << 6;
2405 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2406 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2410 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2411 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2412 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2413 /* PDP values well be assigned later if needed */
2414 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2416 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2418 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2420 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2422 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2424 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2426 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2428 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2431 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2432 /* 64b PPGTT (48bit canonical)
2433 * PDP0_DESCRIPTOR contains the base address to PML4 and
2434 * other PDP Descriptors are ignored.
2436 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2439 * PDP*_DESCRIPTOR contains the base address of space supported.
2440 * With dynamic page allocation, PDPs may not be allocated at
2441 * this point. Point the unallocated PDPs to the scratch page
2443 execlists_update_context_pdps(ppgtt
, reg_state
);
2446 if (engine
->id
== RCS
) {
2447 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2448 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2449 make_rpcs(dev_priv
));
2452 i915_gem_object_unpin_map(ctx_obj
);
2458 * intel_lr_context_size() - return the size of the context for an engine
2459 * @engine: which engine to find the context size for
2461 * Each engine may require a different amount of space for a context image,
2462 * so when allocating (or copying) an image, this function can be used to
2463 * find the right size for the specific engine.
2465 * Return: size (in bytes) of an engine-specific context image
2467 * Note: this size includes the HWSP, which is part of the context image
2468 * in LRC mode, but does not include the "shared data page" used with
2469 * GuC submission. The caller should account for this if using the GuC.
2471 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2475 WARN_ON(INTEL_GEN(engine
->i915
) < 8);
2477 switch (engine
->id
) {
2479 if (INTEL_GEN(engine
->i915
) >= 9)
2480 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2482 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2488 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2496 * execlists_context_deferred_alloc() - create the LRC specific bits of a context
2497 * @ctx: LR context to create.
2498 * @engine: engine to be used with the context.
2500 * This function can be called more than once, with different engines, if we plan
2501 * to use the context with them. The context backing objects and the ringbuffers
2502 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2503 * the creation is a deferred call: it's better to make sure first that we need to use
2504 * a given ring with the context.
2506 * Return: non-zero on error.
2508 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
2509 struct intel_engine_cs
*engine
)
2511 struct drm_i915_gem_object
*ctx_obj
;
2512 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2513 uint32_t context_size
;
2514 struct intel_ringbuffer
*ringbuf
;
2519 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2521 /* One extra page as the sharing data between driver and GuC */
2522 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2524 ctx_obj
= i915_gem_object_create(ctx
->i915
->dev
, context_size
);
2525 if (IS_ERR(ctx_obj
)) {
2526 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2527 return PTR_ERR(ctx_obj
);
2530 ringbuf
= intel_engine_create_ringbuffer(engine
, 4 * PAGE_SIZE
);
2531 if (IS_ERR(ringbuf
)) {
2532 ret
= PTR_ERR(ringbuf
);
2533 goto error_deref_obj
;
2536 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2538 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2542 ce
->ringbuf
= ringbuf
;
2543 ce
->state
= ctx_obj
;
2544 ce
->initialised
= engine
->init_context
== NULL
;
2549 intel_ringbuffer_free(ringbuf
);
2551 drm_gem_object_unreference(&ctx_obj
->base
);
2557 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2558 struct i915_gem_context
*ctx
)
2560 struct intel_engine_cs
*engine
;
2562 for_each_engine(engine
, dev_priv
) {
2563 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2564 struct drm_i915_gem_object
*ctx_obj
= ce
->state
;
2566 uint32_t *reg_state
;
2571 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2572 if (WARN_ON(IS_ERR(vaddr
)))
2575 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2576 ctx_obj
->dirty
= true;
2578 reg_state
[CTX_RING_HEAD
+1] = 0;
2579 reg_state
[CTX_RING_TAIL
+1] = 0;
2581 i915_gem_object_unpin_map(ctx_obj
);
2583 ce
->ringbuf
->head
= 0;
2584 ce
->ringbuf
->tail
= 0;