2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
212 FAULT_AND_HALT
, /* Debug only */
214 FAULT_AND_CONTINUE
/* Unsupported */
216 #define GEN8_CTX_ID_SHIFT 32
217 #define GEN8_CTX_ID_WIDTH 21
218 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
219 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
221 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
222 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
224 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
225 struct intel_engine_cs
*engine
);
226 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
227 struct intel_engine_cs
*engine
);
230 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
231 * @dev_priv: i915 device private
232 * @enable_execlists: value of i915.enable_execlists module parameter.
234 * Only certain platforms support Execlists (the prerequisites being
235 * support for Logical Ring Contexts and Aliasing PPGTT or better).
237 * Return: 1 if Execlists is supported and has to be enabled.
239 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
241 /* On platforms with execlist available, vGPU will only
242 * support execlist mode, no ring buffer mode.
244 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
247 if (INTEL_GEN(dev_priv
) >= 9)
250 if (enable_execlists
== 0)
253 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
254 USES_PPGTT(dev_priv
) &&
255 i915
.use_mmio_flip
>= 0)
262 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
264 struct drm_i915_private
*dev_priv
= engine
->i915
;
266 if (IS_GEN8(dev_priv
) || IS_GEN9(dev_priv
))
267 engine
->idle_lite_restore_wa
= ~0;
269 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
270 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) &&
271 (engine
->id
== VCS
|| engine
->id
== VCS2
);
273 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
274 if (IS_GEN8(dev_priv
))
275 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
276 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
278 /* TODO: WaDisableLiteRestore when we start using semaphore
279 * signalling between Command Streamers */
280 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
282 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
283 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
284 if (engine
->disable_lite_restore_wa
)
285 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
289 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
290 * descriptor for a pinned context
291 * @ctx: Context to work on
292 * @engine: Engine the descriptor will be used with
294 * The context descriptor encodes various attributes of a context,
295 * including its GTT address and some flags. Because it's fairly
296 * expensive to calculate, we'll just do it once and cache the result,
297 * which remains valid until the context is unpinned.
299 * This is what a descriptor looks like, from LSB to MSB::
301 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
302 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
303 * bits 32-52: ctx ID, a globally unique tag
304 * bits 53-54: mbz, reserved for use by hardware
305 * bits 55-63: group ID, currently unused and set to 0
308 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
309 struct intel_engine_cs
*engine
)
311 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
314 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
316 desc
= ctx
->desc_template
; /* bits 3-4 */
317 desc
|= engine
->ctx_desc_template
; /* bits 0-11 */
318 desc
|= i915_ggtt_offset(ce
->state
) + LRC_PPHWSP_PN
* PAGE_SIZE
;
320 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
325 uint64_t intel_lr_context_descriptor(struct i915_gem_context
*ctx
,
326 struct intel_engine_cs
*engine
)
328 return ctx
->engine
[engine
->id
].lrc_desc
;
331 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
332 struct drm_i915_gem_request
*rq1
)
335 struct intel_engine_cs
*engine
= rq0
->engine
;
336 struct drm_i915_private
*dev_priv
= rq0
->i915
;
340 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
341 rq1
->elsp_submitted
++;
346 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
347 rq0
->elsp_submitted
++;
349 /* You must always write both descriptors in the order below. */
350 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
351 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
353 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
354 /* The context is automatically loaded after the following */
355 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
357 /* ELSP is a wo register, use another nearby reg for posting */
358 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
362 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
364 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
365 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
366 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
367 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
370 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
372 struct intel_engine_cs
*engine
= rq
->engine
;
373 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
374 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
376 reg_state
[CTX_RING_TAIL
+1] = intel_ring_offset(rq
->ring
, rq
->tail
);
378 /* True 32b PPGTT with dynamic page allocation: update PDP
379 * registers and point the unallocated PDPs to scratch page.
380 * PML4 is allocated during ppgtt init, so this is not needed
383 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
384 execlists_update_context_pdps(ppgtt
, reg_state
);
387 static void execlists_elsp_submit_contexts(struct drm_i915_gem_request
*rq0
,
388 struct drm_i915_gem_request
*rq1
)
390 struct drm_i915_private
*dev_priv
= rq0
->i915
;
391 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
393 execlists_update_context(rq0
);
396 execlists_update_context(rq1
);
398 spin_lock_irq(&dev_priv
->uncore
.lock
);
399 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
401 execlists_elsp_write(rq0
, rq1
);
403 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
404 spin_unlock_irq(&dev_priv
->uncore
.lock
);
407 static inline void execlists_context_status_change(
408 struct drm_i915_gem_request
*rq
,
409 unsigned long status
)
412 * Only used when GVT-g is enabled now. When GVT-g is disabled,
413 * The compiler should eliminate this function as dead-code.
415 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
418 atomic_notifier_call_chain(&rq
->ctx
->status_notifier
, status
, rq
);
421 static void execlists_unqueue(struct intel_engine_cs
*engine
)
423 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
424 struct drm_i915_gem_request
*cursor
, *tmp
;
426 assert_spin_locked(&engine
->execlist_lock
);
429 * If irqs are not active generate a warning as batches that finish
430 * without the irqs may get lost and a GPU Hang may occur.
432 WARN_ON(!intel_irqs_enabled(engine
->i915
));
434 /* Try to read in pairs */
435 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
439 } else if (req0
->ctx
== cursor
->ctx
) {
440 /* Same ctx: ignore first request, as second request
441 * will update tail past first request's workload */
442 cursor
->elsp_submitted
= req0
->elsp_submitted
;
443 list_del(&req0
->execlist_link
);
444 i915_gem_request_put(req0
);
447 if (IS_ENABLED(CONFIG_DRM_I915_GVT
)) {
449 * req0 (after merged) ctx requires single
450 * submission, stop picking
452 if (req0
->ctx
->execlists_force_single_submission
)
455 * req0 ctx doesn't require single submission,
456 * but next req ctx requires, stop picking
458 if (cursor
->ctx
->execlists_force_single_submission
)
462 WARN_ON(req1
->elsp_submitted
);
470 execlists_context_status_change(req0
, INTEL_CONTEXT_SCHEDULE_IN
);
473 execlists_context_status_change(req1
,
474 INTEL_CONTEXT_SCHEDULE_IN
);
476 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
478 * WaIdleLiteRestore: make sure we never cause a lite restore
481 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
482 * resubmit the request. See gen8_emit_request() for where we
483 * prepare the padding after the end of the request.
486 req0
->tail
&= req0
->ring
->size
- 1;
489 execlists_elsp_submit_contexts(req0
, req1
);
493 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 ctx_id
)
495 struct drm_i915_gem_request
*head_req
;
497 assert_spin_locked(&engine
->execlist_lock
);
499 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
500 struct drm_i915_gem_request
,
503 if (WARN_ON(!head_req
|| (head_req
->ctx_hw_id
!= ctx_id
)))
506 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
508 if (--head_req
->elsp_submitted
> 0)
511 execlists_context_status_change(head_req
, INTEL_CONTEXT_SCHEDULE_OUT
);
513 list_del(&head_req
->execlist_link
);
514 i915_gem_request_put(head_req
);
520 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
523 struct drm_i915_private
*dev_priv
= engine
->i915
;
526 read_pointer
%= GEN8_CSB_ENTRIES
;
528 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
530 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
533 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
540 * Check the unread Context Status Buffers and manage the submission of new
541 * contexts to the ELSP accordingly.
543 static void intel_lrc_irq_handler(unsigned long data
)
545 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
546 struct drm_i915_private
*dev_priv
= engine
->i915
;
548 unsigned int read_pointer
, write_pointer
;
549 u32 csb
[GEN8_CSB_ENTRIES
][2];
550 unsigned int csb_read
= 0, i
;
551 unsigned int submit_contexts
= 0;
553 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
555 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
557 read_pointer
= engine
->next_context_status_buffer
;
558 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
559 if (read_pointer
> write_pointer
)
560 write_pointer
+= GEN8_CSB_ENTRIES
;
562 while (read_pointer
< write_pointer
) {
563 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
565 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
570 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
572 /* Update the read pointer to the old write pointer. Manual ringbuffer
573 * management ftw </sarcasm> */
574 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
575 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
576 engine
->next_context_status_buffer
<< 8));
578 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
580 spin_lock(&engine
->execlist_lock
);
582 for (i
= 0; i
< csb_read
; i
++) {
583 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
584 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
585 if (execlists_check_remove_request(engine
, csb
[i
][1]))
586 WARN(1, "Lite Restored request removed from queue\n");
588 WARN(1, "Preemption without Lite Restore\n");
591 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
592 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
594 execlists_check_remove_request(engine
, csb
[i
][1]);
597 if (submit_contexts
) {
598 if (!engine
->disable_lite_restore_wa
||
599 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
600 execlists_unqueue(engine
);
603 spin_unlock(&engine
->execlist_lock
);
605 if (unlikely(submit_contexts
> 2))
606 DRM_ERROR("More than two context complete events?\n");
609 static void execlists_submit_request(struct drm_i915_gem_request
*request
)
611 struct intel_engine_cs
*engine
= request
->engine
;
612 struct drm_i915_gem_request
*cursor
;
613 int num_elements
= 0;
615 spin_lock_bh(&engine
->execlist_lock
);
617 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
618 if (++num_elements
> 2)
621 if (num_elements
> 2) {
622 struct drm_i915_gem_request
*tail_req
;
624 tail_req
= list_last_entry(&engine
->execlist_queue
,
625 struct drm_i915_gem_request
,
628 if (request
->ctx
== tail_req
->ctx
) {
629 WARN(tail_req
->elsp_submitted
!= 0,
630 "More than 2 already-submitted reqs queued\n");
631 list_del(&tail_req
->execlist_link
);
632 i915_gem_request_put(tail_req
);
636 i915_gem_request_get(request
);
637 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
638 request
->ctx_hw_id
= request
->ctx
->hw_id
;
639 if (num_elements
== 0)
640 execlists_unqueue(engine
);
642 spin_unlock_bh(&engine
->execlist_lock
);
645 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
647 struct intel_engine_cs
*engine
= request
->engine
;
648 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
651 /* Flush enough space to reduce the likelihood of waiting after
652 * we start building the request - in which case we will just
653 * have to repeat work.
655 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
658 ret
= execlists_context_deferred_alloc(request
->ctx
, engine
);
663 request
->ring
= ce
->ring
;
665 if (i915
.enable_guc_submission
) {
667 * Check that the GuC has space for the request before
668 * going any further, as the i915_add_request() call
669 * later on mustn't fail ...
671 ret
= i915_guc_wq_check_space(request
);
676 ret
= intel_lr_context_pin(request
->ctx
, engine
);
680 ret
= intel_ring_begin(request
, 0);
684 if (!ce
->initialised
) {
685 ret
= engine
->init_context(request
);
689 ce
->initialised
= true;
692 /* Note that after this point, we have committed to using
693 * this request as it is being used to both track the
694 * state of engine initialisation and liveness of the
695 * golden renderstate above. Think twice before you try
696 * to cancel/unwind this request now.
699 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
703 intel_lr_context_unpin(request
->ctx
, engine
);
708 * intel_logical_ring_advance() - advance the tail and prepare for submission
709 * @request: Request to advance the logical ringbuffer of.
711 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
712 * really happens during submission is that the context and current tail will be placed
713 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
714 * point, the tail *inside* the context is updated and the ELSP written to.
717 intel_logical_ring_advance(struct drm_i915_gem_request
*request
)
719 struct intel_ring
*ring
= request
->ring
;
720 struct intel_engine_cs
*engine
= request
->engine
;
722 intel_ring_advance(ring
);
723 request
->tail
= ring
->tail
;
726 * Here we add two extra NOOPs as padding to avoid
727 * lite restore of a context with HEAD==TAIL.
729 * Caller must reserve WA_TAIL_DWORDS for us!
731 intel_ring_emit(ring
, MI_NOOP
);
732 intel_ring_emit(ring
, MI_NOOP
);
733 intel_ring_advance(ring
);
735 /* We keep the previous context alive until we retire the following
736 * request. This ensures that any the context object is still pinned
737 * for any residual writes the HW makes into it on the context switch
738 * into the next object following the breadcrumb. Otherwise, we may
739 * retire the context too early.
741 request
->previous_context
= engine
->last_context
;
742 engine
->last_context
= request
->ctx
;
746 void intel_execlists_cancel_requests(struct intel_engine_cs
*engine
)
748 struct drm_i915_gem_request
*req
, *tmp
;
749 LIST_HEAD(cancel_list
);
751 WARN_ON(!mutex_is_locked(&engine
->i915
->drm
.struct_mutex
));
753 spin_lock_bh(&engine
->execlist_lock
);
754 list_replace_init(&engine
->execlist_queue
, &cancel_list
);
755 spin_unlock_bh(&engine
->execlist_lock
);
757 list_for_each_entry_safe(req
, tmp
, &cancel_list
, execlist_link
) {
758 list_del(&req
->execlist_link
);
759 i915_gem_request_put(req
);
763 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
764 struct intel_engine_cs
*engine
)
766 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
771 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
776 ret
= i915_vma_pin(ce
->state
, 0, GEN8_LR_CONTEXT_ALIGN
,
777 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
| PIN_GLOBAL
);
781 vaddr
= i915_gem_object_pin_map(ce
->state
->obj
, I915_MAP_WB
);
783 ret
= PTR_ERR(vaddr
);
787 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
789 ret
= intel_ring_pin(ce
->ring
);
793 intel_lr_context_descriptor_update(ctx
, engine
);
795 lrc_reg_state
[CTX_RING_BUFFER_START
+1] =
796 i915_ggtt_offset(ce
->ring
->vma
);
797 ce
->lrc_reg_state
= lrc_reg_state
;
798 ce
->state
->obj
->dirty
= true;
800 /* Invalidate GuC TLB. */
801 if (i915
.enable_guc_submission
) {
802 struct drm_i915_private
*dev_priv
= ctx
->i915
;
803 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
806 i915_gem_context_get(ctx
);
810 i915_gem_object_unpin_map(ce
->state
->obj
);
812 __i915_vma_unpin(ce
->state
);
818 void intel_lr_context_unpin(struct i915_gem_context
*ctx
,
819 struct intel_engine_cs
*engine
)
821 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
823 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
824 GEM_BUG_ON(ce
->pin_count
== 0);
829 intel_ring_unpin(ce
->ring
);
831 i915_gem_object_unpin_map(ce
->state
->obj
);
832 i915_vma_unpin(ce
->state
);
834 i915_gem_context_put(ctx
);
837 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
840 struct intel_ring
*ring
= req
->ring
;
841 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
846 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
850 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
854 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
855 for (i
= 0; i
< w
->count
; i
++) {
856 intel_ring_emit_reg(ring
, w
->reg
[i
].addr
);
857 intel_ring_emit(ring
, w
->reg
[i
].value
);
859 intel_ring_emit(ring
, MI_NOOP
);
861 intel_ring_advance(ring
);
863 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
870 #define wa_ctx_emit(batch, index, cmd) \
872 int __index = (index)++; \
873 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
876 batch[__index] = (cmd); \
879 #define wa_ctx_emit_reg(batch, index, reg) \
880 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
883 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
884 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
885 * but there is a slight complication as this is applied in WA batch where the
886 * values are only initialized once so we cannot take register value at the
887 * beginning and reuse it further; hence we save its value to memory, upload a
888 * constant value with bit21 set and then we restore it back with the saved value.
889 * To simplify the WA, a constant value is formed by using the default value
890 * of this register. This shouldn't be a problem because we are only modifying
891 * it for a short period and this batch in non-premptible. We can ofcourse
892 * use additional instructions that read the actual value of the register
893 * at that time and set our bit of interest but it makes the WA complicated.
895 * This WA is also required for Gen9 so extracting as a function avoids
898 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
902 struct drm_i915_private
*dev_priv
= engine
->i915
;
903 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
906 * WaDisableLSQCROPERFforOCL:skl,kbl
907 * This WA is implemented in skl_init_clock_gating() but since
908 * this batch updates GEN8_L3SQCREG4 with default value we need to
909 * set this bit here to retain the WA during flush.
911 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
) ||
912 IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
913 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
915 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
916 MI_SRM_LRM_GLOBAL_GTT
));
917 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
918 wa_ctx_emit(batch
, index
, i915_ggtt_offset(engine
->scratch
) + 256);
919 wa_ctx_emit(batch
, index
, 0);
921 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
922 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
923 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
925 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
926 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
927 PIPE_CONTROL_DC_FLUSH_ENABLE
));
928 wa_ctx_emit(batch
, index
, 0);
929 wa_ctx_emit(batch
, index
, 0);
930 wa_ctx_emit(batch
, index
, 0);
931 wa_ctx_emit(batch
, index
, 0);
933 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
934 MI_SRM_LRM_GLOBAL_GTT
));
935 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
936 wa_ctx_emit(batch
, index
, i915_ggtt_offset(engine
->scratch
) + 256);
937 wa_ctx_emit(batch
, index
, 0);
942 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
944 uint32_t start_alignment
)
946 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
949 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
951 uint32_t size_alignment
)
953 wa_ctx
->size
= offset
- wa_ctx
->offset
;
955 WARN(wa_ctx
->size
% size_alignment
,
956 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
957 wa_ctx
->size
, size_alignment
);
962 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
963 * initialized at the beginning and shared across all contexts but this field
964 * helps us to have multiple batches at different offsets and select them based
965 * on a criteria. At the moment this batch always start at the beginning of the page
966 * and at this point we don't have multiple wa_ctx batch buffers.
968 * The number of WA applied are not known at the beginning; we use this field
969 * to return the no of DWORDS written.
971 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
972 * so it adds NOOPs as padding to make it cacheline aligned.
973 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
974 * makes a complete batch buffer.
976 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
977 struct i915_wa_ctx_bb
*wa_ctx
,
981 uint32_t scratch_addr
;
982 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
984 /* WaDisableCtxRestoreArbitration:bdw,chv */
985 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
987 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
988 if (IS_BROADWELL(engine
->i915
)) {
989 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
995 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
996 /* Actual scratch location is at 128 bytes offset */
997 scratch_addr
= i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
999 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1000 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1001 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1002 PIPE_CONTROL_CS_STALL
|
1003 PIPE_CONTROL_QW_WRITE
));
1004 wa_ctx_emit(batch
, index
, scratch_addr
);
1005 wa_ctx_emit(batch
, index
, 0);
1006 wa_ctx_emit(batch
, index
, 0);
1007 wa_ctx_emit(batch
, index
, 0);
1009 /* Pad to end of cacheline */
1010 while (index
% CACHELINE_DWORDS
)
1011 wa_ctx_emit(batch
, index
, MI_NOOP
);
1014 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1015 * execution depends on the length specified in terms of cache lines
1016 * in the register CTX_RCS_INDIRECT_CTX
1019 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1023 * This batch is started immediately after indirect_ctx batch. Since we ensure
1024 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1026 * The number of DWORDS written are returned using this field.
1028 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1029 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1031 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1032 struct i915_wa_ctx_bb
*wa_ctx
,
1036 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1038 /* WaDisableCtxRestoreArbitration:bdw,chv */
1039 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1041 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1043 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1046 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1047 struct i915_wa_ctx_bb
*wa_ctx
,
1052 struct drm_i915_private
*dev_priv
= engine
->i915
;
1053 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1055 /* WaDisableCtxRestoreArbitration:skl,bxt */
1056 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_D0
) ||
1057 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1058 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1060 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1061 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1066 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
1067 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1068 wa_ctx_emit_reg(batch
, index
, COMMON_SLICE_CHICKEN2
);
1069 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(
1070 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE
));
1071 wa_ctx_emit(batch
, index
, MI_NOOP
);
1073 /* WaClearSlmSpaceAtContextSwitch:kbl */
1074 /* Actual scratch location is at 128 bytes offset */
1075 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_A0
)) {
1077 i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
1079 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1080 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1081 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1082 PIPE_CONTROL_CS_STALL
|
1083 PIPE_CONTROL_QW_WRITE
));
1084 wa_ctx_emit(batch
, index
, scratch_addr
);
1085 wa_ctx_emit(batch
, index
, 0);
1086 wa_ctx_emit(batch
, index
, 0);
1087 wa_ctx_emit(batch
, index
, 0);
1090 /* WaMediaPoolStateCmdInWABB:bxt */
1091 if (HAS_POOLED_EU(engine
->i915
)) {
1093 * EU pool configuration is setup along with golden context
1094 * during context initialization. This value depends on
1095 * device type (2x6 or 3x6) and needs to be updated based
1096 * on which subslice is disabled especially for 2x6
1097 * devices, however it is safe to load default
1098 * configuration of 3x6 device instead of masking off
1099 * corresponding bits because HW ignores bits of a disabled
1100 * subslice and drops down to appropriate config. Please
1101 * see render_state_setup() in i915_gem_render_state.c for
1102 * possible configurations, to avoid duplication they are
1103 * not shown here again.
1105 u32 eu_pool_config
= 0x00777000;
1106 wa_ctx_emit(batch
, index
, GEN9_MEDIA_POOL_STATE
);
1107 wa_ctx_emit(batch
, index
, GEN9_MEDIA_POOL_ENABLE
);
1108 wa_ctx_emit(batch
, index
, eu_pool_config
);
1109 wa_ctx_emit(batch
, index
, 0);
1110 wa_ctx_emit(batch
, index
, 0);
1111 wa_ctx_emit(batch
, index
, 0);
1114 /* Pad to end of cacheline */
1115 while (index
% CACHELINE_DWORDS
)
1116 wa_ctx_emit(batch
, index
, MI_NOOP
);
1118 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1121 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1122 struct i915_wa_ctx_bb
*wa_ctx
,
1126 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1128 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1129 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_B0
) ||
1130 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
)) {
1131 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1132 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1133 wa_ctx_emit(batch
, index
,
1134 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1135 wa_ctx_emit(batch
, index
, MI_NOOP
);
1138 /* WaClearTdlStateAckDirtyBits:bxt */
1139 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_B0
)) {
1140 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1142 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1143 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1145 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1146 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1148 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1149 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1151 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1152 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1153 wa_ctx_emit(batch
, index
, 0x0);
1154 wa_ctx_emit(batch
, index
, MI_NOOP
);
1157 /* WaDisableCtxRestoreArbitration:skl,bxt */
1158 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1159 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1160 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1162 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1164 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1167 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1169 struct drm_i915_gem_object
*obj
;
1170 struct i915_vma
*vma
;
1173 obj
= i915_gem_object_create(&engine
->i915
->drm
, PAGE_ALIGN(size
));
1175 return PTR_ERR(obj
);
1177 vma
= i915_vma_create(obj
, &engine
->i915
->ggtt
.base
, NULL
);
1183 err
= i915_vma_pin(vma
, 0, PAGE_SIZE
, PIN_GLOBAL
| PIN_HIGH
);
1187 engine
->wa_ctx
.vma
= vma
;
1191 i915_gem_object_put(obj
);
1195 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1197 i915_vma_unpin_and_release(&engine
->wa_ctx
.vma
);
1200 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1202 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1208 WARN_ON(engine
->id
!= RCS
);
1210 /* update this when WA for higher Gen are added */
1211 if (INTEL_GEN(engine
->i915
) > 9) {
1212 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1213 INTEL_GEN(engine
->i915
));
1217 /* some WA perform writes to scratch page, ensure it is valid */
1218 if (!engine
->scratch
) {
1219 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1223 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1225 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1229 page
= i915_gem_object_get_dirty_page(wa_ctx
->vma
->obj
, 0);
1230 batch
= kmap_atomic(page
);
1233 if (IS_GEN8(engine
->i915
)) {
1234 ret
= gen8_init_indirectctx_bb(engine
,
1235 &wa_ctx
->indirect_ctx
,
1241 ret
= gen8_init_perctx_bb(engine
,
1247 } else if (IS_GEN9(engine
->i915
)) {
1248 ret
= gen9_init_indirectctx_bb(engine
,
1249 &wa_ctx
->indirect_ctx
,
1255 ret
= gen9_init_perctx_bb(engine
,
1264 kunmap_atomic(batch
);
1266 lrc_destroy_wa_ctx_obj(engine
);
1271 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1273 struct drm_i915_private
*dev_priv
= engine
->i915
;
1275 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1276 engine
->status_page
.ggtt_offset
);
1277 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1280 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1282 struct drm_i915_private
*dev_priv
= engine
->i915
;
1283 unsigned int next_context_status_buffer_hw
;
1285 lrc_init_hws(engine
);
1287 I915_WRITE_IMR(engine
,
1288 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1289 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1291 I915_WRITE(RING_MODE_GEN7(engine
),
1292 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1293 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1294 POSTING_READ(RING_MODE_GEN7(engine
));
1297 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1298 * zero, we need to read the write pointer from hardware and use its
1299 * value because "this register is power context save restored".
1300 * Effectively, these states have been observed:
1302 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1303 * BDW | CSB regs not reset | CSB regs reset |
1304 * CHT | CSB regs not reset | CSB regs not reset |
1308 next_context_status_buffer_hw
=
1309 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1312 * When the CSB registers are reset (also after power-up / gpu reset),
1313 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1314 * this special case, so the first element read is CSB[0].
1316 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1317 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1319 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1320 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1322 intel_engine_init_hangcheck(engine
);
1324 return intel_mocs_init_engine(engine
);
1327 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1329 struct drm_i915_private
*dev_priv
= engine
->i915
;
1332 ret
= gen8_init_common_ring(engine
);
1336 /* We need to disable the AsyncFlip performance optimisations in order
1337 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1338 * programmed to '1' on all products.
1340 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1342 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1344 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1346 return init_workarounds_ring(engine
);
1349 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1353 ret
= gen8_init_common_ring(engine
);
1357 return init_workarounds_ring(engine
);
1360 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1362 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1363 struct intel_ring
*ring
= req
->ring
;
1364 struct intel_engine_cs
*engine
= req
->engine
;
1365 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1368 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1372 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1373 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1374 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1376 intel_ring_emit_reg(ring
, GEN8_RING_PDP_UDW(engine
, i
));
1377 intel_ring_emit(ring
, upper_32_bits(pd_daddr
));
1378 intel_ring_emit_reg(ring
, GEN8_RING_PDP_LDW(engine
, i
));
1379 intel_ring_emit(ring
, lower_32_bits(pd_daddr
));
1382 intel_ring_emit(ring
, MI_NOOP
);
1383 intel_ring_advance(ring
);
1388 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1389 u64 offset
, u32 len
,
1390 unsigned int dispatch_flags
)
1392 struct intel_ring
*ring
= req
->ring
;
1393 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1396 /* Don't rely in hw updating PDPs, specially in lite-restore.
1397 * Ideally, we should set Force PD Restore in ctx descriptor,
1398 * but we can't. Force Restore would be a second option, but
1399 * it is unsafe in case of lite-restore (because the ctx is
1400 * not idle). PML4 is allocated during ppgtt init so this is
1401 * not needed in 48-bit.*/
1402 if (req
->ctx
->ppgtt
&&
1403 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1404 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1405 !intel_vgpu_active(req
->i915
)) {
1406 ret
= intel_logical_ring_emit_pdps(req
);
1411 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1414 ret
= intel_ring_begin(req
, 4);
1418 /* FIXME(BDW): Address space and security selectors. */
1419 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
|
1421 (dispatch_flags
& I915_DISPATCH_RS
?
1422 MI_BATCH_RESOURCE_STREAMER
: 0));
1423 intel_ring_emit(ring
, lower_32_bits(offset
));
1424 intel_ring_emit(ring
, upper_32_bits(offset
));
1425 intel_ring_emit(ring
, MI_NOOP
);
1426 intel_ring_advance(ring
);
1431 static void gen8_logical_ring_enable_irq(struct intel_engine_cs
*engine
)
1433 struct drm_i915_private
*dev_priv
= engine
->i915
;
1434 I915_WRITE_IMR(engine
,
1435 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1436 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1439 static void gen8_logical_ring_disable_irq(struct intel_engine_cs
*engine
)
1441 struct drm_i915_private
*dev_priv
= engine
->i915
;
1442 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1445 static int gen8_emit_flush(struct drm_i915_gem_request
*request
, u32 mode
)
1447 struct intel_ring
*ring
= request
->ring
;
1451 ret
= intel_ring_begin(request
, 4);
1455 cmd
= MI_FLUSH_DW
+ 1;
1457 /* We always require a command barrier so that subsequent
1458 * commands, such as breadcrumb interrupts, are strictly ordered
1459 * wrt the contents of the write cache being flushed to memory
1460 * (and thus being coherent from the CPU).
1462 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1464 if (mode
& EMIT_INVALIDATE
) {
1465 cmd
|= MI_INVALIDATE_TLB
;
1466 if (request
->engine
->id
== VCS
)
1467 cmd
|= MI_INVALIDATE_BSD
;
1470 intel_ring_emit(ring
, cmd
);
1471 intel_ring_emit(ring
,
1472 I915_GEM_HWS_SCRATCH_ADDR
|
1473 MI_FLUSH_DW_USE_GTT
);
1474 intel_ring_emit(ring
, 0); /* upper addr */
1475 intel_ring_emit(ring
, 0); /* value */
1476 intel_ring_advance(ring
);
1481 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1484 struct intel_ring
*ring
= request
->ring
;
1485 struct intel_engine_cs
*engine
= request
->engine
;
1487 i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
1488 bool vf_flush_wa
= false, dc_flush_wa
= false;
1493 flags
|= PIPE_CONTROL_CS_STALL
;
1495 if (mode
& EMIT_FLUSH
) {
1496 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1497 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1498 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1499 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1502 if (mode
& EMIT_INVALIDATE
) {
1503 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1504 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1505 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1506 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1507 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1508 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1509 flags
|= PIPE_CONTROL_QW_WRITE
;
1510 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1513 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1516 if (IS_GEN9(request
->i915
))
1519 /* WaForGAMHang:kbl */
1520 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1532 ret
= intel_ring_begin(request
, len
);
1537 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1538 intel_ring_emit(ring
, 0);
1539 intel_ring_emit(ring
, 0);
1540 intel_ring_emit(ring
, 0);
1541 intel_ring_emit(ring
, 0);
1542 intel_ring_emit(ring
, 0);
1546 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1547 intel_ring_emit(ring
, PIPE_CONTROL_DC_FLUSH_ENABLE
);
1548 intel_ring_emit(ring
, 0);
1549 intel_ring_emit(ring
, 0);
1550 intel_ring_emit(ring
, 0);
1551 intel_ring_emit(ring
, 0);
1554 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1555 intel_ring_emit(ring
, flags
);
1556 intel_ring_emit(ring
, scratch_addr
);
1557 intel_ring_emit(ring
, 0);
1558 intel_ring_emit(ring
, 0);
1559 intel_ring_emit(ring
, 0);
1562 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1563 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
);
1564 intel_ring_emit(ring
, 0);
1565 intel_ring_emit(ring
, 0);
1566 intel_ring_emit(ring
, 0);
1567 intel_ring_emit(ring
, 0);
1570 intel_ring_advance(ring
);
1575 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1578 * On BXT A steppings there is a HW coherency issue whereby the
1579 * MI_STORE_DATA_IMM storing the completed request's seqno
1580 * occasionally doesn't invalidate the CPU cache. Work around this by
1581 * clflushing the corresponding cacheline whenever the caller wants
1582 * the coherency to be guaranteed. Note that this cacheline is known
1583 * to be clean at this point, since we only write it in
1584 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1585 * this clflush in practice becomes an invalidate operation.
1587 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1591 * Reserve space for 2 NOOPs at the end of each request to be
1592 * used as a workaround for not being allowed to do lite
1593 * restore with HEAD==TAIL (WaIdleLiteRestore).
1595 #define WA_TAIL_DWORDS 2
1597 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1599 struct intel_ring
*ring
= request
->ring
;
1602 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1606 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1607 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1609 intel_ring_emit(ring
, (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1610 intel_ring_emit(ring
,
1611 intel_hws_seqno_address(request
->engine
) |
1612 MI_FLUSH_DW_USE_GTT
);
1613 intel_ring_emit(ring
, 0);
1614 intel_ring_emit(ring
, request
->fence
.seqno
);
1615 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1616 intel_ring_emit(ring
, MI_NOOP
);
1617 return intel_logical_ring_advance(request
);
1620 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1622 struct intel_ring
*ring
= request
->ring
;
1625 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1629 /* We're using qword write, seqno should be aligned to 8 bytes. */
1630 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1632 /* w/a for post sync ops following a GPGPU operation we
1633 * need a prior CS_STALL, which is emitted by the flush
1634 * following the batch.
1636 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1637 intel_ring_emit(ring
,
1638 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1639 PIPE_CONTROL_CS_STALL
|
1640 PIPE_CONTROL_QW_WRITE
));
1641 intel_ring_emit(ring
, intel_hws_seqno_address(request
->engine
));
1642 intel_ring_emit(ring
, 0);
1643 intel_ring_emit(ring
, i915_gem_request_get_seqno(request
));
1644 /* We're thrashing one dword of HWS. */
1645 intel_ring_emit(ring
, 0);
1646 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1647 intel_ring_emit(ring
, MI_NOOP
);
1648 return intel_logical_ring_advance(request
);
1651 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1655 ret
= intel_logical_ring_workarounds_emit(req
);
1659 ret
= intel_rcs_context_init_mocs(req
);
1661 * Failing to program the MOCS is non-fatal.The system will not
1662 * run at peak performance. So generate an error and carry on.
1665 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1667 return i915_gem_render_state_init(req
);
1671 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1672 * @engine: Engine Command Streamer.
1674 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1676 struct drm_i915_private
*dev_priv
;
1678 if (!intel_engine_initialized(engine
))
1682 * Tasklet cannot be active at this point due intel_mark_active/idle
1683 * so this is just for documentation.
1685 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1686 tasklet_kill(&engine
->irq_tasklet
);
1688 dev_priv
= engine
->i915
;
1690 if (engine
->buffer
) {
1691 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1694 if (engine
->cleanup
)
1695 engine
->cleanup(engine
);
1697 intel_engine_cleanup_common(engine
);
1699 if (engine
->status_page
.vma
) {
1700 i915_gem_object_unpin_map(engine
->status_page
.vma
->obj
);
1701 engine
->status_page
.vma
= NULL
;
1703 intel_lr_context_unpin(dev_priv
->kernel_context
, engine
);
1705 engine
->idle_lite_restore_wa
= 0;
1706 engine
->disable_lite_restore_wa
= false;
1707 engine
->ctx_desc_template
= 0;
1709 lrc_destroy_wa_ctx_obj(engine
);
1710 engine
->i915
= NULL
;
1713 void intel_execlists_enable_submission(struct drm_i915_private
*dev_priv
)
1715 struct intel_engine_cs
*engine
;
1717 for_each_engine(engine
, dev_priv
)
1718 engine
->submit_request
= execlists_submit_request
;
1722 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1724 /* Default vfuncs which can be overriden by each engine. */
1725 engine
->init_hw
= gen8_init_common_ring
;
1726 engine
->emit_flush
= gen8_emit_flush
;
1727 engine
->emit_request
= gen8_emit_request
;
1728 engine
->submit_request
= execlists_submit_request
;
1730 engine
->irq_enable
= gen8_logical_ring_enable_irq
;
1731 engine
->irq_disable
= gen8_logical_ring_disable_irq
;
1732 engine
->emit_bb_start
= gen8_emit_bb_start
;
1733 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1734 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1738 logical_ring_default_irqs(struct intel_engine_cs
*engine
)
1740 unsigned shift
= engine
->irq_shift
;
1741 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1742 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1746 lrc_setup_hws(struct intel_engine_cs
*engine
, struct i915_vma
*vma
)
1748 const int hws_offset
= LRC_PPHWSP_PN
* PAGE_SIZE
;
1751 /* The HWSP is part of the default context object in LRC mode. */
1752 hws
= i915_gem_object_pin_map(vma
->obj
, I915_MAP_WB
);
1754 return PTR_ERR(hws
);
1756 engine
->status_page
.page_addr
= hws
+ hws_offset
;
1757 engine
->status_page
.ggtt_offset
= i915_ggtt_offset(vma
) + hws_offset
;
1758 engine
->status_page
.vma
= vma
;
1764 logical_ring_setup(struct intel_engine_cs
*engine
)
1766 struct drm_i915_private
*dev_priv
= engine
->i915
;
1767 enum forcewake_domains fw_domains
;
1769 intel_engine_setup_common(engine
);
1771 /* Intentionally left blank. */
1772 engine
->buffer
= NULL
;
1774 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
1778 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1779 RING_CONTEXT_STATUS_PTR(engine
),
1780 FW_REG_READ
| FW_REG_WRITE
);
1782 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1783 RING_CONTEXT_STATUS_BUF_BASE(engine
),
1786 engine
->fw_domains
= fw_domains
;
1788 tasklet_init(&engine
->irq_tasklet
,
1789 intel_lrc_irq_handler
, (unsigned long)engine
);
1791 logical_ring_init_platform_invariants(engine
);
1792 logical_ring_default_vfuncs(engine
);
1793 logical_ring_default_irqs(engine
);
1797 logical_ring_init(struct intel_engine_cs
*engine
)
1799 struct i915_gem_context
*dctx
= engine
->i915
->kernel_context
;
1802 ret
= intel_engine_init_common(engine
);
1806 ret
= execlists_context_deferred_alloc(dctx
, engine
);
1810 /* As this is the default context, always pin it */
1811 ret
= intel_lr_context_pin(dctx
, engine
);
1813 DRM_ERROR("Failed to pin context for %s: %d\n",
1818 /* And setup the hardware status page. */
1819 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
1821 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
1828 intel_logical_ring_cleanup(engine
);
1832 int logical_render_ring_init(struct intel_engine_cs
*engine
)
1834 struct drm_i915_private
*dev_priv
= engine
->i915
;
1837 logical_ring_setup(engine
);
1839 if (HAS_L3_DPF(dev_priv
))
1840 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1842 /* Override some for render ring. */
1843 if (INTEL_GEN(dev_priv
) >= 9)
1844 engine
->init_hw
= gen9_init_render_ring
;
1846 engine
->init_hw
= gen8_init_render_ring
;
1847 engine
->init_context
= gen8_init_rcs_context
;
1848 engine
->emit_flush
= gen8_emit_flush_render
;
1849 engine
->emit_request
= gen8_emit_request_render
;
1851 ret
= intel_engine_create_scratch(engine
, 4096);
1855 ret
= intel_init_workaround_bb(engine
);
1858 * We continue even if we fail to initialize WA batch
1859 * because we only expect rare glitches but nothing
1860 * critical to prevent us from using GPU
1862 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1866 ret
= logical_ring_init(engine
);
1868 lrc_destroy_wa_ctx_obj(engine
);
1874 int logical_xcs_ring_init(struct intel_engine_cs
*engine
)
1876 logical_ring_setup(engine
);
1878 return logical_ring_init(engine
);
1882 make_rpcs(struct drm_i915_private
*dev_priv
)
1887 * No explicit RPCS request is needed to ensure full
1888 * slice/subslice/EU enablement prior to Gen9.
1890 if (INTEL_GEN(dev_priv
) < 9)
1894 * Starting in Gen9, render power gating can leave
1895 * slice/subslice/EU in a partially enabled state. We
1896 * must make an explicit request through RPCS for full
1899 if (INTEL_INFO(dev_priv
)->sseu
.has_slice_pg
) {
1900 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1901 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.slice_mask
) <<
1902 GEN8_RPCS_S_CNT_SHIFT
;
1903 rpcs
|= GEN8_RPCS_ENABLE
;
1906 if (INTEL_INFO(dev_priv
)->sseu
.has_subslice_pg
) {
1907 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1908 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.subslice_per_slice
<<
1909 GEN8_RPCS_SS_CNT_SHIFT
;
1910 rpcs
|= GEN8_RPCS_ENABLE
;
1913 if (INTEL_INFO(dev_priv
)->sseu
.has_eu_pg
) {
1914 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1915 GEN8_RPCS_EU_MIN_SHIFT
;
1916 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1917 GEN8_RPCS_EU_MAX_SHIFT
;
1918 rpcs
|= GEN8_RPCS_ENABLE
;
1924 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
1926 u32 indirect_ctx_offset
;
1928 switch (INTEL_GEN(engine
->i915
)) {
1930 MISSING_CASE(INTEL_GEN(engine
->i915
));
1933 indirect_ctx_offset
=
1934 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1937 indirect_ctx_offset
=
1938 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1942 return indirect_ctx_offset
;
1946 populate_lr_context(struct i915_gem_context
*ctx
,
1947 struct drm_i915_gem_object
*ctx_obj
,
1948 struct intel_engine_cs
*engine
,
1949 struct intel_ring
*ring
)
1951 struct drm_i915_private
*dev_priv
= ctx
->i915
;
1952 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1958 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1960 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1962 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1966 vaddr
= i915_gem_object_pin_map(ctx_obj
, I915_MAP_WB
);
1967 if (IS_ERR(vaddr
)) {
1968 ret
= PTR_ERR(vaddr
);
1969 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
1972 ctx_obj
->dirty
= true;
1974 /* The second page of the context object contains some fields which must
1975 * be set up prior to the first execution. */
1976 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
1978 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1979 * commands followed by (reg, value) pairs. The values we are setting here are
1980 * only for the first context restore: on a subsequent save, the GPU will
1981 * recreate this batchbuffer with new values (including all the missing
1982 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1983 reg_state
[CTX_LRI_HEADER_0
] =
1984 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
1985 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
1986 RING_CONTEXT_CONTROL(engine
),
1987 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
1988 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
1989 (HAS_RESOURCE_STREAMER(dev_priv
) ?
1990 CTX_CTRL_RS_CTX_ENABLE
: 0)));
1991 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
1993 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
1995 /* Ring buffer start address is not known until the buffer is pinned.
1996 * It is written to the context image in execlists_update_context()
1998 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
1999 RING_START(engine
->mmio_base
), 0);
2000 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2001 RING_CTL(engine
->mmio_base
),
2002 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2003 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2004 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2005 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2006 RING_BBADDR(engine
->mmio_base
), 0);
2007 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2008 RING_BBSTATE(engine
->mmio_base
),
2010 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2011 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2012 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2013 RING_SBBADDR(engine
->mmio_base
), 0);
2014 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2015 RING_SBBSTATE(engine
->mmio_base
), 0);
2016 if (engine
->id
== RCS
) {
2017 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2018 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2019 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2020 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2021 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2022 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2023 if (engine
->wa_ctx
.vma
) {
2024 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2025 u32 ggtt_offset
= i915_ggtt_offset(wa_ctx
->vma
);
2027 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2028 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2029 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2031 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2032 intel_lr_indirect_ctx_offset(engine
) << 6;
2034 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2035 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2039 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2040 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2041 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2042 /* PDP values well be assigned later if needed */
2043 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2045 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2047 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2049 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2051 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2053 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2055 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2057 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2060 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2061 /* 64b PPGTT (48bit canonical)
2062 * PDP0_DESCRIPTOR contains the base address to PML4 and
2063 * other PDP Descriptors are ignored.
2065 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2068 * PDP*_DESCRIPTOR contains the base address of space supported.
2069 * With dynamic page allocation, PDPs may not be allocated at
2070 * this point. Point the unallocated PDPs to the scratch page
2072 execlists_update_context_pdps(ppgtt
, reg_state
);
2075 if (engine
->id
== RCS
) {
2076 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2077 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2078 make_rpcs(dev_priv
));
2081 i915_gem_object_unpin_map(ctx_obj
);
2087 * intel_lr_context_size() - return the size of the context for an engine
2088 * @engine: which engine to find the context size for
2090 * Each engine may require a different amount of space for a context image,
2091 * so when allocating (or copying) an image, this function can be used to
2092 * find the right size for the specific engine.
2094 * Return: size (in bytes) of an engine-specific context image
2096 * Note: this size includes the HWSP, which is part of the context image
2097 * in LRC mode, but does not include the "shared data page" used with
2098 * GuC submission. The caller should account for this if using the GuC.
2100 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2104 WARN_ON(INTEL_GEN(engine
->i915
) < 8);
2106 switch (engine
->id
) {
2108 if (INTEL_GEN(engine
->i915
) >= 9)
2109 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2111 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2117 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2124 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
2125 struct intel_engine_cs
*engine
)
2127 struct drm_i915_gem_object
*ctx_obj
;
2128 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2129 struct i915_vma
*vma
;
2130 uint32_t context_size
;
2131 struct intel_ring
*ring
;
2136 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2138 /* One extra page as the sharing data between driver and GuC */
2139 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2141 ctx_obj
= i915_gem_object_create(&ctx
->i915
->drm
, context_size
);
2142 if (IS_ERR(ctx_obj
)) {
2143 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2144 return PTR_ERR(ctx_obj
);
2147 vma
= i915_vma_create(ctx_obj
, &ctx
->i915
->ggtt
.base
, NULL
);
2150 goto error_deref_obj
;
2153 ring
= intel_engine_create_ring(engine
, ctx
->ring_size
);
2155 ret
= PTR_ERR(ring
);
2156 goto error_deref_obj
;
2159 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ring
);
2161 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2162 goto error_ring_free
;
2167 ce
->initialised
= engine
->init_context
== NULL
;
2172 intel_ring_free(ring
);
2174 i915_gem_object_put(ctx_obj
);
2178 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2179 struct i915_gem_context
*ctx
)
2181 struct intel_engine_cs
*engine
;
2183 for_each_engine(engine
, dev_priv
) {
2184 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2186 uint32_t *reg_state
;
2191 vaddr
= i915_gem_object_pin_map(ce
->state
->obj
, I915_MAP_WB
);
2192 if (WARN_ON(IS_ERR(vaddr
)))
2195 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2197 reg_state
[CTX_RING_HEAD
+1] = 0;
2198 reg_state
[CTX_RING_TAIL
+1] = 0;
2200 ce
->state
->obj
->dirty
= true;
2201 i915_gem_object_unpin_map(ce
->state
->obj
);