2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
193 const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
194 ppgtt->pdp.page_directory[n]->daddr : \
195 ppgtt->scratch_pd->daddr; \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
201 ADVANCED_CONTEXT
= 0,
206 #define GEN8_CTX_MODE_SHIFT 3
209 FAULT_AND_HALT
, /* Debug only */
211 FAULT_AND_CONTINUE
/* Unsupported */
213 #define GEN8_CTX_ID_SHIFT 32
214 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
216 static int intel_lr_context_pin(struct intel_engine_cs
*ring
,
217 struct intel_context
*ctx
);
220 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
222 * @enable_execlists: value of i915.enable_execlists module parameter.
224 * Only certain platforms support Execlists (the prerequisites being
225 * support for Logical Ring Contexts and Aliasing PPGTT or better).
227 * Return: 1 if Execlists is supported and has to be enabled.
229 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
231 WARN_ON(i915
.enable_ppgtt
== -1);
233 if (INTEL_INFO(dev
)->gen
>= 9)
236 if (enable_execlists
== 0)
239 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
240 i915
.use_mmio_flip
>= 0)
247 * intel_execlists_ctx_id() - get the Execlists Context ID
248 * @ctx_obj: Logical Ring Context backing object.
250 * Do not confuse with ctx->id! Unfortunately we have a name overload
251 * here: the old context ID we pass to userspace as a handler so that
252 * they can refer to a context, and the new context ID we pass to the
253 * ELSP so that the GPU can inform us of the context status via
256 * Return: 20-bits globally unique context ID.
258 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
260 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
262 /* LRCA is required to be 4K aligned so the more significant 20 bits
263 * are globally unique */
267 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs
*ring
,
268 struct drm_i915_gem_object
*ctx_obj
)
270 struct drm_device
*dev
= ring
->dev
;
272 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
274 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
276 desc
= GEN8_CTX_VALID
;
277 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
278 if (IS_GEN8(ctx_obj
->base
.dev
))
279 desc
|= GEN8_CTX_L3LLC_COHERENT
;
280 desc
|= GEN8_CTX_PRIVILEGE
;
282 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
284 /* TODO: WaDisableLiteRestore when we start using semaphore
285 * signalling between Command Streamers */
286 /* desc |= GEN8_CTX_FORCE_RESTORE; */
288 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
290 INTEL_REVID(dev
) <= SKL_REVID_B0
&&
291 (ring
->id
== BCS
|| ring
->id
== VCS
||
292 ring
->id
== VECS
|| ring
->id
== VCS2
))
293 desc
|= GEN8_CTX_FORCE_RESTORE
;
298 static void execlists_elsp_write(struct intel_engine_cs
*ring
,
299 struct drm_i915_gem_object
*ctx_obj0
,
300 struct drm_i915_gem_object
*ctx_obj1
)
302 struct drm_device
*dev
= ring
->dev
;
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
307 /* XXX: You must always write both descriptors in the order below. */
309 temp
= execlists_ctx_descriptor(ring
, ctx_obj1
);
312 desc
[1] = (u32
)(temp
>> 32);
315 temp
= execlists_ctx_descriptor(ring
, ctx_obj0
);
316 desc
[3] = (u32
)(temp
>> 32);
319 spin_lock(&dev_priv
->uncore
.lock
);
320 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
321 I915_WRITE_FW(RING_ELSP(ring
), desc
[1]);
322 I915_WRITE_FW(RING_ELSP(ring
), desc
[0]);
323 I915_WRITE_FW(RING_ELSP(ring
), desc
[3]);
325 /* The context is automatically loaded after the following */
326 I915_WRITE_FW(RING_ELSP(ring
), desc
[2]);
328 /* ELSP is a wo register, so use another nearby reg for posting instead */
329 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
330 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
331 spin_unlock(&dev_priv
->uncore
.lock
);
334 static int execlists_update_context(struct drm_i915_gem_object
*ctx_obj
,
335 struct drm_i915_gem_object
*ring_obj
,
336 struct i915_hw_ppgtt
*ppgtt
,
342 page
= i915_gem_object_get_page(ctx_obj
, 1);
343 reg_state
= kmap_atomic(page
);
345 reg_state
[CTX_RING_TAIL
+1] = tail
;
346 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(ring_obj
);
348 /* True PPGTT with dynamic page allocation: update PDP registers and
349 * point the unallocated PDPs to the scratch page
352 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
353 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
354 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
355 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
358 kunmap_atomic(reg_state
);
363 static void execlists_submit_contexts(struct intel_engine_cs
*ring
,
364 struct intel_context
*to0
, u32 tail0
,
365 struct intel_context
*to1
, u32 tail1
)
367 struct drm_i915_gem_object
*ctx_obj0
= to0
->engine
[ring
->id
].state
;
368 struct intel_ringbuffer
*ringbuf0
= to0
->engine
[ring
->id
].ringbuf
;
369 struct drm_i915_gem_object
*ctx_obj1
= NULL
;
370 struct intel_ringbuffer
*ringbuf1
= NULL
;
373 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0
));
374 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0
->obj
));
376 execlists_update_context(ctx_obj0
, ringbuf0
->obj
, to0
->ppgtt
, tail0
);
379 ringbuf1
= to1
->engine
[ring
->id
].ringbuf
;
380 ctx_obj1
= to1
->engine
[ring
->id
].state
;
382 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1
));
383 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1
->obj
));
385 execlists_update_context(ctx_obj1
, ringbuf1
->obj
, to1
->ppgtt
, tail1
);
388 execlists_elsp_write(ring
, ctx_obj0
, ctx_obj1
);
391 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
393 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
394 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
396 assert_spin_locked(&ring
->execlist_lock
);
399 * If irqs are not active generate a warning as batches that finish
400 * without the irqs may get lost and a GPU Hang may occur.
402 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
404 if (list_empty(&ring
->execlist_queue
))
407 /* Try to read in pairs */
408 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
412 } else if (req0
->ctx
== cursor
->ctx
) {
413 /* Same ctx: ignore first request, as second request
414 * will update tail past first request's workload */
415 cursor
->elsp_submitted
= req0
->elsp_submitted
;
416 list_del(&req0
->execlist_link
);
417 list_add_tail(&req0
->execlist_link
,
418 &ring
->execlist_retired_req_list
);
426 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
428 * WaIdleLiteRestore: make sure we never cause a lite
429 * restore with HEAD==TAIL
431 if (req0
->elsp_submitted
) {
433 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
434 * as we resubmit the request. See gen8_emit_request()
435 * for where we prepare the padding after the end of the
438 struct intel_ringbuffer
*ringbuf
;
440 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
442 req0
->tail
&= ringbuf
->size
- 1;
446 WARN_ON(req1
&& req1
->elsp_submitted
);
448 execlists_submit_contexts(ring
, req0
->ctx
, req0
->tail
,
449 req1
? req1
->ctx
: NULL
,
450 req1
? req1
->tail
: 0);
452 req0
->elsp_submitted
++;
454 req1
->elsp_submitted
++;
457 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
460 struct drm_i915_gem_request
*head_req
;
462 assert_spin_locked(&ring
->execlist_lock
);
464 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
465 struct drm_i915_gem_request
,
468 if (head_req
!= NULL
) {
469 struct drm_i915_gem_object
*ctx_obj
=
470 head_req
->ctx
->engine
[ring
->id
].state
;
471 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
472 WARN(head_req
->elsp_submitted
== 0,
473 "Never submitted head request\n");
475 if (--head_req
->elsp_submitted
<= 0) {
476 list_del(&head_req
->execlist_link
);
477 list_add_tail(&head_req
->execlist_link
,
478 &ring
->execlist_retired_req_list
);
488 * intel_lrc_irq_handler() - handle Context Switch interrupts
489 * @ring: Engine Command Streamer to handle.
491 * Check the unread Context Status Buffers and manage the submission of new
492 * contexts to the ELSP accordingly.
494 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
496 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
502 u32 submit_contexts
= 0;
504 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
506 read_pointer
= ring
->next_context_status_buffer
;
507 write_pointer
= status_pointer
& 0x07;
508 if (read_pointer
> write_pointer
)
511 spin_lock(&ring
->execlist_lock
);
513 while (read_pointer
< write_pointer
) {
515 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
516 (read_pointer
% 6) * 8);
517 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
518 (read_pointer
% 6) * 8 + 4);
520 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
521 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
522 if (execlists_check_remove_request(ring
, status_id
))
523 WARN(1, "Lite Restored request removed from queue\n");
525 WARN(1, "Preemption without Lite Restore\n");
528 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
529 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
530 if (execlists_check_remove_request(ring
, status_id
))
535 if (submit_contexts
!= 0)
536 execlists_context_unqueue(ring
);
538 spin_unlock(&ring
->execlist_lock
);
540 WARN(submit_contexts
> 2, "More than two context complete events?\n");
541 ring
->next_context_status_buffer
= write_pointer
% 6;
543 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
544 ((u32
)ring
->next_context_status_buffer
& 0x07) << 8);
547 static int execlists_context_queue(struct intel_engine_cs
*ring
,
548 struct intel_context
*to
,
550 struct drm_i915_gem_request
*request
)
552 struct drm_i915_gem_request
*cursor
;
553 int num_elements
= 0;
555 if (to
!= ring
->default_context
)
556 intel_lr_context_pin(ring
, to
);
560 * If there isn't a request associated with this submission,
561 * create one as a temporary holder.
563 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
566 request
->ring
= ring
;
568 kref_init(&request
->ref
);
569 i915_gem_context_reference(request
->ctx
);
571 i915_gem_request_reference(request
);
572 WARN_ON(to
!= request
->ctx
);
574 request
->tail
= tail
;
576 spin_lock_irq(&ring
->execlist_lock
);
578 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
579 if (++num_elements
> 2)
582 if (num_elements
> 2) {
583 struct drm_i915_gem_request
*tail_req
;
585 tail_req
= list_last_entry(&ring
->execlist_queue
,
586 struct drm_i915_gem_request
,
589 if (to
== tail_req
->ctx
) {
590 WARN(tail_req
->elsp_submitted
!= 0,
591 "More than 2 already-submitted reqs queued\n");
592 list_del(&tail_req
->execlist_link
);
593 list_add_tail(&tail_req
->execlist_link
,
594 &ring
->execlist_retired_req_list
);
598 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
599 if (num_elements
== 0)
600 execlists_context_unqueue(ring
);
602 spin_unlock_irq(&ring
->execlist_lock
);
607 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
609 struct intel_engine_cs
*ring
= req
->ring
;
610 uint32_t flush_domains
;
614 if (ring
->gpu_caches_dirty
)
615 flush_domains
= I915_GEM_GPU_DOMAINS
;
617 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
621 ring
->gpu_caches_dirty
= false;
625 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
626 struct list_head
*vmas
)
628 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
629 struct i915_vma
*vma
;
630 uint32_t flush_domains
= 0;
631 bool flush_chipset
= false;
634 list_for_each_entry(vma
, vmas
, exec_list
) {
635 struct drm_i915_gem_object
*obj
= vma
->obj
;
637 if (obj
->active
& other_rings
) {
638 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
643 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
644 flush_chipset
|= i915_gem_clflush_object(obj
, false);
646 flush_domains
|= obj
->base
.write_domain
;
649 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
652 /* Unconditionally invalidate gpu caches and ensure that we do flush
653 * any residual writes from the previous batch.
655 return logical_ring_invalidate_all_caches(req
);
658 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
662 if (request
->ctx
!= request
->ring
->default_context
) {
663 ret
= intel_lr_context_pin(request
->ring
, request
->ctx
);
668 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
673 static int logical_ring_wait_for_space(struct intel_ringbuffer
*ringbuf
,
674 struct intel_context
*ctx
,
677 struct intel_engine_cs
*ring
= ringbuf
->ring
;
678 struct drm_i915_gem_request
*request
;
682 /* The whole point of reserving space is to not wait! */
683 WARN_ON(ringbuf
->reserved_in_use
);
685 if (intel_ring_space(ringbuf
) >= bytes
)
688 list_for_each_entry(request
, &ring
->request_list
, list
) {
690 * The request queue is per-engine, so can contain requests
691 * from multiple ringbuffers. Here, we must ignore any that
692 * aren't from the ringbuffer we're considering.
694 if (request
->ringbuf
!= ringbuf
)
697 /* Would completion of this request free enough space? */
698 space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
704 if (WARN_ON(&request
->list
== &ring
->request_list
))
707 ret
= i915_wait_request(request
);
711 ringbuf
->space
= space
;
716 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
717 * @ringbuf: Logical Ringbuffer to advance.
719 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
720 * really happens during submission is that the context and current tail will be placed
721 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
722 * point, the tail *inside* the context is updated and the ELSP written to.
725 intel_logical_ring_advance_and_submit(struct intel_ringbuffer
*ringbuf
,
726 struct intel_context
*ctx
,
727 struct drm_i915_gem_request
*request
)
729 struct intel_engine_cs
*ring
= ringbuf
->ring
;
731 intel_logical_ring_advance(ringbuf
);
733 if (intel_ring_stopped(ring
))
736 execlists_context_queue(ring
, ctx
, ringbuf
->tail
, request
);
739 static int logical_ring_wrap_buffer(struct intel_ringbuffer
*ringbuf
,
740 struct intel_context
*ctx
)
742 uint32_t __iomem
*virt
;
743 int rem
= ringbuf
->size
- ringbuf
->tail
;
745 /* Can't wrap if space has already been reserved! */
746 WARN_ON(ringbuf
->reserved_in_use
);
748 if (ringbuf
->space
< rem
) {
749 int ret
= logical_ring_wait_for_space(ringbuf
, ctx
, rem
);
755 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
758 iowrite32(MI_NOOP
, virt
++);
761 intel_ring_update_space(ringbuf
);
766 static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf
,
767 struct intel_context
*ctx
, int bytes
)
772 * Add on the reserved size to the request to make sure that after
773 * the intended commands have been emitted, there is guaranteed to
774 * still be enough free space to send them to the hardware.
776 if (!ringbuf
->reserved_in_use
)
777 bytes
+= ringbuf
->reserved_size
;
779 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
780 ret
= logical_ring_wrap_buffer(ringbuf
, ctx
);
784 if(ringbuf
->reserved_size
) {
785 uint32_t size
= ringbuf
->reserved_size
;
787 intel_ring_reserved_space_cancel(ringbuf
);
788 intel_ring_reserved_space_reserve(ringbuf
, size
);
792 if (unlikely(ringbuf
->space
< bytes
)) {
793 ret
= logical_ring_wait_for_space(ringbuf
, ctx
, bytes
);
802 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
804 * @request: The request to start some new work for
805 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
807 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
808 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
809 * and also preallocates a request (every workload submission is still mediated through
810 * requests, same as it did with legacy ringbuffer submission).
812 * Return: non-zero if the ringbuffer is not ready to be written to.
814 static int intel_logical_ring_begin(struct drm_i915_gem_request
*req
,
817 struct drm_i915_private
*dev_priv
;
820 WARN_ON(req
== NULL
);
821 dev_priv
= req
->ring
->dev
->dev_private
;
823 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
824 dev_priv
->mm
.interruptible
);
828 ret
= logical_ring_prepare(req
->ringbuf
, req
->ctx
,
829 num_dwords
* sizeof(uint32_t));
833 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
837 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
840 * The first call merely notes the reserve request and is common for
841 * all back ends. The subsequent localised _begin() call actually
842 * ensures that the reservation is available. Without the begin, if
843 * the request creator immediately submitted the request without
844 * adding any commands to it then there might not actually be
845 * sufficient room for the submission commands.
847 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
849 return intel_logical_ring_begin(request
, 0);
853 * execlists_submission() - submit a batchbuffer for execution, Execlists style
856 * @ring: Engine Command Streamer to submit to.
857 * @ctx: Context to employ for this submission.
858 * @args: execbuffer call arguments.
859 * @vmas: list of vmas.
860 * @batch_obj: the batchbuffer to submit.
861 * @exec_start: batchbuffer start virtual address pointer.
862 * @dispatch_flags: translated execbuffer call flags.
864 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
865 * away the submission details of the execbuffer ioctl call.
867 * Return: non-zero if the submission fails.
869 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
870 struct drm_i915_gem_execbuffer2
*args
,
871 struct list_head
*vmas
)
873 struct drm_device
*dev
= params
->dev
;
874 struct intel_engine_cs
*ring
= params
->ring
;
875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
876 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
882 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
883 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
884 switch (instp_mode
) {
885 case I915_EXEC_CONSTANTS_REL_GENERAL
:
886 case I915_EXEC_CONSTANTS_ABSOLUTE
:
887 case I915_EXEC_CONSTANTS_REL_SURFACE
:
888 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
889 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
893 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
894 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
895 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
899 /* The HW changed the meaning on this bit on gen6 */
900 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
904 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
908 if (args
->num_cliprects
!= 0) {
909 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
912 if (args
->DR4
== 0xffffffff) {
913 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
917 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
918 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
923 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
924 DRM_DEBUG("sol reset is gen7 only\n");
928 ret
= execlists_move_to_gpu(params
->request
, vmas
);
932 if (ring
== &dev_priv
->ring
[RCS
] &&
933 instp_mode
!= dev_priv
->relative_constants_mode
) {
934 ret
= intel_logical_ring_begin(params
->request
, 4);
938 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
939 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
940 intel_logical_ring_emit(ringbuf
, INSTPM
);
941 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
942 intel_logical_ring_advance(ringbuf
);
944 dev_priv
->relative_constants_mode
= instp_mode
;
947 exec_start
= params
->batch_obj_vm_offset
+
948 args
->batch_start_offset
;
950 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
954 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
956 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
957 i915_gem_execbuffer_retire_commands(params
);
962 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
964 struct drm_i915_gem_request
*req
, *tmp
;
965 struct list_head retired_list
;
967 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
968 if (list_empty(&ring
->execlist_retired_req_list
))
971 INIT_LIST_HEAD(&retired_list
);
972 spin_lock_irq(&ring
->execlist_lock
);
973 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
974 spin_unlock_irq(&ring
->execlist_lock
);
976 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
977 struct intel_context
*ctx
= req
->ctx
;
978 struct drm_i915_gem_object
*ctx_obj
=
979 ctx
->engine
[ring
->id
].state
;
981 if (ctx_obj
&& (ctx
!= ring
->default_context
))
982 intel_lr_context_unpin(ring
, ctx
);
983 list_del(&req
->execlist_link
);
984 i915_gem_request_unreference(req
);
988 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
990 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
993 if (!intel_ring_initialized(ring
))
996 ret
= intel_ring_idle(ring
);
997 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
998 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1001 /* TODO: Is this correct with Execlists enabled? */
1002 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
1003 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
1004 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
1007 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
1010 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
1012 struct intel_engine_cs
*ring
= req
->ring
;
1015 if (!ring
->gpu_caches_dirty
)
1018 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
1022 ring
->gpu_caches_dirty
= false;
1026 static int intel_lr_context_pin(struct intel_engine_cs
*ring
,
1027 struct intel_context
*ctx
)
1029 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
1030 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1033 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1034 if (ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1035 ret
= i915_gem_obj_ggtt_pin(ctx_obj
,
1036 GEN8_LR_CONTEXT_ALIGN
, 0);
1038 goto reset_pin_count
;
1040 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1048 i915_gem_object_ggtt_unpin(ctx_obj
);
1050 ctx
->engine
[ring
->id
].pin_count
= 0;
1055 void intel_lr_context_unpin(struct intel_engine_cs
*ring
,
1056 struct intel_context
*ctx
)
1058 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
1059 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1062 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1063 if (--ctx
->engine
[ring
->id
].pin_count
== 0) {
1064 intel_unpin_ringbuffer_obj(ringbuf
);
1065 i915_gem_object_ggtt_unpin(ctx_obj
);
1070 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1073 struct intel_engine_cs
*ring
= req
->ring
;
1074 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1075 struct drm_device
*dev
= ring
->dev
;
1076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1077 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1079 if (WARN_ON_ONCE(w
->count
== 0))
1082 ring
->gpu_caches_dirty
= true;
1083 ret
= logical_ring_flush_all_caches(req
);
1087 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1091 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1092 for (i
= 0; i
< w
->count
; i
++) {
1093 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1094 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1096 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1098 intel_logical_ring_advance(ringbuf
);
1100 ring
->gpu_caches_dirty
= true;
1101 ret
= logical_ring_flush_all_caches(req
);
1108 #define wa_ctx_emit(batch, cmd) \
1110 if (WARN_ON(index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1113 batch[index++] = (cmd); \
1116 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1118 uint32_t start_alignment
)
1120 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1123 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1125 uint32_t size_alignment
)
1127 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1129 WARN(wa_ctx
->size
% size_alignment
,
1130 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1131 wa_ctx
->size
, size_alignment
);
1136 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1138 * @ring: only applicable for RCS
1139 * @wa_ctx: structure representing wa_ctx
1140 * offset: specifies start of the batch, should be cache-aligned. This is updated
1141 * with the offset value received as input.
1142 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1143 * @batch: page in which WA are loaded
1144 * @offset: This field specifies the start of the batch, it should be
1145 * cache-aligned otherwise it is adjusted accordingly.
1146 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1147 * initialized at the beginning and shared across all contexts but this field
1148 * helps us to have multiple batches at different offsets and select them based
1149 * on a criteria. At the moment this batch always start at the beginning of the page
1150 * and at this point we don't have multiple wa_ctx batch buffers.
1152 * The number of WA applied are not known at the beginning; we use this field
1153 * to return the no of DWORDS written.
1155 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1156 * so it adds NOOPs as padding to make it cacheline aligned.
1157 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1158 * makes a complete batch buffer.
1160 * Return: non-zero if we exceed the PAGE_SIZE limit.
1163 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1164 struct i915_wa_ctx_bb
*wa_ctx
,
1165 uint32_t *const batch
,
1168 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1170 /* WaDisableCtxRestoreArbitration:bdw,chv */
1171 wa_ctx_emit(batch
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1173 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1174 if (IS_BROADWELL(ring
->dev
)) {
1175 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
1176 uint32_t l3sqc4_flush
= (I915_READ(GEN8_L3SQCREG4
) |
1177 GEN8_LQSC_FLUSH_COHERENT_LINES
);
1179 wa_ctx_emit(batch
, MI_LOAD_REGISTER_IMM(1));
1180 wa_ctx_emit(batch
, GEN8_L3SQCREG4
);
1181 wa_ctx_emit(batch
, l3sqc4_flush
);
1183 wa_ctx_emit(batch
, GFX_OP_PIPE_CONTROL(6));
1184 wa_ctx_emit(batch
, (PIPE_CONTROL_CS_STALL
|
1185 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1186 wa_ctx_emit(batch
, 0);
1187 wa_ctx_emit(batch
, 0);
1188 wa_ctx_emit(batch
, 0);
1189 wa_ctx_emit(batch
, 0);
1191 wa_ctx_emit(batch
, MI_LOAD_REGISTER_IMM(1));
1192 wa_ctx_emit(batch
, GEN8_L3SQCREG4
);
1193 wa_ctx_emit(batch
, l3sqc4_flush
& ~GEN8_LQSC_FLUSH_COHERENT_LINES
);
1196 /* Pad to end of cacheline */
1197 while (index
% CACHELINE_DWORDS
)
1198 wa_ctx_emit(batch
, MI_NOOP
);
1201 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1202 * execution depends on the length specified in terms of cache lines
1203 * in the register CTX_RCS_INDIRECT_CTX
1206 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1210 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1212 * @ring: only applicable for RCS
1213 * @wa_ctx: structure representing wa_ctx
1214 * offset: specifies start of the batch, should be cache-aligned.
1215 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1216 * @offset: This field specifies the start of this batch.
1217 * This batch is started immediately after indirect_ctx batch. Since we ensure
1218 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1220 * The number of DWORDS written are returned using this field.
1222 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1223 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1225 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1226 struct i915_wa_ctx_bb
*wa_ctx
,
1227 uint32_t *const batch
,
1230 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1232 /* WaDisableCtxRestoreArbitration:bdw,chv */
1233 wa_ctx_emit(batch
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1235 wa_ctx_emit(batch
, MI_BATCH_BUFFER_END
);
1237 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1240 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1244 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1245 if (!ring
->wa_ctx
.obj
) {
1246 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1250 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1252 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1254 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1261 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1263 if (ring
->wa_ctx
.obj
) {
1264 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1265 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1266 ring
->wa_ctx
.obj
= NULL
;
1270 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1276 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1278 WARN_ON(ring
->id
!= RCS
);
1280 /* some WA perform writes to scratch page, ensure it is valid */
1281 if (ring
->scratch
.obj
== NULL
) {
1282 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1286 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1288 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1292 page
= i915_gem_object_get_page(wa_ctx
->obj
, 0);
1293 batch
= kmap_atomic(page
);
1296 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1297 ret
= gen8_init_indirectctx_bb(ring
,
1298 &wa_ctx
->indirect_ctx
,
1304 ret
= gen8_init_perctx_bb(ring
,
1311 WARN(INTEL_INFO(ring
->dev
)->gen
>= 8,
1312 "WA batch buffer is not initialized for Gen%d\n",
1313 INTEL_INFO(ring
->dev
)->gen
);
1314 lrc_destroy_wa_ctx_obj(ring
);
1318 kunmap_atomic(batch
);
1320 lrc_destroy_wa_ctx_obj(ring
);
1325 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1327 struct drm_device
*dev
= ring
->dev
;
1328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1330 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1331 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1333 I915_WRITE(RING_MODE_GEN7(ring
),
1334 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1335 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1336 POSTING_READ(RING_MODE_GEN7(ring
));
1337 ring
->next_context_status_buffer
= 0;
1338 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1340 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1345 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1347 struct drm_device
*dev
= ring
->dev
;
1348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1351 ret
= gen8_init_common_ring(ring
);
1355 /* We need to disable the AsyncFlip performance optimisations in order
1356 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1357 * programmed to '1' on all products.
1359 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1361 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1363 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1365 return init_workarounds_ring(ring
);
1368 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1372 ret
= gen8_init_common_ring(ring
);
1376 return init_workarounds_ring(ring
);
1379 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1380 u64 offset
, unsigned dispatch_flags
)
1382 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1383 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1386 ret
= intel_logical_ring_begin(req
, 4);
1390 /* FIXME(BDW): Address space and security selectors. */
1391 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
1392 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1393 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1394 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1395 intel_logical_ring_advance(ringbuf
);
1400 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1402 struct drm_device
*dev
= ring
->dev
;
1403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1404 unsigned long flags
;
1406 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1409 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1410 if (ring
->irq_refcount
++ == 0) {
1411 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1412 POSTING_READ(RING_IMR(ring
->mmio_base
));
1414 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1419 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1421 struct drm_device
*dev
= ring
->dev
;
1422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1423 unsigned long flags
;
1425 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1426 if (--ring
->irq_refcount
== 0) {
1427 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1428 POSTING_READ(RING_IMR(ring
->mmio_base
));
1430 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1433 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1434 u32 invalidate_domains
,
1437 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1438 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1439 struct drm_device
*dev
= ring
->dev
;
1440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 ret
= intel_logical_ring_begin(request
, 4);
1448 cmd
= MI_FLUSH_DW
+ 1;
1450 /* We always require a command barrier so that subsequent
1451 * commands, such as breadcrumb interrupts, are strictly ordered
1452 * wrt the contents of the write cache being flushed to memory
1453 * (and thus being coherent from the CPU).
1455 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1457 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1458 cmd
|= MI_INVALIDATE_TLB
;
1459 if (ring
== &dev_priv
->ring
[VCS
])
1460 cmd
|= MI_INVALIDATE_BSD
;
1463 intel_logical_ring_emit(ringbuf
, cmd
);
1464 intel_logical_ring_emit(ringbuf
,
1465 I915_GEM_HWS_SCRATCH_ADDR
|
1466 MI_FLUSH_DW_USE_GTT
);
1467 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1468 intel_logical_ring_emit(ringbuf
, 0); /* value */
1469 intel_logical_ring_advance(ringbuf
);
1474 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1475 u32 invalidate_domains
,
1478 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1479 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1480 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1485 flags
|= PIPE_CONTROL_CS_STALL
;
1487 if (flush_domains
) {
1488 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1489 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1492 if (invalidate_domains
) {
1493 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1494 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1495 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1496 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1497 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1498 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1499 flags
|= PIPE_CONTROL_QW_WRITE
;
1500 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1504 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1507 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1508 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1510 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1515 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1516 intel_logical_ring_emit(ringbuf
, 0);
1517 intel_logical_ring_emit(ringbuf
, 0);
1518 intel_logical_ring_emit(ringbuf
, 0);
1519 intel_logical_ring_emit(ringbuf
, 0);
1520 intel_logical_ring_emit(ringbuf
, 0);
1523 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1524 intel_logical_ring_emit(ringbuf
, flags
);
1525 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1526 intel_logical_ring_emit(ringbuf
, 0);
1527 intel_logical_ring_emit(ringbuf
, 0);
1528 intel_logical_ring_emit(ringbuf
, 0);
1529 intel_logical_ring_advance(ringbuf
);
1534 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1536 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1539 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1541 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1544 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1546 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1547 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1552 * Reserve space for 2 NOOPs at the end of each request to be
1553 * used as a workaround for not being allowed to do lite
1554 * restore with HEAD==TAIL (WaIdleLiteRestore).
1556 ret
= intel_logical_ring_begin(request
, 8);
1560 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1561 cmd
|= MI_GLOBAL_GTT
;
1563 intel_logical_ring_emit(ringbuf
, cmd
);
1564 intel_logical_ring_emit(ringbuf
,
1565 (ring
->status_page
.gfx_addr
+
1566 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1567 intel_logical_ring_emit(ringbuf
, 0);
1568 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1569 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1570 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1571 intel_logical_ring_advance_and_submit(ringbuf
, request
->ctx
, request
);
1574 * Here we add two extra NOOPs as padding to avoid
1575 * lite restore of a context with HEAD==TAIL.
1577 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1578 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1579 intel_logical_ring_advance(ringbuf
);
1584 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1586 struct render_state so
;
1589 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1593 if (so
.rodata
== NULL
)
1596 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1597 I915_DISPATCH_SECURE
);
1601 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1604 i915_gem_render_state_fini(&so
);
1608 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1612 ret
= intel_logical_ring_workarounds_emit(req
);
1616 return intel_lr_context_render_state_init(req
);
1620 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1622 * @ring: Engine Command Streamer.
1625 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1627 struct drm_i915_private
*dev_priv
;
1629 if (!intel_ring_initialized(ring
))
1632 dev_priv
= ring
->dev
->dev_private
;
1634 intel_logical_ring_stop(ring
);
1635 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1636 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
1639 ring
->cleanup(ring
);
1641 i915_cmd_parser_fini_ring(ring
);
1642 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1644 if (ring
->status_page
.obj
) {
1645 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1646 ring
->status_page
.obj
= NULL
;
1649 lrc_destroy_wa_ctx_obj(ring
);
1652 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1656 /* Intentionally left blank. */
1657 ring
->buffer
= NULL
;
1660 INIT_LIST_HEAD(&ring
->active_list
);
1661 INIT_LIST_HEAD(&ring
->request_list
);
1662 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1663 init_waitqueue_head(&ring
->irq_queue
);
1665 INIT_LIST_HEAD(&ring
->execlist_queue
);
1666 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1667 spin_lock_init(&ring
->execlist_lock
);
1669 ret
= i915_cmd_parser_init_ring(ring
);
1673 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1678 static int logical_render_ring_init(struct drm_device
*dev
)
1680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1681 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1684 ring
->name
= "render ring";
1686 ring
->mmio_base
= RENDER_RING_BASE
;
1687 ring
->irq_enable_mask
=
1688 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1689 ring
->irq_keep_mask
=
1690 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1691 if (HAS_L3_DPF(dev
))
1692 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1694 if (INTEL_INFO(dev
)->gen
>= 9)
1695 ring
->init_hw
= gen9_init_render_ring
;
1697 ring
->init_hw
= gen8_init_render_ring
;
1698 ring
->init_context
= gen8_init_rcs_context
;
1699 ring
->cleanup
= intel_fini_pipe_control
;
1700 ring
->get_seqno
= gen8_get_seqno
;
1701 ring
->set_seqno
= gen8_set_seqno
;
1702 ring
->emit_request
= gen8_emit_request
;
1703 ring
->emit_flush
= gen8_emit_flush_render
;
1704 ring
->irq_get
= gen8_logical_ring_get_irq
;
1705 ring
->irq_put
= gen8_logical_ring_put_irq
;
1706 ring
->emit_bb_start
= gen8_emit_bb_start
;
1710 ret
= intel_init_pipe_control(ring
);
1714 ret
= intel_init_workaround_bb(ring
);
1717 * We continue even if we fail to initialize WA batch
1718 * because we only expect rare glitches but nothing
1719 * critical to prevent us from using GPU
1721 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1725 ret
= logical_ring_init(dev
, ring
);
1727 lrc_destroy_wa_ctx_obj(ring
);
1733 static int logical_bsd_ring_init(struct drm_device
*dev
)
1735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1736 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1738 ring
->name
= "bsd ring";
1740 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1741 ring
->irq_enable_mask
=
1742 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1743 ring
->irq_keep_mask
=
1744 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1746 ring
->init_hw
= gen8_init_common_ring
;
1747 ring
->get_seqno
= gen8_get_seqno
;
1748 ring
->set_seqno
= gen8_set_seqno
;
1749 ring
->emit_request
= gen8_emit_request
;
1750 ring
->emit_flush
= gen8_emit_flush
;
1751 ring
->irq_get
= gen8_logical_ring_get_irq
;
1752 ring
->irq_put
= gen8_logical_ring_put_irq
;
1753 ring
->emit_bb_start
= gen8_emit_bb_start
;
1755 return logical_ring_init(dev
, ring
);
1758 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1761 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1763 ring
->name
= "bds2 ring";
1765 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1766 ring
->irq_enable_mask
=
1767 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1768 ring
->irq_keep_mask
=
1769 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1771 ring
->init_hw
= gen8_init_common_ring
;
1772 ring
->get_seqno
= gen8_get_seqno
;
1773 ring
->set_seqno
= gen8_set_seqno
;
1774 ring
->emit_request
= gen8_emit_request
;
1775 ring
->emit_flush
= gen8_emit_flush
;
1776 ring
->irq_get
= gen8_logical_ring_get_irq
;
1777 ring
->irq_put
= gen8_logical_ring_put_irq
;
1778 ring
->emit_bb_start
= gen8_emit_bb_start
;
1780 return logical_ring_init(dev
, ring
);
1783 static int logical_blt_ring_init(struct drm_device
*dev
)
1785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1786 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1788 ring
->name
= "blitter ring";
1790 ring
->mmio_base
= BLT_RING_BASE
;
1791 ring
->irq_enable_mask
=
1792 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1793 ring
->irq_keep_mask
=
1794 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1796 ring
->init_hw
= gen8_init_common_ring
;
1797 ring
->get_seqno
= gen8_get_seqno
;
1798 ring
->set_seqno
= gen8_set_seqno
;
1799 ring
->emit_request
= gen8_emit_request
;
1800 ring
->emit_flush
= gen8_emit_flush
;
1801 ring
->irq_get
= gen8_logical_ring_get_irq
;
1802 ring
->irq_put
= gen8_logical_ring_put_irq
;
1803 ring
->emit_bb_start
= gen8_emit_bb_start
;
1805 return logical_ring_init(dev
, ring
);
1808 static int logical_vebox_ring_init(struct drm_device
*dev
)
1810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1811 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1813 ring
->name
= "video enhancement ring";
1815 ring
->mmio_base
= VEBOX_RING_BASE
;
1816 ring
->irq_enable_mask
=
1817 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1818 ring
->irq_keep_mask
=
1819 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1821 ring
->init_hw
= gen8_init_common_ring
;
1822 ring
->get_seqno
= gen8_get_seqno
;
1823 ring
->set_seqno
= gen8_set_seqno
;
1824 ring
->emit_request
= gen8_emit_request
;
1825 ring
->emit_flush
= gen8_emit_flush
;
1826 ring
->irq_get
= gen8_logical_ring_get_irq
;
1827 ring
->irq_put
= gen8_logical_ring_put_irq
;
1828 ring
->emit_bb_start
= gen8_emit_bb_start
;
1830 return logical_ring_init(dev
, ring
);
1834 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1837 * This function inits the engines for an Execlists submission style (the equivalent in the
1838 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1839 * those engines that are present in the hardware.
1841 * Return: non-zero if the initialization failed.
1843 int intel_logical_rings_init(struct drm_device
*dev
)
1845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1848 ret
= logical_render_ring_init(dev
);
1853 ret
= logical_bsd_ring_init(dev
);
1855 goto cleanup_render_ring
;
1859 ret
= logical_blt_ring_init(dev
);
1861 goto cleanup_bsd_ring
;
1864 if (HAS_VEBOX(dev
)) {
1865 ret
= logical_vebox_ring_init(dev
);
1867 goto cleanup_blt_ring
;
1870 if (HAS_BSD2(dev
)) {
1871 ret
= logical_bsd2_ring_init(dev
);
1873 goto cleanup_vebox_ring
;
1876 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
1878 goto cleanup_bsd2_ring
;
1883 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
1885 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
1887 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
1889 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
1890 cleanup_render_ring
:
1891 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
1897 make_rpcs(struct drm_device
*dev
)
1902 * No explicit RPCS request is needed to ensure full
1903 * slice/subslice/EU enablement prior to Gen9.
1905 if (INTEL_INFO(dev
)->gen
< 9)
1909 * Starting in Gen9, render power gating can leave
1910 * slice/subslice/EU in a partially enabled state. We
1911 * must make an explicit request through RPCS for full
1914 if (INTEL_INFO(dev
)->has_slice_pg
) {
1915 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1916 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
1917 GEN8_RPCS_S_CNT_SHIFT
;
1918 rpcs
|= GEN8_RPCS_ENABLE
;
1921 if (INTEL_INFO(dev
)->has_subslice_pg
) {
1922 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1923 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
1924 GEN8_RPCS_SS_CNT_SHIFT
;
1925 rpcs
|= GEN8_RPCS_ENABLE
;
1928 if (INTEL_INFO(dev
)->has_eu_pg
) {
1929 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
1930 GEN8_RPCS_EU_MIN_SHIFT
;
1931 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
1932 GEN8_RPCS_EU_MAX_SHIFT
;
1933 rpcs
|= GEN8_RPCS_ENABLE
;
1940 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
1941 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
1943 struct drm_device
*dev
= ring
->dev
;
1944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1945 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1947 uint32_t *reg_state
;
1951 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1953 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1955 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1959 ret
= i915_gem_object_get_pages(ctx_obj
);
1961 DRM_DEBUG_DRIVER("Could not get object pages\n");
1965 i915_gem_object_pin_pages(ctx_obj
);
1967 /* The second page of the context object contains some fields which must
1968 * be set up prior to the first execution. */
1969 page
= i915_gem_object_get_page(ctx_obj
, 1);
1970 reg_state
= kmap_atomic(page
);
1972 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1973 * commands followed by (reg, value) pairs. The values we are setting here are
1974 * only for the first context restore: on a subsequent save, the GPU will
1975 * recreate this batchbuffer with new values (including all the missing
1976 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1977 if (ring
->id
== RCS
)
1978 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
1980 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
1981 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
1982 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
1983 reg_state
[CTX_CONTEXT_CONTROL
+1] =
1984 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
1985 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
);
1986 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
1987 reg_state
[CTX_RING_HEAD
+1] = 0;
1988 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
1989 reg_state
[CTX_RING_TAIL
+1] = 0;
1990 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
1991 /* Ring buffer start address is not known until the buffer is pinned.
1992 * It is written to the context image in execlists_update_context()
1994 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
1995 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
1996 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
1997 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
1998 reg_state
[CTX_BB_HEAD_U
+1] = 0;
1999 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
2000 reg_state
[CTX_BB_HEAD_L
+1] = 0;
2001 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
2002 reg_state
[CTX_BB_STATE
+1] = (1<<5);
2003 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
2004 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
2005 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
2006 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
2007 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
2008 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
2009 if (ring
->id
== RCS
) {
2010 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
2011 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
2012 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
2013 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
2014 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
2015 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
2016 if (ring
->wa_ctx
.obj
) {
2017 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2018 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2020 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2021 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2022 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2024 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2025 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2027 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2028 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2032 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
2033 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
2034 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
2035 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
2036 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
2037 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
2038 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
2039 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
2040 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
2041 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
2042 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
2043 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
2045 /* With dynamic page allocation, PDPs may not be allocated at this point,
2046 * Point the unallocated PDPs to the scratch page
2048 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2049 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2050 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2051 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2052 if (ring
->id
== RCS
) {
2053 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2054 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
2055 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
2058 kunmap_atomic(reg_state
);
2061 set_page_dirty(page
);
2062 i915_gem_object_unpin_pages(ctx_obj
);
2068 * intel_lr_context_free() - free the LRC specific bits of a context
2069 * @ctx: the LR context to free.
2071 * The real context freeing is done in i915_gem_context_free: this only
2072 * takes care of the bits that are LRC related: the per-engine backing
2073 * objects and the logical ringbuffer.
2075 void intel_lr_context_free(struct intel_context
*ctx
)
2079 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2080 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2083 struct intel_ringbuffer
*ringbuf
=
2084 ctx
->engine
[i
].ringbuf
;
2085 struct intel_engine_cs
*ring
= ringbuf
->ring
;
2087 if (ctx
== ring
->default_context
) {
2088 intel_unpin_ringbuffer_obj(ringbuf
);
2089 i915_gem_object_ggtt_unpin(ctx_obj
);
2091 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
2092 intel_destroy_ringbuffer_obj(ringbuf
);
2094 drm_gem_object_unreference(&ctx_obj
->base
);
2099 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
2103 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2107 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2108 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2110 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2116 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2123 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2124 struct drm_i915_gem_object
*default_ctx_obj
)
2126 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2128 /* The status page is offset 0 from the default context object
2130 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
);
2131 ring
->status_page
.page_addr
=
2132 kmap(sg_page(default_ctx_obj
->pages
->sgl
));
2133 ring
->status_page
.obj
= default_ctx_obj
;
2135 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2136 (u32
)ring
->status_page
.gfx_addr
);
2137 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2141 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2142 * @ctx: LR context to create.
2143 * @ring: engine to be used with the context.
2145 * This function can be called more than once, with different engines, if we plan
2146 * to use the context with them. The context backing objects and the ringbuffers
2147 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2148 * the creation is a deferred call: it's better to make sure first that we need to use
2149 * a given ring with the context.
2151 * Return: non-zero on error.
2153 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
2154 struct intel_engine_cs
*ring
)
2156 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
2157 struct drm_device
*dev
= ring
->dev
;
2158 struct drm_i915_gem_object
*ctx_obj
;
2159 uint32_t context_size
;
2160 struct intel_ringbuffer
*ringbuf
;
2163 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2164 WARN_ON(ctx
->engine
[ring
->id
].state
);
2166 context_size
= round_up(get_lr_context_size(ring
), 4096);
2168 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2170 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2174 if (is_global_default_ctx
) {
2175 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
2177 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2179 drm_gem_object_unreference(&ctx_obj
->base
);
2184 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2186 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2189 goto error_unpin_ctx
;
2192 ringbuf
->ring
= ring
;
2194 ringbuf
->size
= 32 * PAGE_SIZE
;
2195 ringbuf
->effective_size
= ringbuf
->size
;
2198 ringbuf
->last_retired_head
= -1;
2199 intel_ring_update_space(ringbuf
);
2201 if (ringbuf
->obj
== NULL
) {
2202 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
2205 "Failed to allocate ringbuffer obj %s: %d\n",
2207 goto error_free_rbuf
;
2210 if (is_global_default_ctx
) {
2211 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2214 "Failed to pin and map ringbuffer %s: %d\n",
2216 goto error_destroy_rbuf
;
2222 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2224 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2228 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2229 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2231 if (ctx
== ring
->default_context
)
2232 lrc_setup_hardware_status_page(ring
, ctx_obj
);
2233 else if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
2234 if (ring
->init_context
) {
2235 struct drm_i915_gem_request
*req
;
2237 ret
= i915_gem_request_alloc(ring
, ctx
, &req
);
2241 ret
= ring
->init_context(req
);
2243 DRM_ERROR("ring init context: %d\n", ret
);
2244 i915_gem_request_cancel(req
);
2245 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2246 ctx
->engine
[ring
->id
].state
= NULL
;
2250 i915_add_request_no_flush(req
);
2253 ctx
->rcs_initialized
= true;
2259 if (is_global_default_ctx
)
2260 intel_unpin_ringbuffer_obj(ringbuf
);
2262 intel_destroy_ringbuffer_obj(ringbuf
);
2266 if (is_global_default_ctx
)
2267 i915_gem_object_ggtt_unpin(ctx_obj
);
2268 drm_gem_object_unreference(&ctx_obj
->base
);
2272 void intel_lr_context_reset(struct drm_device
*dev
,
2273 struct intel_context
*ctx
)
2275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2276 struct intel_engine_cs
*ring
;
2279 for_each_ring(ring
, dev_priv
, i
) {
2280 struct drm_i915_gem_object
*ctx_obj
=
2281 ctx
->engine
[ring
->id
].state
;
2282 struct intel_ringbuffer
*ringbuf
=
2283 ctx
->engine
[ring
->id
].ringbuf
;
2284 uint32_t *reg_state
;
2290 if (i915_gem_object_get_pages(ctx_obj
)) {
2291 WARN(1, "Failed get_pages for context obj\n");
2294 page
= i915_gem_object_get_page(ctx_obj
, 1);
2295 reg_state
= kmap_atomic(page
);
2297 reg_state
[CTX_RING_HEAD
+1] = 0;
2298 reg_state
[CTX_RING_TAIL
+1] = 0;
2300 kunmap_atomic(reg_state
);