2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
194 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
195 (reg_state)[(pos)+1] = (val); \
198 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
199 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
200 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
201 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
204 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
205 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
206 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
210 ADVANCED_CONTEXT
= 0,
215 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
216 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
217 LEGACY_64B_CONTEXT :\
221 FAULT_AND_HALT
, /* Debug only */
223 FAULT_AND_CONTINUE
/* Unsupported */
225 #define GEN8_CTX_ID_SHIFT 32
226 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
);
229 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
230 struct drm_i915_gem_object
*default_ctx_obj
);
234 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
236 * @enable_execlists: value of i915.enable_execlists module parameter.
238 * Only certain platforms support Execlists (the prerequisites being
239 * support for Logical Ring Contexts and Aliasing PPGTT or better).
241 * Return: 1 if Execlists is supported and has to be enabled.
243 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
245 WARN_ON(i915
.enable_ppgtt
== -1);
247 /* On platforms with execlist available, vGPU will only
248 * support execlist mode, no ring buffer mode.
250 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
253 if (INTEL_INFO(dev
)->gen
>= 9)
256 if (enable_execlists
== 0)
259 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
260 i915
.use_mmio_flip
>= 0)
267 * intel_execlists_ctx_id() - get the Execlists Context ID
268 * @ctx_obj: Logical Ring Context backing object.
270 * Do not confuse with ctx->id! Unfortunately we have a name overload
271 * here: the old context ID we pass to userspace as a handler so that
272 * they can refer to a context, and the new context ID we pass to the
273 * ELSP so that the GPU can inform us of the context status via
276 * Return: 20-bits globally unique context ID.
278 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
280 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
) +
281 LRC_PPHWSP_PN
* PAGE_SIZE
;
283 /* LRCA is required to be 4K aligned so the more significant 20 bits
284 * are globally unique */
288 static bool disable_lite_restore_wa(struct intel_engine_cs
*ring
)
290 struct drm_device
*dev
= ring
->dev
;
292 return (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
293 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) &&
294 (ring
->id
== VCS
|| ring
->id
== VCS2
);
297 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
298 struct intel_engine_cs
*ring
)
300 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
302 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
) +
303 LRC_PPHWSP_PN
* PAGE_SIZE
;
305 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
307 desc
= GEN8_CTX_VALID
;
308 desc
|= GEN8_CTX_ADDRESSING_MODE(dev
) << GEN8_CTX_ADDRESSING_MODE_SHIFT
;
309 if (IS_GEN8(ctx_obj
->base
.dev
))
310 desc
|= GEN8_CTX_L3LLC_COHERENT
;
311 desc
|= GEN8_CTX_PRIVILEGE
;
313 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
315 /* TODO: WaDisableLiteRestore when we start using semaphore
316 * signalling between Command Streamers */
317 /* desc |= GEN8_CTX_FORCE_RESTORE; */
319 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
320 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
321 if (disable_lite_restore_wa(ring
))
322 desc
|= GEN8_CTX_FORCE_RESTORE
;
327 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
328 struct drm_i915_gem_request
*rq1
)
331 struct intel_engine_cs
*ring
= rq0
->ring
;
332 struct drm_device
*dev
= ring
->dev
;
333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
337 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->ring
);
338 rq1
->elsp_submitted
++;
343 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->ring
);
344 rq0
->elsp_submitted
++;
346 /* You must always write both descriptors in the order below. */
347 spin_lock(&dev_priv
->uncore
.lock
);
348 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
349 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[1]));
350 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[1]));
352 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[0]));
353 /* The context is automatically loaded after the following */
354 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[0]));
356 /* ELSP is a wo register, use another nearby reg for posting */
357 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring
));
358 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
359 spin_unlock(&dev_priv
->uncore
.lock
);
362 static int execlists_update_context(struct drm_i915_gem_request
*rq
)
364 struct intel_engine_cs
*ring
= rq
->ring
;
365 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
366 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
367 struct drm_i915_gem_object
*rb_obj
= rq
->ringbuf
->obj
;
372 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj
));
373 WARN_ON(!i915_gem_obj_is_pinned(rb_obj
));
375 page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
376 reg_state
= kmap_atomic(page
);
378 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
379 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(rb_obj
);
381 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
382 /* True 32b PPGTT with dynamic page allocation: update PDP
383 * registers and point the unallocated PDPs to scratch page.
384 * PML4 is allocated during ppgtt init, so this is not needed
387 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
388 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
389 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
390 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
393 kunmap_atomic(reg_state
);
398 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
399 struct drm_i915_gem_request
*rq1
)
401 execlists_update_context(rq0
);
404 execlists_update_context(rq1
);
406 execlists_elsp_write(rq0
, rq1
);
409 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
411 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
412 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
414 assert_spin_locked(&ring
->execlist_lock
);
417 * If irqs are not active generate a warning as batches that finish
418 * without the irqs may get lost and a GPU Hang may occur.
420 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
422 if (list_empty(&ring
->execlist_queue
))
425 /* Try to read in pairs */
426 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
430 } else if (req0
->ctx
== cursor
->ctx
) {
431 /* Same ctx: ignore first request, as second request
432 * will update tail past first request's workload */
433 cursor
->elsp_submitted
= req0
->elsp_submitted
;
434 list_del(&req0
->execlist_link
);
435 list_add_tail(&req0
->execlist_link
,
436 &ring
->execlist_retired_req_list
);
444 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
446 * WaIdleLiteRestore: make sure we never cause a lite
447 * restore with HEAD==TAIL
449 if (req0
->elsp_submitted
) {
451 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
452 * as we resubmit the request. See gen8_emit_request()
453 * for where we prepare the padding after the end of the
456 struct intel_ringbuffer
*ringbuf
;
458 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
460 req0
->tail
&= ringbuf
->size
- 1;
464 WARN_ON(req1
&& req1
->elsp_submitted
);
466 execlists_submit_requests(req0
, req1
);
469 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
472 struct drm_i915_gem_request
*head_req
;
474 assert_spin_locked(&ring
->execlist_lock
);
476 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
477 struct drm_i915_gem_request
,
480 if (head_req
!= NULL
) {
481 struct drm_i915_gem_object
*ctx_obj
=
482 head_req
->ctx
->engine
[ring
->id
].state
;
483 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
484 WARN(head_req
->elsp_submitted
== 0,
485 "Never submitted head request\n");
487 if (--head_req
->elsp_submitted
<= 0) {
488 list_del(&head_req
->execlist_link
);
489 list_add_tail(&head_req
->execlist_link
,
490 &ring
->execlist_retired_req_list
);
500 * intel_lrc_irq_handler() - handle Context Switch interrupts
501 * @ring: Engine Command Streamer to handle.
503 * Check the unread Context Status Buffers and manage the submission of new
504 * contexts to the ELSP accordingly.
506 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
508 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
514 u32 submit_contexts
= 0;
516 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
518 read_pointer
= ring
->next_context_status_buffer
;
519 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
520 if (read_pointer
> write_pointer
)
521 write_pointer
+= GEN8_CSB_ENTRIES
;
523 spin_lock(&ring
->execlist_lock
);
525 while (read_pointer
< write_pointer
) {
527 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring
, read_pointer
% GEN8_CSB_ENTRIES
));
528 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring
, read_pointer
% GEN8_CSB_ENTRIES
));
530 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
533 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
534 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
535 if (execlists_check_remove_request(ring
, status_id
))
536 WARN(1, "Lite Restored request removed from queue\n");
538 WARN(1, "Preemption without Lite Restore\n");
541 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
542 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
543 if (execlists_check_remove_request(ring
, status_id
))
548 if (disable_lite_restore_wa(ring
)) {
549 /* Prevent a ctx to preempt itself */
550 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) &&
551 (submit_contexts
!= 0))
552 execlists_context_unqueue(ring
);
553 } else if (submit_contexts
!= 0) {
554 execlists_context_unqueue(ring
);
557 spin_unlock(&ring
->execlist_lock
);
559 WARN(submit_contexts
> 2, "More than two context complete events?\n");
560 ring
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
562 /* Update the read pointer to the old write pointer. Manual ringbuffer
563 * management ftw </sarcasm> */
564 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
565 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
566 ring
->next_context_status_buffer
<< 8));
569 static int execlists_context_queue(struct drm_i915_gem_request
*request
)
571 struct intel_engine_cs
*ring
= request
->ring
;
572 struct drm_i915_gem_request
*cursor
;
573 int num_elements
= 0;
575 if (request
->ctx
!= ring
->default_context
)
576 intel_lr_context_pin(request
);
578 i915_gem_request_reference(request
);
580 spin_lock_irq(&ring
->execlist_lock
);
582 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
583 if (++num_elements
> 2)
586 if (num_elements
> 2) {
587 struct drm_i915_gem_request
*tail_req
;
589 tail_req
= list_last_entry(&ring
->execlist_queue
,
590 struct drm_i915_gem_request
,
593 if (request
->ctx
== tail_req
->ctx
) {
594 WARN(tail_req
->elsp_submitted
!= 0,
595 "More than 2 already-submitted reqs queued\n");
596 list_del(&tail_req
->execlist_link
);
597 list_add_tail(&tail_req
->execlist_link
,
598 &ring
->execlist_retired_req_list
);
602 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
603 if (num_elements
== 0)
604 execlists_context_unqueue(ring
);
606 spin_unlock_irq(&ring
->execlist_lock
);
611 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
613 struct intel_engine_cs
*ring
= req
->ring
;
614 uint32_t flush_domains
;
618 if (ring
->gpu_caches_dirty
)
619 flush_domains
= I915_GEM_GPU_DOMAINS
;
621 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
625 ring
->gpu_caches_dirty
= false;
629 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
630 struct list_head
*vmas
)
632 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
633 struct i915_vma
*vma
;
634 uint32_t flush_domains
= 0;
635 bool flush_chipset
= false;
638 list_for_each_entry(vma
, vmas
, exec_list
) {
639 struct drm_i915_gem_object
*obj
= vma
->obj
;
641 if (obj
->active
& other_rings
) {
642 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
647 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
648 flush_chipset
|= i915_gem_clflush_object(obj
, false);
650 flush_domains
|= obj
->base
.write_domain
;
653 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
656 /* Unconditionally invalidate gpu caches and ensure that we do flush
657 * any residual writes from the previous batch.
659 return logical_ring_invalidate_all_caches(req
);
662 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
666 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
668 if (request
->ctx
!= request
->ring
->default_context
) {
669 ret
= intel_lr_context_pin(request
);
674 if (i915
.enable_guc_submission
) {
676 * Check that the GuC has space for the request before
677 * going any further, as the i915_add_request() call
678 * later on mustn't fail ...
680 struct intel_guc
*guc
= &request
->i915
->guc
;
682 ret
= i915_guc_wq_check_space(guc
->execbuf_client
);
690 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
693 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
694 struct intel_engine_cs
*ring
= req
->ring
;
695 struct drm_i915_gem_request
*target
;
699 if (intel_ring_space(ringbuf
) >= bytes
)
702 /* The whole point of reserving space is to not wait! */
703 WARN_ON(ringbuf
->reserved_in_use
);
705 list_for_each_entry(target
, &ring
->request_list
, list
) {
707 * The request queue is per-engine, so can contain requests
708 * from multiple ringbuffers. Here, we must ignore any that
709 * aren't from the ringbuffer we're considering.
711 if (target
->ringbuf
!= ringbuf
)
714 /* Would completion of this request free enough space? */
715 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
721 if (WARN_ON(&target
->list
== &ring
->request_list
))
724 ret
= i915_wait_request(target
);
728 ringbuf
->space
= space
;
733 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
734 * @request: Request to advance the logical ringbuffer of.
736 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
737 * really happens during submission is that the context and current tail will be placed
738 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
739 * point, the tail *inside* the context is updated and the ELSP written to.
742 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
744 struct intel_engine_cs
*ring
= request
->ring
;
745 struct drm_i915_private
*dev_priv
= request
->i915
;
747 intel_logical_ring_advance(request
->ringbuf
);
749 request
->tail
= request
->ringbuf
->tail
;
751 if (intel_ring_stopped(ring
))
754 if (dev_priv
->guc
.execbuf_client
)
755 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
757 execlists_context_queue(request
);
760 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
762 uint32_t __iomem
*virt
;
763 int rem
= ringbuf
->size
- ringbuf
->tail
;
765 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
768 iowrite32(MI_NOOP
, virt
++);
771 intel_ring_update_space(ringbuf
);
774 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
776 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
777 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
778 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
779 int ret
, total_bytes
, wait_bytes
= 0;
780 bool need_wrap
= false;
782 if (ringbuf
->reserved_in_use
)
785 total_bytes
= bytes
+ ringbuf
->reserved_size
;
787 if (unlikely(bytes
> remain_usable
)) {
789 * Not enough space for the basic request. So need to flush
790 * out the remainder and then wait for base + reserved.
792 wait_bytes
= remain_actual
+ total_bytes
;
795 if (unlikely(total_bytes
> remain_usable
)) {
797 * The base request will fit but the reserved space
798 * falls off the end. So only need to to wait for the
799 * reserved size after flushing out the remainder.
801 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
803 } else if (total_bytes
> ringbuf
->space
) {
804 /* No wrapping required, just waiting. */
805 wait_bytes
= total_bytes
;
810 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
815 __wrap_ring_buffer(ringbuf
);
822 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
824 * @req: The request to start some new work for
825 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
827 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
828 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
829 * and also preallocates a request (every workload submission is still mediated through
830 * requests, same as it did with legacy ringbuffer submission).
832 * Return: non-zero if the ringbuffer is not ready to be written to.
834 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
836 struct drm_i915_private
*dev_priv
;
839 WARN_ON(req
== NULL
);
840 dev_priv
= req
->ring
->dev
->dev_private
;
842 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
843 dev_priv
->mm
.interruptible
);
847 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
851 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
855 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
858 * The first call merely notes the reserve request and is common for
859 * all back ends. The subsequent localised _begin() call actually
860 * ensures that the reservation is available. Without the begin, if
861 * the request creator immediately submitted the request without
862 * adding any commands to it then there might not actually be
863 * sufficient room for the submission commands.
865 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
867 return intel_logical_ring_begin(request
, 0);
871 * execlists_submission() - submit a batchbuffer for execution, Execlists style
874 * @ring: Engine Command Streamer to submit to.
875 * @ctx: Context to employ for this submission.
876 * @args: execbuffer call arguments.
877 * @vmas: list of vmas.
878 * @batch_obj: the batchbuffer to submit.
879 * @exec_start: batchbuffer start virtual address pointer.
880 * @dispatch_flags: translated execbuffer call flags.
882 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
883 * away the submission details of the execbuffer ioctl call.
885 * Return: non-zero if the submission fails.
887 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
888 struct drm_i915_gem_execbuffer2
*args
,
889 struct list_head
*vmas
)
891 struct drm_device
*dev
= params
->dev
;
892 struct intel_engine_cs
*ring
= params
->ring
;
893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
894 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
900 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
901 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
902 switch (instp_mode
) {
903 case I915_EXEC_CONSTANTS_REL_GENERAL
:
904 case I915_EXEC_CONSTANTS_ABSOLUTE
:
905 case I915_EXEC_CONSTANTS_REL_SURFACE
:
906 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
907 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
911 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
912 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
913 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
917 /* The HW changed the meaning on this bit on gen6 */
918 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
922 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
926 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
927 DRM_DEBUG("sol reset is gen7 only\n");
931 ret
= execlists_move_to_gpu(params
->request
, vmas
);
935 if (ring
== &dev_priv
->ring
[RCS
] &&
936 instp_mode
!= dev_priv
->relative_constants_mode
) {
937 ret
= intel_logical_ring_begin(params
->request
, 4);
941 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
942 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
943 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
944 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
945 intel_logical_ring_advance(ringbuf
);
947 dev_priv
->relative_constants_mode
= instp_mode
;
950 exec_start
= params
->batch_obj_vm_offset
+
951 args
->batch_start_offset
;
953 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
957 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
959 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
960 i915_gem_execbuffer_retire_commands(params
);
965 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
967 struct drm_i915_gem_request
*req
, *tmp
;
968 struct list_head retired_list
;
970 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
971 if (list_empty(&ring
->execlist_retired_req_list
))
974 INIT_LIST_HEAD(&retired_list
);
975 spin_lock_irq(&ring
->execlist_lock
);
976 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
977 spin_unlock_irq(&ring
->execlist_lock
);
979 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
980 struct intel_context
*ctx
= req
->ctx
;
981 struct drm_i915_gem_object
*ctx_obj
=
982 ctx
->engine
[ring
->id
].state
;
984 if (ctx_obj
&& (ctx
!= ring
->default_context
))
985 intel_lr_context_unpin(req
);
986 list_del(&req
->execlist_link
);
987 i915_gem_request_unreference(req
);
991 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
993 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
996 if (!intel_ring_initialized(ring
))
999 ret
= intel_ring_idle(ring
);
1000 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
1001 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1004 /* TODO: Is this correct with Execlists enabled? */
1005 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
1006 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
1007 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
1010 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
1013 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
1015 struct intel_engine_cs
*ring
= req
->ring
;
1018 if (!ring
->gpu_caches_dirty
)
1021 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
1025 ring
->gpu_caches_dirty
= false;
1029 static int intel_lr_context_do_pin(struct intel_engine_cs
*ring
,
1030 struct drm_i915_gem_object
*ctx_obj
,
1031 struct intel_ringbuffer
*ringbuf
)
1033 struct drm_device
*dev
= ring
->dev
;
1034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1037 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1038 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
1039 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
1043 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1047 ctx_obj
->dirty
= true;
1049 /* Invalidate GuC TLB. */
1050 if (i915
.enable_guc_submission
)
1051 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1056 i915_gem_object_ggtt_unpin(ctx_obj
);
1061 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
)
1064 struct intel_engine_cs
*ring
= rq
->ring
;
1065 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1066 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1068 if (rq
->ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1069 ret
= intel_lr_context_do_pin(ring
, ctx_obj
, ringbuf
);
1071 goto reset_pin_count
;
1076 rq
->ctx
->engine
[ring
->id
].pin_count
= 0;
1080 void intel_lr_context_unpin(struct drm_i915_gem_request
*rq
)
1082 struct intel_engine_cs
*ring
= rq
->ring
;
1083 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1084 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1087 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1088 if (--rq
->ctx
->engine
[ring
->id
].pin_count
== 0) {
1089 intel_unpin_ringbuffer_obj(ringbuf
);
1090 i915_gem_object_ggtt_unpin(ctx_obj
);
1095 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1098 struct intel_engine_cs
*ring
= req
->ring
;
1099 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1100 struct drm_device
*dev
= ring
->dev
;
1101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1102 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1104 if (WARN_ON_ONCE(w
->count
== 0))
1107 ring
->gpu_caches_dirty
= true;
1108 ret
= logical_ring_flush_all_caches(req
);
1112 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1116 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1117 for (i
= 0; i
< w
->count
; i
++) {
1118 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1119 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1121 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1123 intel_logical_ring_advance(ringbuf
);
1125 ring
->gpu_caches_dirty
= true;
1126 ret
= logical_ring_flush_all_caches(req
);
1133 #define wa_ctx_emit(batch, index, cmd) \
1135 int __index = (index)++; \
1136 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1139 batch[__index] = (cmd); \
1142 #define wa_ctx_emit_reg(batch, index, reg) \
1143 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1146 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1147 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1148 * but there is a slight complication as this is applied in WA batch where the
1149 * values are only initialized once so we cannot take register value at the
1150 * beginning and reuse it further; hence we save its value to memory, upload a
1151 * constant value with bit21 set and then we restore it back with the saved value.
1152 * To simplify the WA, a constant value is formed by using the default value
1153 * of this register. This shouldn't be a problem because we are only modifying
1154 * it for a short period and this batch in non-premptible. We can ofcourse
1155 * use additional instructions that read the actual value of the register
1156 * at that time and set our bit of interest but it makes the WA complicated.
1158 * This WA is also required for Gen9 so extracting as a function avoids
1161 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*ring
,
1162 uint32_t *const batch
,
1165 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1168 * WaDisableLSQCROPERFforOCL:skl
1169 * This WA is implemented in skl_init_clock_gating() but since
1170 * this batch updates GEN8_L3SQCREG4 with default value we need to
1171 * set this bit here to retain the WA during flush.
1173 if (IS_SKL_REVID(ring
->dev
, 0, SKL_REVID_E0
))
1174 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1176 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1177 MI_SRM_LRM_GLOBAL_GTT
));
1178 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1179 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1180 wa_ctx_emit(batch
, index
, 0);
1182 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1183 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1184 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1186 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1187 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1188 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1189 wa_ctx_emit(batch
, index
, 0);
1190 wa_ctx_emit(batch
, index
, 0);
1191 wa_ctx_emit(batch
, index
, 0);
1192 wa_ctx_emit(batch
, index
, 0);
1194 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1195 MI_SRM_LRM_GLOBAL_GTT
));
1196 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1197 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1198 wa_ctx_emit(batch
, index
, 0);
1203 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1205 uint32_t start_alignment
)
1207 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1210 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1212 uint32_t size_alignment
)
1214 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1216 WARN(wa_ctx
->size
% size_alignment
,
1217 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1218 wa_ctx
->size
, size_alignment
);
1223 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1225 * @ring: only applicable for RCS
1226 * @wa_ctx: structure representing wa_ctx
1227 * offset: specifies start of the batch, should be cache-aligned. This is updated
1228 * with the offset value received as input.
1229 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1230 * @batch: page in which WA are loaded
1231 * @offset: This field specifies the start of the batch, it should be
1232 * cache-aligned otherwise it is adjusted accordingly.
1233 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1234 * initialized at the beginning and shared across all contexts but this field
1235 * helps us to have multiple batches at different offsets and select them based
1236 * on a criteria. At the moment this batch always start at the beginning of the page
1237 * and at this point we don't have multiple wa_ctx batch buffers.
1239 * The number of WA applied are not known at the beginning; we use this field
1240 * to return the no of DWORDS written.
1242 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1243 * so it adds NOOPs as padding to make it cacheline aligned.
1244 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1245 * makes a complete batch buffer.
1247 * Return: non-zero if we exceed the PAGE_SIZE limit.
1250 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1251 struct i915_wa_ctx_bb
*wa_ctx
,
1252 uint32_t *const batch
,
1255 uint32_t scratch_addr
;
1256 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1258 /* WaDisableCtxRestoreArbitration:bdw,chv */
1259 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1261 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1262 if (IS_BROADWELL(ring
->dev
)) {
1263 int rc
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1269 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1270 /* Actual scratch location is at 128 bytes offset */
1271 scratch_addr
= ring
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1273 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1274 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1275 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1276 PIPE_CONTROL_CS_STALL
|
1277 PIPE_CONTROL_QW_WRITE
));
1278 wa_ctx_emit(batch
, index
, scratch_addr
);
1279 wa_ctx_emit(batch
, index
, 0);
1280 wa_ctx_emit(batch
, index
, 0);
1281 wa_ctx_emit(batch
, index
, 0);
1283 /* Pad to end of cacheline */
1284 while (index
% CACHELINE_DWORDS
)
1285 wa_ctx_emit(batch
, index
, MI_NOOP
);
1288 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1289 * execution depends on the length specified in terms of cache lines
1290 * in the register CTX_RCS_INDIRECT_CTX
1293 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1297 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1299 * @ring: only applicable for RCS
1300 * @wa_ctx: structure representing wa_ctx
1301 * offset: specifies start of the batch, should be cache-aligned.
1302 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1303 * @batch: page in which WA are loaded
1304 * @offset: This field specifies the start of this batch.
1305 * This batch is started immediately after indirect_ctx batch. Since we ensure
1306 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1308 * The number of DWORDS written are returned using this field.
1310 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1311 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1313 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1314 struct i915_wa_ctx_bb
*wa_ctx
,
1315 uint32_t *const batch
,
1318 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1320 /* WaDisableCtxRestoreArbitration:bdw,chv */
1321 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1323 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1325 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1328 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1329 struct i915_wa_ctx_bb
*wa_ctx
,
1330 uint32_t *const batch
,
1334 struct drm_device
*dev
= ring
->dev
;
1335 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1337 /* WaDisableCtxRestoreArbitration:skl,bxt */
1338 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1339 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1340 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1342 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1343 ret
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1348 /* Pad to end of cacheline */
1349 while (index
% CACHELINE_DWORDS
)
1350 wa_ctx_emit(batch
, index
, MI_NOOP
);
1352 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1355 static int gen9_init_perctx_bb(struct intel_engine_cs
*ring
,
1356 struct i915_wa_ctx_bb
*wa_ctx
,
1357 uint32_t *const batch
,
1360 struct drm_device
*dev
= ring
->dev
;
1361 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1363 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1364 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
1365 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1366 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1367 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1368 wa_ctx_emit(batch
, index
,
1369 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1370 wa_ctx_emit(batch
, index
, MI_NOOP
);
1373 /* WaDisableCtxRestoreArbitration:skl,bxt */
1374 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1375 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1376 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1378 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1380 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1383 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1387 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1388 if (!ring
->wa_ctx
.obj
) {
1389 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1393 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1395 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1397 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1404 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1406 if (ring
->wa_ctx
.obj
) {
1407 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1408 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1409 ring
->wa_ctx
.obj
= NULL
;
1413 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1419 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1421 WARN_ON(ring
->id
!= RCS
);
1423 /* update this when WA for higher Gen are added */
1424 if (INTEL_INFO(ring
->dev
)->gen
> 9) {
1425 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1426 INTEL_INFO(ring
->dev
)->gen
);
1430 /* some WA perform writes to scratch page, ensure it is valid */
1431 if (ring
->scratch
.obj
== NULL
) {
1432 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1436 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1438 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1442 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1443 batch
= kmap_atomic(page
);
1446 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1447 ret
= gen8_init_indirectctx_bb(ring
,
1448 &wa_ctx
->indirect_ctx
,
1454 ret
= gen8_init_perctx_bb(ring
,
1460 } else if (INTEL_INFO(ring
->dev
)->gen
== 9) {
1461 ret
= gen9_init_indirectctx_bb(ring
,
1462 &wa_ctx
->indirect_ctx
,
1468 ret
= gen9_init_perctx_bb(ring
,
1477 kunmap_atomic(batch
);
1479 lrc_destroy_wa_ctx_obj(ring
);
1484 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1486 struct drm_device
*dev
= ring
->dev
;
1487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1488 u8 next_context_status_buffer_hw
;
1490 lrc_setup_hardware_status_page(ring
,
1491 ring
->default_context
->engine
[ring
->id
].state
);
1493 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1494 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1496 I915_WRITE(RING_MODE_GEN7(ring
),
1497 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1498 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1499 POSTING_READ(RING_MODE_GEN7(ring
));
1502 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1503 * zero, we need to read the write pointer from hardware and use its
1504 * value because "this register is power context save restored".
1505 * Effectively, these states have been observed:
1507 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1508 * BDW | CSB regs not reset | CSB regs reset |
1509 * CHT | CSB regs not reset | CSB regs not reset |
1513 next_context_status_buffer_hw
=
1514 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(ring
)));
1517 * When the CSB registers are reset (also after power-up / gpu reset),
1518 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1519 * this special case, so the first element read is CSB[0].
1521 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1522 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1524 ring
->next_context_status_buffer
= next_context_status_buffer_hw
;
1525 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1527 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1532 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1534 struct drm_device
*dev
= ring
->dev
;
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1538 ret
= gen8_init_common_ring(ring
);
1542 /* We need to disable the AsyncFlip performance optimisations in order
1543 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1544 * programmed to '1' on all products.
1546 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1548 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1550 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1552 return init_workarounds_ring(ring
);
1555 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1559 ret
= gen8_init_common_ring(ring
);
1563 return init_workarounds_ring(ring
);
1566 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1568 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1569 struct intel_engine_cs
*ring
= req
->ring
;
1570 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1571 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1574 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1578 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1579 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1580 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1582 intel_logical_ring_emit_reg(ringbuf
, GEN8_RING_PDP_UDW(ring
, i
));
1583 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1584 intel_logical_ring_emit_reg(ringbuf
, GEN8_RING_PDP_LDW(ring
, i
));
1585 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1588 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1589 intel_logical_ring_advance(ringbuf
);
1594 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1595 u64 offset
, unsigned dispatch_flags
)
1597 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1598 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1601 /* Don't rely in hw updating PDPs, specially in lite-restore.
1602 * Ideally, we should set Force PD Restore in ctx descriptor,
1603 * but we can't. Force Restore would be a second option, but
1604 * it is unsafe in case of lite-restore (because the ctx is
1605 * not idle). PML4 is allocated during ppgtt init so this is
1606 * not needed in 48-bit.*/
1607 if (req
->ctx
->ppgtt
&&
1608 (intel_ring_flag(req
->ring
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1609 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1610 !intel_vgpu_active(req
->i915
->dev
)) {
1611 ret
= intel_logical_ring_emit_pdps(req
);
1616 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(req
->ring
);
1619 ret
= intel_logical_ring_begin(req
, 4);
1623 /* FIXME(BDW): Address space and security selectors. */
1624 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1626 (dispatch_flags
& I915_DISPATCH_RS
?
1627 MI_BATCH_RESOURCE_STREAMER
: 0));
1628 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1629 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1630 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1631 intel_logical_ring_advance(ringbuf
);
1636 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1638 struct drm_device
*dev
= ring
->dev
;
1639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1640 unsigned long flags
;
1642 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1645 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1646 if (ring
->irq_refcount
++ == 0) {
1647 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1648 POSTING_READ(RING_IMR(ring
->mmio_base
));
1650 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1655 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1657 struct drm_device
*dev
= ring
->dev
;
1658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1659 unsigned long flags
;
1661 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1662 if (--ring
->irq_refcount
== 0) {
1663 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1664 POSTING_READ(RING_IMR(ring
->mmio_base
));
1666 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1669 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1670 u32 invalidate_domains
,
1673 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1674 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1675 struct drm_device
*dev
= ring
->dev
;
1676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1680 ret
= intel_logical_ring_begin(request
, 4);
1684 cmd
= MI_FLUSH_DW
+ 1;
1686 /* We always require a command barrier so that subsequent
1687 * commands, such as breadcrumb interrupts, are strictly ordered
1688 * wrt the contents of the write cache being flushed to memory
1689 * (and thus being coherent from the CPU).
1691 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1693 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1694 cmd
|= MI_INVALIDATE_TLB
;
1695 if (ring
== &dev_priv
->ring
[VCS
])
1696 cmd
|= MI_INVALIDATE_BSD
;
1699 intel_logical_ring_emit(ringbuf
, cmd
);
1700 intel_logical_ring_emit(ringbuf
,
1701 I915_GEM_HWS_SCRATCH_ADDR
|
1702 MI_FLUSH_DW_USE_GTT
);
1703 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1704 intel_logical_ring_emit(ringbuf
, 0); /* value */
1705 intel_logical_ring_advance(ringbuf
);
1710 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1711 u32 invalidate_domains
,
1714 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1715 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1716 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1717 bool vf_flush_wa
= false;
1721 flags
|= PIPE_CONTROL_CS_STALL
;
1723 if (flush_domains
) {
1724 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1725 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1726 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1729 if (invalidate_domains
) {
1730 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1731 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1732 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1733 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1734 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1735 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1736 flags
|= PIPE_CONTROL_QW_WRITE
;
1737 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1740 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1743 if (IS_GEN9(ring
->dev
))
1747 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1752 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1753 intel_logical_ring_emit(ringbuf
, 0);
1754 intel_logical_ring_emit(ringbuf
, 0);
1755 intel_logical_ring_emit(ringbuf
, 0);
1756 intel_logical_ring_emit(ringbuf
, 0);
1757 intel_logical_ring_emit(ringbuf
, 0);
1760 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1761 intel_logical_ring_emit(ringbuf
, flags
);
1762 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1763 intel_logical_ring_emit(ringbuf
, 0);
1764 intel_logical_ring_emit(ringbuf
, 0);
1765 intel_logical_ring_emit(ringbuf
, 0);
1766 intel_logical_ring_advance(ringbuf
);
1771 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1773 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1776 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1778 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1781 static u32
bxt_a_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1785 * On BXT A steppings there is a HW coherency issue whereby the
1786 * MI_STORE_DATA_IMM storing the completed request's seqno
1787 * occasionally doesn't invalidate the CPU cache. Work around this by
1788 * clflushing the corresponding cacheline whenever the caller wants
1789 * the coherency to be guaranteed. Note that this cacheline is known
1790 * to be clean at this point, since we only write it in
1791 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1792 * this clflush in practice becomes an invalidate operation.
1795 if (!lazy_coherency
)
1796 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1798 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1801 static void bxt_a_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1803 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1805 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1806 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1809 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1811 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1812 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1817 * Reserve space for 2 NOOPs at the end of each request to be
1818 * used as a workaround for not being allowed to do lite
1819 * restore with HEAD==TAIL (WaIdleLiteRestore).
1821 ret
= intel_logical_ring_begin(request
, 8);
1825 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1826 cmd
|= MI_GLOBAL_GTT
;
1828 intel_logical_ring_emit(ringbuf
, cmd
);
1829 intel_logical_ring_emit(ringbuf
,
1830 (ring
->status_page
.gfx_addr
+
1831 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1832 intel_logical_ring_emit(ringbuf
, 0);
1833 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1834 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1835 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1836 intel_logical_ring_advance_and_submit(request
);
1839 * Here we add two extra NOOPs as padding to avoid
1840 * lite restore of a context with HEAD==TAIL.
1842 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1843 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1844 intel_logical_ring_advance(ringbuf
);
1849 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1851 struct render_state so
;
1854 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1858 if (so
.rodata
== NULL
)
1861 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1862 I915_DISPATCH_SECURE
);
1866 ret
= req
->ring
->emit_bb_start(req
,
1867 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1868 I915_DISPATCH_SECURE
);
1872 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1875 i915_gem_render_state_fini(&so
);
1879 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1883 ret
= intel_logical_ring_workarounds_emit(req
);
1887 ret
= intel_rcs_context_init_mocs(req
);
1889 * Failing to program the MOCS is non-fatal.The system will not
1890 * run at peak performance. So generate an error and carry on.
1893 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1895 return intel_lr_context_render_state_init(req
);
1899 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1901 * @ring: Engine Command Streamer.
1904 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1906 struct drm_i915_private
*dev_priv
;
1908 if (!intel_ring_initialized(ring
))
1911 dev_priv
= ring
->dev
->dev_private
;
1914 intel_logical_ring_stop(ring
);
1915 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1919 ring
->cleanup(ring
);
1921 i915_cmd_parser_fini_ring(ring
);
1922 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1924 if (ring
->status_page
.obj
) {
1925 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1926 ring
->status_page
.obj
= NULL
;
1929 lrc_destroy_wa_ctx_obj(ring
);
1933 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1937 /* Intentionally left blank. */
1938 ring
->buffer
= NULL
;
1941 INIT_LIST_HEAD(&ring
->active_list
);
1942 INIT_LIST_HEAD(&ring
->request_list
);
1943 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1944 init_waitqueue_head(&ring
->irq_queue
);
1946 INIT_LIST_HEAD(&ring
->buffers
);
1947 INIT_LIST_HEAD(&ring
->execlist_queue
);
1948 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1949 spin_lock_init(&ring
->execlist_lock
);
1951 ret
= i915_cmd_parser_init_ring(ring
);
1955 ret
= intel_lr_context_deferred_alloc(ring
->default_context
, ring
);
1959 /* As this is the default context, always pin it */
1960 ret
= intel_lr_context_do_pin(
1962 ring
->default_context
->engine
[ring
->id
].state
,
1963 ring
->default_context
->engine
[ring
->id
].ringbuf
);
1966 "Failed to pin and map ringbuffer %s: %d\n",
1974 intel_logical_ring_cleanup(ring
);
1978 static int logical_render_ring_init(struct drm_device
*dev
)
1980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1981 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1984 ring
->name
= "render ring";
1986 ring
->mmio_base
= RENDER_RING_BASE
;
1987 ring
->irq_enable_mask
=
1988 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1989 ring
->irq_keep_mask
=
1990 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1991 if (HAS_L3_DPF(dev
))
1992 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1994 if (INTEL_INFO(dev
)->gen
>= 9)
1995 ring
->init_hw
= gen9_init_render_ring
;
1997 ring
->init_hw
= gen8_init_render_ring
;
1998 ring
->init_context
= gen8_init_rcs_context
;
1999 ring
->cleanup
= intel_fini_pipe_control
;
2000 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
2001 ring
->get_seqno
= bxt_a_get_seqno
;
2002 ring
->set_seqno
= bxt_a_set_seqno
;
2004 ring
->get_seqno
= gen8_get_seqno
;
2005 ring
->set_seqno
= gen8_set_seqno
;
2007 ring
->emit_request
= gen8_emit_request
;
2008 ring
->emit_flush
= gen8_emit_flush_render
;
2009 ring
->irq_get
= gen8_logical_ring_get_irq
;
2010 ring
->irq_put
= gen8_logical_ring_put_irq
;
2011 ring
->emit_bb_start
= gen8_emit_bb_start
;
2015 ret
= intel_init_pipe_control(ring
);
2019 ret
= intel_init_workaround_bb(ring
);
2022 * We continue even if we fail to initialize WA batch
2023 * because we only expect rare glitches but nothing
2024 * critical to prevent us from using GPU
2026 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2030 ret
= logical_ring_init(dev
, ring
);
2032 lrc_destroy_wa_ctx_obj(ring
);
2038 static int logical_bsd_ring_init(struct drm_device
*dev
)
2040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2041 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2043 ring
->name
= "bsd ring";
2045 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2046 ring
->irq_enable_mask
=
2047 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2048 ring
->irq_keep_mask
=
2049 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2051 ring
->init_hw
= gen8_init_common_ring
;
2052 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
2053 ring
->get_seqno
= bxt_a_get_seqno
;
2054 ring
->set_seqno
= bxt_a_set_seqno
;
2056 ring
->get_seqno
= gen8_get_seqno
;
2057 ring
->set_seqno
= gen8_set_seqno
;
2059 ring
->emit_request
= gen8_emit_request
;
2060 ring
->emit_flush
= gen8_emit_flush
;
2061 ring
->irq_get
= gen8_logical_ring_get_irq
;
2062 ring
->irq_put
= gen8_logical_ring_put_irq
;
2063 ring
->emit_bb_start
= gen8_emit_bb_start
;
2065 return logical_ring_init(dev
, ring
);
2068 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2071 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2073 ring
->name
= "bds2 ring";
2075 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2076 ring
->irq_enable_mask
=
2077 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2078 ring
->irq_keep_mask
=
2079 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2081 ring
->init_hw
= gen8_init_common_ring
;
2082 ring
->get_seqno
= gen8_get_seqno
;
2083 ring
->set_seqno
= gen8_set_seqno
;
2084 ring
->emit_request
= gen8_emit_request
;
2085 ring
->emit_flush
= gen8_emit_flush
;
2086 ring
->irq_get
= gen8_logical_ring_get_irq
;
2087 ring
->irq_put
= gen8_logical_ring_put_irq
;
2088 ring
->emit_bb_start
= gen8_emit_bb_start
;
2090 return logical_ring_init(dev
, ring
);
2093 static int logical_blt_ring_init(struct drm_device
*dev
)
2095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2096 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2098 ring
->name
= "blitter ring";
2100 ring
->mmio_base
= BLT_RING_BASE
;
2101 ring
->irq_enable_mask
=
2102 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2103 ring
->irq_keep_mask
=
2104 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2106 ring
->init_hw
= gen8_init_common_ring
;
2107 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
2108 ring
->get_seqno
= bxt_a_get_seqno
;
2109 ring
->set_seqno
= bxt_a_set_seqno
;
2111 ring
->get_seqno
= gen8_get_seqno
;
2112 ring
->set_seqno
= gen8_set_seqno
;
2114 ring
->emit_request
= gen8_emit_request
;
2115 ring
->emit_flush
= gen8_emit_flush
;
2116 ring
->irq_get
= gen8_logical_ring_get_irq
;
2117 ring
->irq_put
= gen8_logical_ring_put_irq
;
2118 ring
->emit_bb_start
= gen8_emit_bb_start
;
2120 return logical_ring_init(dev
, ring
);
2123 static int logical_vebox_ring_init(struct drm_device
*dev
)
2125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2126 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2128 ring
->name
= "video enhancement ring";
2130 ring
->mmio_base
= VEBOX_RING_BASE
;
2131 ring
->irq_enable_mask
=
2132 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2133 ring
->irq_keep_mask
=
2134 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2136 ring
->init_hw
= gen8_init_common_ring
;
2137 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
2138 ring
->get_seqno
= bxt_a_get_seqno
;
2139 ring
->set_seqno
= bxt_a_set_seqno
;
2141 ring
->get_seqno
= gen8_get_seqno
;
2142 ring
->set_seqno
= gen8_set_seqno
;
2144 ring
->emit_request
= gen8_emit_request
;
2145 ring
->emit_flush
= gen8_emit_flush
;
2146 ring
->irq_get
= gen8_logical_ring_get_irq
;
2147 ring
->irq_put
= gen8_logical_ring_put_irq
;
2148 ring
->emit_bb_start
= gen8_emit_bb_start
;
2150 return logical_ring_init(dev
, ring
);
2154 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2157 * This function inits the engines for an Execlists submission style (the equivalent in the
2158 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2159 * those engines that are present in the hardware.
2161 * Return: non-zero if the initialization failed.
2163 int intel_logical_rings_init(struct drm_device
*dev
)
2165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2168 ret
= logical_render_ring_init(dev
);
2173 ret
= logical_bsd_ring_init(dev
);
2175 goto cleanup_render_ring
;
2179 ret
= logical_blt_ring_init(dev
);
2181 goto cleanup_bsd_ring
;
2184 if (HAS_VEBOX(dev
)) {
2185 ret
= logical_vebox_ring_init(dev
);
2187 goto cleanup_blt_ring
;
2190 if (HAS_BSD2(dev
)) {
2191 ret
= logical_bsd2_ring_init(dev
);
2193 goto cleanup_vebox_ring
;
2199 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
2201 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
2203 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
2204 cleanup_render_ring
:
2205 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
2211 make_rpcs(struct drm_device
*dev
)
2216 * No explicit RPCS request is needed to ensure full
2217 * slice/subslice/EU enablement prior to Gen9.
2219 if (INTEL_INFO(dev
)->gen
< 9)
2223 * Starting in Gen9, render power gating can leave
2224 * slice/subslice/EU in a partially enabled state. We
2225 * must make an explicit request through RPCS for full
2228 if (INTEL_INFO(dev
)->has_slice_pg
) {
2229 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2230 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2231 GEN8_RPCS_S_CNT_SHIFT
;
2232 rpcs
|= GEN8_RPCS_ENABLE
;
2235 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2236 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2237 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2238 GEN8_RPCS_SS_CNT_SHIFT
;
2239 rpcs
|= GEN8_RPCS_ENABLE
;
2242 if (INTEL_INFO(dev
)->has_eu_pg
) {
2243 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2244 GEN8_RPCS_EU_MIN_SHIFT
;
2245 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2246 GEN8_RPCS_EU_MAX_SHIFT
;
2247 rpcs
|= GEN8_RPCS_ENABLE
;
2254 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2255 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
2257 struct drm_device
*dev
= ring
->dev
;
2258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2259 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2261 uint32_t *reg_state
;
2265 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2267 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2269 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2273 ret
= i915_gem_object_get_pages(ctx_obj
);
2275 DRM_DEBUG_DRIVER("Could not get object pages\n");
2279 i915_gem_object_pin_pages(ctx_obj
);
2281 /* The second page of the context object contains some fields which must
2282 * be set up prior to the first execution. */
2283 page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
2284 reg_state
= kmap_atomic(page
);
2286 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2287 * commands followed by (reg, value) pairs. The values we are setting here are
2288 * only for the first context restore: on a subsequent save, the GPU will
2289 * recreate this batchbuffer with new values (including all the missing
2290 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2291 reg_state
[CTX_LRI_HEADER_0
] =
2292 MI_LOAD_REGISTER_IMM(ring
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2293 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
, RING_CONTEXT_CONTROL(ring
),
2294 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2295 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2296 CTX_CTRL_RS_CTX_ENABLE
));
2297 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(ring
->mmio_base
), 0);
2298 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(ring
->mmio_base
), 0);
2299 /* Ring buffer start address is not known until the buffer is pinned.
2300 * It is written to the context image in execlists_update_context()
2302 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
, RING_START(ring
->mmio_base
), 0);
2303 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
, RING_CTL(ring
->mmio_base
),
2304 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2305 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
, RING_BBADDR_UDW(ring
->mmio_base
), 0);
2306 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
, RING_BBADDR(ring
->mmio_base
), 0);
2307 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
, RING_BBSTATE(ring
->mmio_base
),
2309 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
, RING_SBBADDR_UDW(ring
->mmio_base
), 0);
2310 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
, RING_SBBADDR(ring
->mmio_base
), 0);
2311 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
, RING_SBBSTATE(ring
->mmio_base
), 0);
2312 if (ring
->id
== RCS
) {
2313 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
, RING_BB_PER_CTX_PTR(ring
->mmio_base
), 0);
2314 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
, RING_INDIRECT_CTX(ring
->mmio_base
), 0);
2315 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
, RING_INDIRECT_CTX_OFFSET(ring
->mmio_base
), 0);
2316 if (ring
->wa_ctx
.obj
) {
2317 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2318 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2320 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2321 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2322 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2324 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2325 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2327 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2328 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2332 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2333 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
, RING_CTX_TIMESTAMP(ring
->mmio_base
), 0);
2334 /* PDP values well be assigned later if needed */
2335 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(ring
, 3), 0);
2336 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(ring
, 3), 0);
2337 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(ring
, 2), 0);
2338 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(ring
, 2), 0);
2339 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(ring
, 1), 0);
2340 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(ring
, 1), 0);
2341 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(ring
, 0), 0);
2342 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(ring
, 0), 0);
2344 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2345 /* 64b PPGTT (48bit canonical)
2346 * PDP0_DESCRIPTOR contains the base address to PML4 and
2347 * other PDP Descriptors are ignored.
2349 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2352 * PDP*_DESCRIPTOR contains the base address of space supported.
2353 * With dynamic page allocation, PDPs may not be allocated at
2354 * this point. Point the unallocated PDPs to the scratch page
2356 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2357 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2358 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2359 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2362 if (ring
->id
== RCS
) {
2363 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2364 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2368 kunmap_atomic(reg_state
);
2369 i915_gem_object_unpin_pages(ctx_obj
);
2375 * intel_lr_context_free() - free the LRC specific bits of a context
2376 * @ctx: the LR context to free.
2378 * The real context freeing is done in i915_gem_context_free: this only
2379 * takes care of the bits that are LRC related: the per-engine backing
2380 * objects and the logical ringbuffer.
2382 void intel_lr_context_free(struct intel_context
*ctx
)
2386 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2387 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2390 struct intel_ringbuffer
*ringbuf
=
2391 ctx
->engine
[i
].ringbuf
;
2392 struct intel_engine_cs
*ring
= ringbuf
->ring
;
2394 if (ctx
== ring
->default_context
) {
2395 intel_unpin_ringbuffer_obj(ringbuf
);
2396 i915_gem_object_ggtt_unpin(ctx_obj
);
2398 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
2399 intel_ringbuffer_free(ringbuf
);
2400 drm_gem_object_unreference(&ctx_obj
->base
);
2406 * intel_lr_context_size() - return the size of the context for an engine
2407 * @ring: which engine to find the context size for
2409 * Each engine may require a different amount of space for a context image,
2410 * so when allocating (or copying) an image, this function can be used to
2411 * find the right size for the specific engine.
2413 * Return: size (in bytes) of an engine-specific context image
2415 * Note: this size includes the HWSP, which is part of the context image
2416 * in LRC mode, but does not include the "shared data page" used with
2417 * GuC submission. The caller should account for this if using the GuC.
2419 uint32_t intel_lr_context_size(struct intel_engine_cs
*ring
)
2423 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2427 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2428 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2430 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2436 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2443 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2444 struct drm_i915_gem_object
*default_ctx_obj
)
2446 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2449 /* The HWSP is part of the default context object in LRC mode. */
2450 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
)
2451 + LRC_PPHWSP_PN
* PAGE_SIZE
;
2452 page
= i915_gem_object_get_page(default_ctx_obj
, LRC_PPHWSP_PN
);
2453 ring
->status_page
.page_addr
= kmap(page
);
2454 ring
->status_page
.obj
= default_ctx_obj
;
2456 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2457 (u32
)ring
->status_page
.gfx_addr
);
2458 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2462 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2463 * @ctx: LR context to create.
2464 * @ring: engine to be used with the context.
2466 * This function can be called more than once, with different engines, if we plan
2467 * to use the context with them. The context backing objects and the ringbuffers
2468 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2469 * the creation is a deferred call: it's better to make sure first that we need to use
2470 * a given ring with the context.
2472 * Return: non-zero on error.
2475 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
2476 struct intel_engine_cs
*ring
)
2478 struct drm_device
*dev
= ring
->dev
;
2479 struct drm_i915_gem_object
*ctx_obj
;
2480 uint32_t context_size
;
2481 struct intel_ringbuffer
*ringbuf
;
2484 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2485 WARN_ON(ctx
->engine
[ring
->id
].state
);
2487 context_size
= round_up(intel_lr_context_size(ring
), 4096);
2489 /* One extra page as the sharing data between driver and GuC */
2490 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2492 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2494 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2498 ringbuf
= intel_engine_create_ringbuffer(ring
, 4 * PAGE_SIZE
);
2499 if (IS_ERR(ringbuf
)) {
2500 ret
= PTR_ERR(ringbuf
);
2501 goto error_deref_obj
;
2504 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2506 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2510 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2511 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2513 if (ctx
!= ring
->default_context
&& ring
->init_context
) {
2514 struct drm_i915_gem_request
*req
;
2516 ret
= i915_gem_request_alloc(ring
,
2519 DRM_ERROR("ring create req: %d\n",
2524 ret
= ring
->init_context(req
);
2526 DRM_ERROR("ring init context: %d\n",
2528 i915_gem_request_cancel(req
);
2531 i915_add_request_no_flush(req
);
2536 intel_ringbuffer_free(ringbuf
);
2538 drm_gem_object_unreference(&ctx_obj
->base
);
2539 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2540 ctx
->engine
[ring
->id
].state
= NULL
;
2544 void intel_lr_context_reset(struct drm_device
*dev
,
2545 struct intel_context
*ctx
)
2547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2548 struct intel_engine_cs
*ring
;
2551 for_each_ring(ring
, dev_priv
, i
) {
2552 struct drm_i915_gem_object
*ctx_obj
=
2553 ctx
->engine
[ring
->id
].state
;
2554 struct intel_ringbuffer
*ringbuf
=
2555 ctx
->engine
[ring
->id
].ringbuf
;
2556 uint32_t *reg_state
;
2562 if (i915_gem_object_get_pages(ctx_obj
)) {
2563 WARN(1, "Failed get_pages for context obj\n");
2566 page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
2567 reg_state
= kmap_atomic(page
);
2569 reg_state
[CTX_RING_HEAD
+1] = 0;
2570 reg_state
[CTX_RING_TAIL
+1] = 0;
2572 kunmap_atomic(reg_state
);