2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 ADVANCED_CONTEXT
= 0,
197 #define GEN8_CTX_MODE_SHIFT 3
200 FAULT_AND_HALT
, /* Debug only */
202 FAULT_AND_CONTINUE
/* Unsupported */
204 #define GEN8_CTX_ID_SHIFT 32
206 static int intel_lr_context_pin(struct intel_engine_cs
*ring
,
207 struct intel_context
*ctx
);
210 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
212 * @enable_execlists: value of i915.enable_execlists module parameter.
214 * Only certain platforms support Execlists (the prerequisites being
215 * support for Logical Ring Contexts and Aliasing PPGTT or better),
216 * and only when enabled via module parameter.
218 * Return: 1 if Execlists is supported and has to be enabled.
220 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
222 WARN_ON(i915
.enable_ppgtt
== -1);
224 if (INTEL_INFO(dev
)->gen
>= 9)
227 if (enable_execlists
== 0)
230 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
231 i915
.use_mmio_flip
>= 0)
238 * intel_execlists_ctx_id() - get the Execlists Context ID
239 * @ctx_obj: Logical Ring Context backing object.
241 * Do not confuse with ctx->id! Unfortunately we have a name overload
242 * here: the old context ID we pass to userspace as a handler so that
243 * they can refer to a context, and the new context ID we pass to the
244 * ELSP so that the GPU can inform us of the context status via
247 * Return: 20-bits globally unique context ID.
249 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
251 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
253 /* LRCA is required to be 4K aligned so the more significant 20 bits
254 * are globally unique */
258 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object
*ctx_obj
)
261 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
263 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
265 desc
= GEN8_CTX_VALID
;
266 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
267 desc
|= GEN8_CTX_L3LLC_COHERENT
;
268 desc
|= GEN8_CTX_PRIVILEGE
;
270 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
272 /* TODO: WaDisableLiteRestore when we start using semaphore
273 * signalling between Command Streamers */
274 /* desc |= GEN8_CTX_FORCE_RESTORE; */
279 static void execlists_elsp_write(struct intel_engine_cs
*ring
,
280 struct drm_i915_gem_object
*ctx_obj0
,
281 struct drm_i915_gem_object
*ctx_obj1
)
283 struct drm_device
*dev
= ring
->dev
;
284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
289 /* XXX: You must always write both descriptors in the order below. */
291 temp
= execlists_ctx_descriptor(ctx_obj1
);
294 desc
[1] = (u32
)(temp
>> 32);
297 temp
= execlists_ctx_descriptor(ctx_obj0
);
298 desc
[3] = (u32
)(temp
>> 32);
301 /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
304 * The other problem is that we can't just call gen6_gt_force_wake_get()
305 * because that function calls intel_runtime_pm_get(), which might sleep.
306 * Instead, we do the runtime_pm_get/put when creating/destroying requests.
308 spin_lock_irqsave(&dev_priv
->uncore
.lock
, flags
);
309 if (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
310 if (dev_priv
->uncore
.fw_rendercount
++ == 0)
311 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
313 if (dev_priv
->uncore
.fw_mediacount
++ == 0)
314 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
316 if (INTEL_INFO(dev
)->gen
>= 9) {
317 if (dev_priv
->uncore
.fw_blittercount
++ == 0)
318 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
322 if (dev_priv
->uncore
.forcewake_count
++ == 0)
323 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
326 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, flags
);
328 I915_WRITE(RING_ELSP(ring
), desc
[1]);
329 I915_WRITE(RING_ELSP(ring
), desc
[0]);
330 I915_WRITE(RING_ELSP(ring
), desc
[3]);
331 /* The context is automatically loaded after the following */
332 I915_WRITE(RING_ELSP(ring
), desc
[2]);
334 /* ELSP is a wo register, so use another nearby reg for posting instead */
335 POSTING_READ(RING_EXECLIST_STATUS(ring
));
337 /* Release Force Wakeup (see the big comment above). */
338 spin_lock_irqsave(&dev_priv
->uncore
.lock
, flags
);
339 if (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
340 if (--dev_priv
->uncore
.fw_rendercount
== 0)
341 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
343 if (--dev_priv
->uncore
.fw_mediacount
== 0)
344 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
346 if (INTEL_INFO(dev
)->gen
>= 9) {
347 if (--dev_priv
->uncore
.fw_blittercount
== 0)
348 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
352 if (--dev_priv
->uncore
.forcewake_count
== 0)
353 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
357 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, flags
);
360 static int execlists_update_context(struct drm_i915_gem_object
*ctx_obj
,
361 struct drm_i915_gem_object
*ring_obj
,
367 page
= i915_gem_object_get_page(ctx_obj
, 1);
368 reg_state
= kmap_atomic(page
);
370 reg_state
[CTX_RING_TAIL
+1] = tail
;
371 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(ring_obj
);
373 kunmap_atomic(reg_state
);
378 static void execlists_submit_contexts(struct intel_engine_cs
*ring
,
379 struct intel_context
*to0
, u32 tail0
,
380 struct intel_context
*to1
, u32 tail1
)
382 struct drm_i915_gem_object
*ctx_obj0
= to0
->engine
[ring
->id
].state
;
383 struct intel_ringbuffer
*ringbuf0
= to0
->engine
[ring
->id
].ringbuf
;
384 struct drm_i915_gem_object
*ctx_obj1
= NULL
;
385 struct intel_ringbuffer
*ringbuf1
= NULL
;
388 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0
));
389 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0
->obj
));
391 execlists_update_context(ctx_obj0
, ringbuf0
->obj
, tail0
);
394 ringbuf1
= to1
->engine
[ring
->id
].ringbuf
;
395 ctx_obj1
= to1
->engine
[ring
->id
].state
;
397 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1
));
398 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1
->obj
));
400 execlists_update_context(ctx_obj1
, ringbuf1
->obj
, tail1
);
403 execlists_elsp_write(ring
, ctx_obj0
, ctx_obj1
);
406 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
408 struct intel_ctx_submit_request
*req0
= NULL
, *req1
= NULL
;
409 struct intel_ctx_submit_request
*cursor
= NULL
, *tmp
= NULL
;
411 assert_spin_locked(&ring
->execlist_lock
);
413 if (list_empty(&ring
->execlist_queue
))
416 /* Try to read in pairs */
417 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
421 } else if (req0
->ctx
== cursor
->ctx
) {
422 /* Same ctx: ignore first request, as second request
423 * will update tail past first request's workload */
424 cursor
->elsp_submitted
= req0
->elsp_submitted
;
425 list_del(&req0
->execlist_link
);
426 list_add_tail(&req0
->execlist_link
,
427 &ring
->execlist_retired_req_list
);
435 WARN_ON(req1
&& req1
->elsp_submitted
);
437 execlists_submit_contexts(ring
, req0
->ctx
, req0
->tail
,
438 req1
? req1
->ctx
: NULL
,
439 req1
? req1
->tail
: 0);
441 req0
->elsp_submitted
++;
443 req1
->elsp_submitted
++;
446 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
449 struct intel_ctx_submit_request
*head_req
;
451 assert_spin_locked(&ring
->execlist_lock
);
453 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
454 struct intel_ctx_submit_request
,
457 if (head_req
!= NULL
) {
458 struct drm_i915_gem_object
*ctx_obj
=
459 head_req
->ctx
->engine
[ring
->id
].state
;
460 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
461 WARN(head_req
->elsp_submitted
== 0,
462 "Never submitted head request\n");
464 if (--head_req
->elsp_submitted
<= 0) {
465 list_del(&head_req
->execlist_link
);
466 list_add_tail(&head_req
->execlist_link
,
467 &ring
->execlist_retired_req_list
);
477 * intel_execlists_handle_ctx_events() - handle Context Switch interrupts
478 * @ring: Engine Command Streamer to handle.
480 * Check the unread Context Status Buffers and manage the submission of new
481 * contexts to the ELSP accordingly.
483 void intel_execlists_handle_ctx_events(struct intel_engine_cs
*ring
)
485 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
491 u32 submit_contexts
= 0;
493 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
495 read_pointer
= ring
->next_context_status_buffer
;
496 write_pointer
= status_pointer
& 0x07;
497 if (read_pointer
> write_pointer
)
500 spin_lock(&ring
->execlist_lock
);
502 while (read_pointer
< write_pointer
) {
504 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
505 (read_pointer
% 6) * 8);
506 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
507 (read_pointer
% 6) * 8 + 4);
509 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
510 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
511 if (execlists_check_remove_request(ring
, status_id
))
512 WARN(1, "Lite Restored request removed from queue\n");
514 WARN(1, "Preemption without Lite Restore\n");
517 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
518 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
519 if (execlists_check_remove_request(ring
, status_id
))
524 if (submit_contexts
!= 0)
525 execlists_context_unqueue(ring
);
527 spin_unlock(&ring
->execlist_lock
);
529 WARN(submit_contexts
> 2, "More than two context complete events?\n");
530 ring
->next_context_status_buffer
= write_pointer
% 6;
532 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
533 ((u32
)ring
->next_context_status_buffer
& 0x07) << 8);
536 static int execlists_context_queue(struct intel_engine_cs
*ring
,
537 struct intel_context
*to
,
540 struct intel_ctx_submit_request
*req
= NULL
, *cursor
;
541 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
543 int num_elements
= 0;
545 req
= kzalloc(sizeof(*req
), GFP_KERNEL
);
549 i915_gem_context_reference(req
->ctx
);
551 if (to
!= ring
->default_context
)
552 intel_lr_context_pin(ring
, to
);
557 intel_runtime_pm_get(dev_priv
);
559 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
561 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
562 if (++num_elements
> 2)
565 if (num_elements
> 2) {
566 struct intel_ctx_submit_request
*tail_req
;
568 tail_req
= list_last_entry(&ring
->execlist_queue
,
569 struct intel_ctx_submit_request
,
572 if (to
== tail_req
->ctx
) {
573 WARN(tail_req
->elsp_submitted
!= 0,
574 "More than 2 already-submitted reqs queued\n");
575 list_del(&tail_req
->execlist_link
);
576 list_add_tail(&tail_req
->execlist_link
,
577 &ring
->execlist_retired_req_list
);
581 list_add_tail(&req
->execlist_link
, &ring
->execlist_queue
);
582 if (num_elements
== 0)
583 execlists_context_unqueue(ring
);
585 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
590 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer
*ringbuf
)
592 struct intel_engine_cs
*ring
= ringbuf
->ring
;
593 uint32_t flush_domains
;
597 if (ring
->gpu_caches_dirty
)
598 flush_domains
= I915_GEM_GPU_DOMAINS
;
600 ret
= ring
->emit_flush(ringbuf
, I915_GEM_GPU_DOMAINS
, flush_domains
);
604 ring
->gpu_caches_dirty
= false;
608 static int execlists_move_to_gpu(struct intel_ringbuffer
*ringbuf
,
609 struct list_head
*vmas
)
611 struct intel_engine_cs
*ring
= ringbuf
->ring
;
612 struct i915_vma
*vma
;
613 uint32_t flush_domains
= 0;
614 bool flush_chipset
= false;
617 list_for_each_entry(vma
, vmas
, exec_list
) {
618 struct drm_i915_gem_object
*obj
= vma
->obj
;
620 ret
= i915_gem_object_sync(obj
, ring
);
624 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
625 flush_chipset
|= i915_gem_clflush_object(obj
, false);
627 flush_domains
|= obj
->base
.write_domain
;
630 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
633 /* Unconditionally invalidate gpu caches and ensure that we do flush
634 * any residual writes from the previous batch.
636 return logical_ring_invalidate_all_caches(ringbuf
);
640 * execlists_submission() - submit a batchbuffer for execution, Execlists style
643 * @ring: Engine Command Streamer to submit to.
644 * @ctx: Context to employ for this submission.
645 * @args: execbuffer call arguments.
646 * @vmas: list of vmas.
647 * @batch_obj: the batchbuffer to submit.
648 * @exec_start: batchbuffer start virtual address pointer.
649 * @flags: translated execbuffer call flags.
651 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
652 * away the submission details of the execbuffer ioctl call.
654 * Return: non-zero if the submission fails.
656 int intel_execlists_submission(struct drm_device
*dev
, struct drm_file
*file
,
657 struct intel_engine_cs
*ring
,
658 struct intel_context
*ctx
,
659 struct drm_i915_gem_execbuffer2
*args
,
660 struct list_head
*vmas
,
661 struct drm_i915_gem_object
*batch_obj
,
662 u64 exec_start
, u32 flags
)
664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
665 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
670 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
671 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
672 switch (instp_mode
) {
673 case I915_EXEC_CONSTANTS_REL_GENERAL
:
674 case I915_EXEC_CONSTANTS_ABSOLUTE
:
675 case I915_EXEC_CONSTANTS_REL_SURFACE
:
676 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
677 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
681 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
682 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
683 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
687 /* The HW changed the meaning on this bit on gen6 */
688 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
692 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
696 if (args
->num_cliprects
!= 0) {
697 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
700 if (args
->DR4
== 0xffffffff) {
701 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
705 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
706 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
711 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
712 DRM_DEBUG("sol reset is gen7 only\n");
716 ret
= execlists_move_to_gpu(ringbuf
, vmas
);
720 if (ring
== &dev_priv
->ring
[RCS
] &&
721 instp_mode
!= dev_priv
->relative_constants_mode
) {
722 ret
= intel_logical_ring_begin(ringbuf
, 4);
726 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
727 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
728 intel_logical_ring_emit(ringbuf
, INSTPM
);
729 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
730 intel_logical_ring_advance(ringbuf
);
732 dev_priv
->relative_constants_mode
= instp_mode
;
735 ret
= ring
->emit_bb_start(ringbuf
, exec_start
, flags
);
739 i915_gem_execbuffer_move_to_active(vmas
, ring
);
740 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
745 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
747 struct intel_ctx_submit_request
*req
, *tmp
;
748 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
750 struct list_head retired_list
;
752 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
753 if (list_empty(&ring
->execlist_retired_req_list
))
756 INIT_LIST_HEAD(&retired_list
);
757 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
758 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
759 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
761 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
762 struct intel_context
*ctx
= req
->ctx
;
763 struct drm_i915_gem_object
*ctx_obj
=
764 ctx
->engine
[ring
->id
].state
;
766 if (ctx_obj
&& (ctx
!= ring
->default_context
))
767 intel_lr_context_unpin(ring
, ctx
);
768 intel_runtime_pm_put(dev_priv
);
769 i915_gem_context_unreference(req
->ctx
);
770 list_del(&req
->execlist_link
);
775 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
777 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
780 if (!intel_ring_initialized(ring
))
783 ret
= intel_ring_idle(ring
);
784 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
785 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
788 /* TODO: Is this correct with Execlists enabled? */
789 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
790 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
791 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
794 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
797 int logical_ring_flush_all_caches(struct intel_ringbuffer
*ringbuf
)
799 struct intel_engine_cs
*ring
= ringbuf
->ring
;
802 if (!ring
->gpu_caches_dirty
)
805 ret
= ring
->emit_flush(ringbuf
, 0, I915_GEM_GPU_DOMAINS
);
809 ring
->gpu_caches_dirty
= false;
814 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
815 * @ringbuf: Logical Ringbuffer to advance.
817 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
818 * really happens during submission is that the context and current tail will be placed
819 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
820 * point, the tail *inside* the context is updated and the ELSP written to.
822 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer
*ringbuf
)
824 struct intel_engine_cs
*ring
= ringbuf
->ring
;
825 struct intel_context
*ctx
= ringbuf
->FIXME_lrc_ctx
;
827 intel_logical_ring_advance(ringbuf
);
829 if (intel_ring_stopped(ring
))
832 execlists_context_queue(ring
, ctx
, ringbuf
->tail
);
835 static int intel_lr_context_pin(struct intel_engine_cs
*ring
,
836 struct intel_context
*ctx
)
838 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
839 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
842 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
843 if (ctx
->engine
[ring
->id
].unpin_count
++ == 0) {
844 ret
= i915_gem_obj_ggtt_pin(ctx_obj
,
845 GEN8_LR_CONTEXT_ALIGN
, 0);
847 goto reset_unpin_count
;
849 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
857 i915_gem_object_ggtt_unpin(ctx_obj
);
859 ctx
->engine
[ring
->id
].unpin_count
= 0;
864 void intel_lr_context_unpin(struct intel_engine_cs
*ring
,
865 struct intel_context
*ctx
)
867 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
868 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
871 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
872 if (--ctx
->engine
[ring
->id
].unpin_count
== 0) {
873 intel_unpin_ringbuffer_obj(ringbuf
);
874 i915_gem_object_ggtt_unpin(ctx_obj
);
879 static int logical_ring_alloc_request(struct intel_engine_cs
*ring
,
880 struct intel_context
*ctx
)
882 struct drm_i915_gem_request
*request
;
885 if (ring
->outstanding_lazy_request
)
888 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
892 if (ctx
!= ring
->default_context
) {
893 ret
= intel_lr_context_pin(ring
, ctx
);
900 kref_init(&request
->ref
);
901 request
->ring
= ring
;
903 ret
= i915_gem_get_seqno(ring
->dev
, &request
->seqno
);
905 intel_lr_context_unpin(ring
, ctx
);
910 /* Hold a reference to the context this request belongs to
911 * (we will need it when the time comes to emit/retire the
915 i915_gem_context_reference(request
->ctx
);
917 ring
->outstanding_lazy_request
= request
;
921 static int logical_ring_wait_request(struct intel_ringbuffer
*ringbuf
,
924 struct intel_engine_cs
*ring
= ringbuf
->ring
;
925 struct drm_i915_gem_request
*request
;
928 if (intel_ring_space(ringbuf
) >= bytes
)
931 list_for_each_entry(request
, &ring
->request_list
, list
) {
933 * The request queue is per-engine, so can contain requests
934 * from multiple ringbuffers. Here, we must ignore any that
935 * aren't from the ringbuffer we're considering.
937 struct intel_context
*ctx
= request
->ctx
;
938 if (ctx
->engine
[ring
->id
].ringbuf
!= ringbuf
)
941 /* Would completion of this request free enough space? */
942 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
943 ringbuf
->size
) >= bytes
) {
948 if (&request
->list
== &ring
->request_list
)
951 ret
= i915_wait_request(request
);
955 i915_gem_retire_requests_ring(ring
);
957 return intel_ring_space(ringbuf
) >= bytes
? 0 : -ENOSPC
;
960 static int logical_ring_wait_for_space(struct intel_ringbuffer
*ringbuf
,
963 struct intel_engine_cs
*ring
= ringbuf
->ring
;
964 struct drm_device
*dev
= ring
->dev
;
965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
969 ret
= logical_ring_wait_request(ringbuf
, bytes
);
973 /* Force the context submission in case we have been skipping it */
974 intel_logical_ring_advance_and_submit(ringbuf
);
976 /* With GEM the hangcheck timer should kick us out of the loop,
977 * leaving it early runs the risk of corrupting GEM state (due
978 * to running on almost untested codepaths). But on resume
979 * timers don't work yet, so prevent a complete hang in that
980 * case by choosing an insanely large timeout. */
981 end
= jiffies
+ 60 * HZ
;
985 if (intel_ring_space(ringbuf
) >= bytes
)
990 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
995 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
996 dev_priv
->mm
.interruptible
);
1000 if (time_after(jiffies
, end
)) {
1009 static int logical_ring_wrap_buffer(struct intel_ringbuffer
*ringbuf
)
1011 uint32_t __iomem
*virt
;
1012 int rem
= ringbuf
->size
- ringbuf
->tail
;
1014 if (ringbuf
->space
< rem
) {
1015 int ret
= logical_ring_wait_for_space(ringbuf
, rem
);
1021 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
1024 iowrite32(MI_NOOP
, virt
++);
1027 intel_ring_update_space(ringbuf
);
1032 static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf
, int bytes
)
1036 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
1037 ret
= logical_ring_wrap_buffer(ringbuf
);
1042 if (unlikely(ringbuf
->space
< bytes
)) {
1043 ret
= logical_ring_wait_for_space(ringbuf
, bytes
);
1052 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1054 * @ringbuf: Logical ringbuffer.
1055 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1057 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1058 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1059 * and also preallocates a request (every workload submission is still mediated through
1060 * requests, same as it did with legacy ringbuffer submission).
1062 * Return: non-zero if the ringbuffer is not ready to be written to.
1064 int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf
, int num_dwords
)
1066 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1067 struct drm_device
*dev
= ring
->dev
;
1068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1071 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1072 dev_priv
->mm
.interruptible
);
1076 ret
= logical_ring_prepare(ringbuf
, num_dwords
* sizeof(uint32_t));
1080 /* Preallocate the olr before touching the ring */
1081 ret
= logical_ring_alloc_request(ring
, ringbuf
->FIXME_lrc_ctx
);
1085 ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
1089 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs
*ring
,
1090 struct intel_context
*ctx
)
1093 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1094 struct drm_device
*dev
= ring
->dev
;
1095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1096 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1098 if (WARN_ON(w
->count
== 0))
1101 ring
->gpu_caches_dirty
= true;
1102 ret
= logical_ring_flush_all_caches(ringbuf
);
1106 ret
= intel_logical_ring_begin(ringbuf
, w
->count
* 2 + 2);
1110 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1111 for (i
= 0; i
< w
->count
; i
++) {
1112 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1113 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1115 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1117 intel_logical_ring_advance(ringbuf
);
1119 ring
->gpu_caches_dirty
= true;
1120 ret
= logical_ring_flush_all_caches(ringbuf
);
1127 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1129 struct drm_device
*dev
= ring
->dev
;
1130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1132 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1133 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1135 I915_WRITE(RING_MODE_GEN7(ring
),
1136 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1137 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1138 POSTING_READ(RING_MODE_GEN7(ring
));
1139 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1141 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1146 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1148 struct drm_device
*dev
= ring
->dev
;
1149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1152 ret
= gen8_init_common_ring(ring
);
1156 /* We need to disable the AsyncFlip performance optimisations in order
1157 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1158 * programmed to '1' on all products.
1160 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1162 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1164 ret
= intel_init_pipe_control(ring
);
1168 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1170 return init_workarounds_ring(ring
);
1173 static int gen8_emit_bb_start(struct intel_ringbuffer
*ringbuf
,
1174 u64 offset
, unsigned flags
)
1176 bool ppgtt
= !(flags
& I915_DISPATCH_SECURE
);
1179 ret
= intel_logical_ring_begin(ringbuf
, 4);
1183 /* FIXME(BDW): Address space and security selectors. */
1184 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
1185 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1186 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1187 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1188 intel_logical_ring_advance(ringbuf
);
1193 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1195 struct drm_device
*dev
= ring
->dev
;
1196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1197 unsigned long flags
;
1199 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1202 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1203 if (ring
->irq_refcount
++ == 0) {
1204 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1205 POSTING_READ(RING_IMR(ring
->mmio_base
));
1207 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1212 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1214 struct drm_device
*dev
= ring
->dev
;
1215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1216 unsigned long flags
;
1218 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1219 if (--ring
->irq_refcount
== 0) {
1220 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1221 POSTING_READ(RING_IMR(ring
->mmio_base
));
1223 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1226 static int gen8_emit_flush(struct intel_ringbuffer
*ringbuf
,
1227 u32 invalidate_domains
,
1230 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1231 struct drm_device
*dev
= ring
->dev
;
1232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1236 ret
= intel_logical_ring_begin(ringbuf
, 4);
1240 cmd
= MI_FLUSH_DW
+ 1;
1242 if (ring
== &dev_priv
->ring
[VCS
]) {
1243 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
1244 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1245 MI_FLUSH_DW_STORE_INDEX
|
1246 MI_FLUSH_DW_OP_STOREDW
;
1248 if (invalidate_domains
& I915_GEM_DOMAIN_RENDER
)
1249 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1250 MI_FLUSH_DW_OP_STOREDW
;
1253 intel_logical_ring_emit(ringbuf
, cmd
);
1254 intel_logical_ring_emit(ringbuf
,
1255 I915_GEM_HWS_SCRATCH_ADDR
|
1256 MI_FLUSH_DW_USE_GTT
);
1257 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1258 intel_logical_ring_emit(ringbuf
, 0); /* value */
1259 intel_logical_ring_advance(ringbuf
);
1264 static int gen8_emit_flush_render(struct intel_ringbuffer
*ringbuf
,
1265 u32 invalidate_domains
,
1268 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1269 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1273 flags
|= PIPE_CONTROL_CS_STALL
;
1275 if (flush_domains
) {
1276 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1277 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1280 if (invalidate_domains
) {
1281 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1282 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1283 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1284 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1285 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1286 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1287 flags
|= PIPE_CONTROL_QW_WRITE
;
1288 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1291 ret
= intel_logical_ring_begin(ringbuf
, 6);
1295 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1296 intel_logical_ring_emit(ringbuf
, flags
);
1297 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1298 intel_logical_ring_emit(ringbuf
, 0);
1299 intel_logical_ring_emit(ringbuf
, 0);
1300 intel_logical_ring_emit(ringbuf
, 0);
1301 intel_logical_ring_advance(ringbuf
);
1306 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1308 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1311 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1313 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1316 static int gen8_emit_request(struct intel_ringbuffer
*ringbuf
)
1318 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1322 ret
= intel_logical_ring_begin(ringbuf
, 6);
1326 cmd
= MI_STORE_DWORD_IMM_GEN8
;
1327 cmd
|= MI_GLOBAL_GTT
;
1329 intel_logical_ring_emit(ringbuf
, cmd
);
1330 intel_logical_ring_emit(ringbuf
,
1331 (ring
->status_page
.gfx_addr
+
1332 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1333 intel_logical_ring_emit(ringbuf
, 0);
1334 intel_logical_ring_emit(ringbuf
,
1335 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1336 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1337 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1338 intel_logical_ring_advance_and_submit(ringbuf
);
1344 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1346 * @ring: Engine Command Streamer.
1349 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1351 struct drm_i915_private
*dev_priv
;
1353 if (!intel_ring_initialized(ring
))
1356 dev_priv
= ring
->dev
->dev_private
;
1358 intel_logical_ring_stop(ring
);
1359 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1360 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
1363 ring
->cleanup(ring
);
1365 i915_cmd_parser_fini_ring(ring
);
1367 if (ring
->status_page
.obj
) {
1368 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1369 ring
->status_page
.obj
= NULL
;
1373 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1377 /* Intentionally left blank. */
1378 ring
->buffer
= NULL
;
1381 INIT_LIST_HEAD(&ring
->active_list
);
1382 INIT_LIST_HEAD(&ring
->request_list
);
1383 init_waitqueue_head(&ring
->irq_queue
);
1385 INIT_LIST_HEAD(&ring
->execlist_queue
);
1386 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1387 spin_lock_init(&ring
->execlist_lock
);
1388 ring
->next_context_status_buffer
= 0;
1390 ret
= i915_cmd_parser_init_ring(ring
);
1395 ret
= ring
->init(ring
);
1400 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1405 static int logical_render_ring_init(struct drm_device
*dev
)
1407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1408 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1410 ring
->name
= "render ring";
1412 ring
->mmio_base
= RENDER_RING_BASE
;
1413 ring
->irq_enable_mask
=
1414 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1415 ring
->irq_keep_mask
=
1416 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1417 if (HAS_L3_DPF(dev
))
1418 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1420 ring
->init
= gen8_init_render_ring
;
1421 ring
->init_context
= intel_logical_ring_workarounds_emit
;
1422 ring
->cleanup
= intel_fini_pipe_control
;
1423 ring
->get_seqno
= gen8_get_seqno
;
1424 ring
->set_seqno
= gen8_set_seqno
;
1425 ring
->emit_request
= gen8_emit_request
;
1426 ring
->emit_flush
= gen8_emit_flush_render
;
1427 ring
->irq_get
= gen8_logical_ring_get_irq
;
1428 ring
->irq_put
= gen8_logical_ring_put_irq
;
1429 ring
->emit_bb_start
= gen8_emit_bb_start
;
1431 return logical_ring_init(dev
, ring
);
1434 static int logical_bsd_ring_init(struct drm_device
*dev
)
1436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1437 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1439 ring
->name
= "bsd ring";
1441 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1442 ring
->irq_enable_mask
=
1443 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1444 ring
->irq_keep_mask
=
1445 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1447 ring
->init
= gen8_init_common_ring
;
1448 ring
->get_seqno
= gen8_get_seqno
;
1449 ring
->set_seqno
= gen8_set_seqno
;
1450 ring
->emit_request
= gen8_emit_request
;
1451 ring
->emit_flush
= gen8_emit_flush
;
1452 ring
->irq_get
= gen8_logical_ring_get_irq
;
1453 ring
->irq_put
= gen8_logical_ring_put_irq
;
1454 ring
->emit_bb_start
= gen8_emit_bb_start
;
1456 return logical_ring_init(dev
, ring
);
1459 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1462 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1464 ring
->name
= "bds2 ring";
1466 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1467 ring
->irq_enable_mask
=
1468 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1469 ring
->irq_keep_mask
=
1470 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1472 ring
->init
= gen8_init_common_ring
;
1473 ring
->get_seqno
= gen8_get_seqno
;
1474 ring
->set_seqno
= gen8_set_seqno
;
1475 ring
->emit_request
= gen8_emit_request
;
1476 ring
->emit_flush
= gen8_emit_flush
;
1477 ring
->irq_get
= gen8_logical_ring_get_irq
;
1478 ring
->irq_put
= gen8_logical_ring_put_irq
;
1479 ring
->emit_bb_start
= gen8_emit_bb_start
;
1481 return logical_ring_init(dev
, ring
);
1484 static int logical_blt_ring_init(struct drm_device
*dev
)
1486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1487 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1489 ring
->name
= "blitter ring";
1491 ring
->mmio_base
= BLT_RING_BASE
;
1492 ring
->irq_enable_mask
=
1493 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1494 ring
->irq_keep_mask
=
1495 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1497 ring
->init
= gen8_init_common_ring
;
1498 ring
->get_seqno
= gen8_get_seqno
;
1499 ring
->set_seqno
= gen8_set_seqno
;
1500 ring
->emit_request
= gen8_emit_request
;
1501 ring
->emit_flush
= gen8_emit_flush
;
1502 ring
->irq_get
= gen8_logical_ring_get_irq
;
1503 ring
->irq_put
= gen8_logical_ring_put_irq
;
1504 ring
->emit_bb_start
= gen8_emit_bb_start
;
1506 return logical_ring_init(dev
, ring
);
1509 static int logical_vebox_ring_init(struct drm_device
*dev
)
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1514 ring
->name
= "video enhancement ring";
1516 ring
->mmio_base
= VEBOX_RING_BASE
;
1517 ring
->irq_enable_mask
=
1518 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1519 ring
->irq_keep_mask
=
1520 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1522 ring
->init
= gen8_init_common_ring
;
1523 ring
->get_seqno
= gen8_get_seqno
;
1524 ring
->set_seqno
= gen8_set_seqno
;
1525 ring
->emit_request
= gen8_emit_request
;
1526 ring
->emit_flush
= gen8_emit_flush
;
1527 ring
->irq_get
= gen8_logical_ring_get_irq
;
1528 ring
->irq_put
= gen8_logical_ring_put_irq
;
1529 ring
->emit_bb_start
= gen8_emit_bb_start
;
1531 return logical_ring_init(dev
, ring
);
1535 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1538 * This function inits the engines for an Execlists submission style (the equivalent in the
1539 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1540 * those engines that are present in the hardware.
1542 * Return: non-zero if the initialization failed.
1544 int intel_logical_rings_init(struct drm_device
*dev
)
1546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1549 ret
= logical_render_ring_init(dev
);
1554 ret
= logical_bsd_ring_init(dev
);
1556 goto cleanup_render_ring
;
1560 ret
= logical_blt_ring_init(dev
);
1562 goto cleanup_bsd_ring
;
1565 if (HAS_VEBOX(dev
)) {
1566 ret
= logical_vebox_ring_init(dev
);
1568 goto cleanup_blt_ring
;
1571 if (HAS_BSD2(dev
)) {
1572 ret
= logical_bsd2_ring_init(dev
);
1574 goto cleanup_vebox_ring
;
1577 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
1579 goto cleanup_bsd2_ring
;
1584 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
1586 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
1588 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
1590 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
1591 cleanup_render_ring
:
1592 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
1597 int intel_lr_context_render_state_init(struct intel_engine_cs
*ring
,
1598 struct intel_context
*ctx
)
1600 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1601 struct render_state so
;
1602 struct drm_i915_file_private
*file_priv
= ctx
->file_priv
;
1603 struct drm_file
*file
= file_priv
? file_priv
->file
: NULL
;
1606 ret
= i915_gem_render_state_prepare(ring
, &so
);
1610 if (so
.rodata
== NULL
)
1613 ret
= ring
->emit_bb_start(ringbuf
,
1615 I915_DISPATCH_SECURE
);
1619 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), ring
);
1621 ret
= __i915_add_request(ring
, file
, so
.obj
);
1622 /* intel_logical_ring_add_request moves object to inactive if it
1625 i915_gem_render_state_fini(&so
);
1630 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
1631 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
1633 struct drm_device
*dev
= ring
->dev
;
1634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1635 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1637 uint32_t *reg_state
;
1641 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1643 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1645 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1649 ret
= i915_gem_object_get_pages(ctx_obj
);
1651 DRM_DEBUG_DRIVER("Could not get object pages\n");
1655 i915_gem_object_pin_pages(ctx_obj
);
1657 /* The second page of the context object contains some fields which must
1658 * be set up prior to the first execution. */
1659 page
= i915_gem_object_get_page(ctx_obj
, 1);
1660 reg_state
= kmap_atomic(page
);
1662 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1663 * commands followed by (reg, value) pairs. The values we are setting here are
1664 * only for the first context restore: on a subsequent save, the GPU will
1665 * recreate this batchbuffer with new values (including all the missing
1666 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1667 if (ring
->id
== RCS
)
1668 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
1670 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
1671 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
1672 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
1673 reg_state
[CTX_CONTEXT_CONTROL
+1] =
1674 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT
);
1675 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
1676 reg_state
[CTX_RING_HEAD
+1] = 0;
1677 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
1678 reg_state
[CTX_RING_TAIL
+1] = 0;
1679 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
1680 /* Ring buffer start address is not known until the buffer is pinned.
1681 * It is written to the context image in execlists_update_context()
1683 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
1684 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
1685 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
1686 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
1687 reg_state
[CTX_BB_HEAD_U
+1] = 0;
1688 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
1689 reg_state
[CTX_BB_HEAD_L
+1] = 0;
1690 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
1691 reg_state
[CTX_BB_STATE
+1] = (1<<5);
1692 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
1693 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
1694 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
1695 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
1696 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
1697 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
1698 if (ring
->id
== RCS
) {
1699 /* TODO: according to BSpec, the register state context
1700 * for CHV does not have these. OTOH, these registers do
1701 * exist in CHV. I'm waiting for a clarification */
1702 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
1703 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
1704 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
1705 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
1706 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
1707 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
1709 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
1710 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
1711 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
1712 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
1713 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
1714 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
1715 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
1716 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
1717 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
1718 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
1719 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
1720 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
1721 reg_state
[CTX_PDP3_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[3]);
1722 reg_state
[CTX_PDP3_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[3]);
1723 reg_state
[CTX_PDP2_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[2]);
1724 reg_state
[CTX_PDP2_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[2]);
1725 reg_state
[CTX_PDP1_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[1]);
1726 reg_state
[CTX_PDP1_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[1]);
1727 reg_state
[CTX_PDP0_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[0]);
1728 reg_state
[CTX_PDP0_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[0]);
1729 if (ring
->id
== RCS
) {
1730 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
1731 reg_state
[CTX_R_PWR_CLK_STATE
] = 0x20c8;
1732 reg_state
[CTX_R_PWR_CLK_STATE
+1] = 0;
1735 kunmap_atomic(reg_state
);
1738 set_page_dirty(page
);
1739 i915_gem_object_unpin_pages(ctx_obj
);
1745 * intel_lr_context_free() - free the LRC specific bits of a context
1746 * @ctx: the LR context to free.
1748 * The real context freeing is done in i915_gem_context_free: this only
1749 * takes care of the bits that are LRC related: the per-engine backing
1750 * objects and the logical ringbuffer.
1752 void intel_lr_context_free(struct intel_context
*ctx
)
1756 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1757 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
1760 struct intel_ringbuffer
*ringbuf
=
1761 ctx
->engine
[i
].ringbuf
;
1762 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1764 if (ctx
== ring
->default_context
) {
1765 intel_unpin_ringbuffer_obj(ringbuf
);
1766 i915_gem_object_ggtt_unpin(ctx_obj
);
1768 intel_destroy_ringbuffer_obj(ringbuf
);
1770 drm_gem_object_unreference(&ctx_obj
->base
);
1775 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
1779 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
1783 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
1784 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
1786 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
1792 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
1799 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
1800 struct drm_i915_gem_object
*default_ctx_obj
)
1802 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1804 /* The status page is offset 0 from the default context object
1806 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
);
1807 ring
->status_page
.page_addr
=
1808 kmap(sg_page(default_ctx_obj
->pages
->sgl
));
1809 ring
->status_page
.obj
= default_ctx_obj
;
1811 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1812 (u32
)ring
->status_page
.gfx_addr
);
1813 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1817 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1818 * @ctx: LR context to create.
1819 * @ring: engine to be used with the context.
1821 * This function can be called more than once, with different engines, if we plan
1822 * to use the context with them. The context backing objects and the ringbuffers
1823 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1824 * the creation is a deferred call: it's better to make sure first that we need to use
1825 * a given ring with the context.
1827 * Return: non-zero on error.
1829 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
1830 struct intel_engine_cs
*ring
)
1832 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
1833 struct drm_device
*dev
= ring
->dev
;
1834 struct drm_i915_gem_object
*ctx_obj
;
1835 uint32_t context_size
;
1836 struct intel_ringbuffer
*ringbuf
;
1839 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
1840 if (ctx
->engine
[ring
->id
].state
)
1843 context_size
= round_up(get_lr_context_size(ring
), 4096);
1845 ctx_obj
= i915_gem_alloc_context_obj(dev
, context_size
);
1846 if (IS_ERR(ctx_obj
)) {
1847 ret
= PTR_ERR(ctx_obj
);
1848 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret
);
1852 if (is_global_default_ctx
) {
1853 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
1855 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1857 drm_gem_object_unreference(&ctx_obj
->base
);
1862 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1864 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1867 goto error_unpin_ctx
;
1870 ringbuf
->ring
= ring
;
1871 ringbuf
->FIXME_lrc_ctx
= ctx
;
1873 ringbuf
->size
= 32 * PAGE_SIZE
;
1874 ringbuf
->effective_size
= ringbuf
->size
;
1877 ringbuf
->last_retired_head
= -1;
1878 intel_ring_update_space(ringbuf
);
1880 if (ringbuf
->obj
== NULL
) {
1881 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1884 "Failed to allocate ringbuffer obj %s: %d\n",
1886 goto error_free_rbuf
;
1889 if (is_global_default_ctx
) {
1890 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
1893 "Failed to pin and map ringbuffer %s: %d\n",
1895 goto error_destroy_rbuf
;
1901 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
1903 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
1907 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
1908 ctx
->engine
[ring
->id
].state
= ctx_obj
;
1910 if (ctx
== ring
->default_context
)
1911 lrc_setup_hardware_status_page(ring
, ctx_obj
);
1913 if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
1914 if (ring
->init_context
) {
1915 ret
= ring
->init_context(ring
, ctx
);
1917 DRM_ERROR("ring init context: %d\n", ret
);
1920 ret
= intel_lr_context_render_state_init(ring
, ctx
);
1922 DRM_ERROR("Init render state failed: %d\n", ret
);
1923 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
1924 ctx
->engine
[ring
->id
].state
= NULL
;
1927 ctx
->rcs_initialized
= true;
1933 if (is_global_default_ctx
)
1934 intel_unpin_ringbuffer_obj(ringbuf
);
1936 intel_destroy_ringbuffer_obj(ringbuf
);
1940 if (is_global_default_ctx
)
1941 i915_gem_object_ggtt_unpin(ctx_obj
);
1942 drm_gem_object_unreference(&ctx_obj
->base
);