2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
212 FAULT_AND_HALT
, /* Debug only */
214 FAULT_AND_CONTINUE
/* Unsupported */
216 #define GEN8_CTX_ID_SHIFT 32
217 #define GEN8_CTX_ID_WIDTH 21
218 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
219 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
221 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
222 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
224 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
225 struct intel_engine_cs
*engine
);
226 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
227 struct intel_engine_cs
*engine
);
230 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
231 * @dev_priv: i915 device private
232 * @enable_execlists: value of i915.enable_execlists module parameter.
234 * Only certain platforms support Execlists (the prerequisites being
235 * support for Logical Ring Contexts and Aliasing PPGTT or better).
237 * Return: 1 if Execlists is supported and has to be enabled.
239 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
241 /* On platforms with execlist available, vGPU will only
242 * support execlist mode, no ring buffer mode.
244 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
247 if (INTEL_GEN(dev_priv
) >= 9)
250 if (enable_execlists
== 0)
253 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
254 USES_PPGTT(dev_priv
) &&
255 i915
.use_mmio_flip
>= 0)
262 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
264 struct drm_i915_private
*dev_priv
= engine
->i915
;
266 if (IS_GEN8(dev_priv
) || IS_GEN9(dev_priv
))
267 engine
->idle_lite_restore_wa
= ~0;
269 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
270 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) &&
271 (engine
->id
== VCS
|| engine
->id
== VCS2
);
273 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
274 if (IS_GEN8(dev_priv
))
275 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
276 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
278 /* TODO: WaDisableLiteRestore when we start using semaphore
279 * signalling between Command Streamers */
280 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
282 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
283 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
284 if (engine
->disable_lite_restore_wa
)
285 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
289 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
290 * descriptor for a pinned context
292 * @ctx: Context to work on
293 * @engine: Engine the descriptor will be used with
295 * The context descriptor encodes various attributes of a context,
296 * including its GTT address and some flags. Because it's fairly
297 * expensive to calculate, we'll just do it once and cache the result,
298 * which remains valid until the context is unpinned.
300 * This is what a descriptor looks like, from LSB to MSB:
301 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
302 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
303 * bits 32-52: ctx ID, a globally unique tag
304 * bits 53-54: mbz, reserved for use by hardware
305 * bits 55-63: group ID, currently unused and set to 0
308 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
309 struct intel_engine_cs
*engine
)
311 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
314 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
316 desc
= ctx
->desc_template
; /* bits 3-4 */
317 desc
|= engine
->ctx_desc_template
; /* bits 0-11 */
318 desc
|= ce
->lrc_vma
->node
.start
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
320 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
325 uint64_t intel_lr_context_descriptor(struct i915_gem_context
*ctx
,
326 struct intel_engine_cs
*engine
)
328 return ctx
->engine
[engine
->id
].lrc_desc
;
331 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
332 struct drm_i915_gem_request
*rq1
)
335 struct intel_engine_cs
*engine
= rq0
->engine
;
336 struct drm_i915_private
*dev_priv
= rq0
->i915
;
340 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
341 rq1
->elsp_submitted
++;
346 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
347 rq0
->elsp_submitted
++;
349 /* You must always write both descriptors in the order below. */
350 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
351 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
353 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
354 /* The context is automatically loaded after the following */
355 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
357 /* ELSP is a wo register, use another nearby reg for posting */
358 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
362 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
364 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
365 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
366 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
367 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
370 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
372 struct intel_engine_cs
*engine
= rq
->engine
;
373 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
374 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
376 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
378 /* True 32b PPGTT with dynamic page allocation: update PDP
379 * registers and point the unallocated PDPs to scratch page.
380 * PML4 is allocated during ppgtt init, so this is not needed
383 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
384 execlists_update_context_pdps(ppgtt
, reg_state
);
387 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
388 struct drm_i915_gem_request
*rq1
)
390 struct drm_i915_private
*dev_priv
= rq0
->i915
;
391 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
393 execlists_update_context(rq0
);
396 execlists_update_context(rq1
);
398 spin_lock_irq(&dev_priv
->uncore
.lock
);
399 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
401 execlists_elsp_write(rq0
, rq1
);
403 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
404 spin_unlock_irq(&dev_priv
->uncore
.lock
);
407 static inline void execlists_context_status_change(
408 struct drm_i915_gem_request
*rq
,
409 unsigned long status
)
412 * Only used when GVT-g is enabled now. When GVT-g is disabled,
413 * The compiler should eliminate this function as dead-code.
415 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
418 atomic_notifier_call_chain(&rq
->ctx
->status_notifier
, status
, rq
);
421 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
423 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
424 struct drm_i915_gem_request
*cursor
, *tmp
;
426 assert_spin_locked(&engine
->execlist_lock
);
429 * If irqs are not active generate a warning as batches that finish
430 * without the irqs may get lost and a GPU Hang may occur.
432 WARN_ON(!intel_irqs_enabled(engine
->i915
));
434 /* Try to read in pairs */
435 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
439 } else if (req0
->ctx
== cursor
->ctx
) {
440 /* Same ctx: ignore first request, as second request
441 * will update tail past first request's workload */
442 cursor
->elsp_submitted
= req0
->elsp_submitted
;
443 list_del(&req0
->execlist_link
);
444 i915_gem_request_unreference(req0
);
447 if (IS_ENABLED(CONFIG_DRM_I915_GVT
)) {
449 * req0 (after merged) ctx requires single
450 * submission, stop picking
452 if (req0
->ctx
->execlists_force_single_submission
)
455 * req0 ctx doesn't require single submission,
456 * but next req ctx requires, stop picking
458 if (cursor
->ctx
->execlists_force_single_submission
)
462 WARN_ON(req1
->elsp_submitted
);
470 execlists_context_status_change(req0
, INTEL_CONTEXT_SCHEDULE_IN
);
473 execlists_context_status_change(req1
,
474 INTEL_CONTEXT_SCHEDULE_IN
);
476 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
478 * WaIdleLiteRestore: make sure we never cause a lite restore
481 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
482 * resubmit the request. See gen8_emit_request() for where we
483 * prepare the padding after the end of the request.
485 struct intel_ringbuffer
*ringbuf
;
487 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
489 req0
->tail
&= ringbuf
->size
- 1;
492 execlists_submit_requests(req0
, req1
);
496 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 ctx_id
)
498 struct drm_i915_gem_request
*head_req
;
500 assert_spin_locked(&engine
->execlist_lock
);
502 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
503 struct drm_i915_gem_request
,
506 if (WARN_ON(!head_req
|| (head_req
->ctx_hw_id
!= ctx_id
)))
509 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
511 if (--head_req
->elsp_submitted
> 0)
514 execlists_context_status_change(head_req
, INTEL_CONTEXT_SCHEDULE_OUT
);
516 list_del(&head_req
->execlist_link
);
517 i915_gem_request_unreference(head_req
);
523 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
526 struct drm_i915_private
*dev_priv
= engine
->i915
;
529 read_pointer
%= GEN8_CSB_ENTRIES
;
531 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
533 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
536 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
543 * intel_lrc_irq_handler() - handle Context Switch interrupts
544 * @data: tasklet handler passed in unsigned long
546 * Check the unread Context Status Buffers and manage the submission of new
547 * contexts to the ELSP accordingly.
549 static void intel_lrc_irq_handler(unsigned long data
)
551 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
552 struct drm_i915_private
*dev_priv
= engine
->i915
;
554 unsigned int read_pointer
, write_pointer
;
555 u32 csb
[GEN8_CSB_ENTRIES
][2];
556 unsigned int csb_read
= 0, i
;
557 unsigned int submit_contexts
= 0;
559 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
561 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
563 read_pointer
= engine
->next_context_status_buffer
;
564 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
565 if (read_pointer
> write_pointer
)
566 write_pointer
+= GEN8_CSB_ENTRIES
;
568 while (read_pointer
< write_pointer
) {
569 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
571 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
576 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
578 /* Update the read pointer to the old write pointer. Manual ringbuffer
579 * management ftw </sarcasm> */
580 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
581 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
582 engine
->next_context_status_buffer
<< 8));
584 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
586 spin_lock(&engine
->execlist_lock
);
588 for (i
= 0; i
< csb_read
; i
++) {
589 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
590 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
591 if (execlists_check_remove_request(engine
, csb
[i
][1]))
592 WARN(1, "Lite Restored request removed from queue\n");
594 WARN(1, "Preemption without Lite Restore\n");
597 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
598 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
600 execlists_check_remove_request(engine
, csb
[i
][1]);
603 if (submit_contexts
) {
604 if (!engine
->disable_lite_restore_wa
||
605 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
606 execlists_context_unqueue(engine
);
609 spin_unlock(&engine
->execlist_lock
);
611 if (unlikely(submit_contexts
> 2))
612 DRM_ERROR("More than two context complete events?\n");
615 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
617 struct intel_engine_cs
*engine
= request
->engine
;
618 struct drm_i915_gem_request
*cursor
;
619 int num_elements
= 0;
621 spin_lock_bh(&engine
->execlist_lock
);
623 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
624 if (++num_elements
> 2)
627 if (num_elements
> 2) {
628 struct drm_i915_gem_request
*tail_req
;
630 tail_req
= list_last_entry(&engine
->execlist_queue
,
631 struct drm_i915_gem_request
,
634 if (request
->ctx
== tail_req
->ctx
) {
635 WARN(tail_req
->elsp_submitted
!= 0,
636 "More than 2 already-submitted reqs queued\n");
637 list_del(&tail_req
->execlist_link
);
638 i915_gem_request_unreference(tail_req
);
642 i915_gem_request_reference(request
);
643 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
644 request
->ctx_hw_id
= request
->ctx
->hw_id
;
645 if (num_elements
== 0)
646 execlists_context_unqueue(engine
);
648 spin_unlock_bh(&engine
->execlist_lock
);
651 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
653 struct intel_engine_cs
*engine
= req
->engine
;
654 uint32_t flush_domains
;
658 if (engine
->gpu_caches_dirty
)
659 flush_domains
= I915_GEM_GPU_DOMAINS
;
661 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
665 engine
->gpu_caches_dirty
= false;
669 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
670 struct list_head
*vmas
)
672 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
673 struct i915_vma
*vma
;
674 uint32_t flush_domains
= 0;
675 bool flush_chipset
= false;
678 list_for_each_entry(vma
, vmas
, exec_list
) {
679 struct drm_i915_gem_object
*obj
= vma
->obj
;
681 if (obj
->active
& other_rings
) {
682 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
687 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
688 flush_chipset
|= i915_gem_clflush_object(obj
, false);
690 flush_domains
|= obj
->base
.write_domain
;
693 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
696 /* Unconditionally invalidate gpu caches and ensure that we do flush
697 * any residual writes from the previous batch.
699 return logical_ring_invalidate_all_caches(req
);
702 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
704 struct intel_engine_cs
*engine
= request
->engine
;
705 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
708 /* Flush enough space to reduce the likelihood of waiting after
709 * we start building the request - in which case we will just
710 * have to repeat work.
712 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
715 ret
= execlists_context_deferred_alloc(request
->ctx
, engine
);
720 request
->ringbuf
= ce
->ringbuf
;
722 if (i915
.enable_guc_submission
) {
724 * Check that the GuC has space for the request before
725 * going any further, as the i915_add_request() call
726 * later on mustn't fail ...
728 ret
= i915_guc_wq_check_space(request
);
733 ret
= intel_lr_context_pin(request
->ctx
, engine
);
737 ret
= intel_ring_begin(request
, 0);
741 if (!ce
->initialised
) {
742 ret
= engine
->init_context(request
);
746 ce
->initialised
= true;
749 /* Note that after this point, we have committed to using
750 * this request as it is being used to both track the
751 * state of engine initialisation and liveness of the
752 * golden renderstate above. Think twice before you try
753 * to cancel/unwind this request now.
756 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
760 intel_lr_context_unpin(request
->ctx
, engine
);
765 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
766 * @request: Request to advance the logical ringbuffer of.
768 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
769 * really happens during submission is that the context and current tail will be placed
770 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
771 * point, the tail *inside* the context is updated and the ELSP written to.
774 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
776 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
777 struct intel_engine_cs
*engine
= request
->engine
;
779 intel_logical_ring_advance(ringbuf
);
780 request
->tail
= ringbuf
->tail
;
783 * Here we add two extra NOOPs as padding to avoid
784 * lite restore of a context with HEAD==TAIL.
786 * Caller must reserve WA_TAIL_DWORDS for us!
788 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
789 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
790 intel_logical_ring_advance(ringbuf
);
792 /* We keep the previous context alive until we retire the following
793 * request. This ensures that any the context object is still pinned
794 * for any residual writes the HW makes into it on the context switch
795 * into the next object following the breadcrumb. Otherwise, we may
796 * retire the context too early.
798 request
->previous_context
= engine
->last_context
;
799 engine
->last_context
= request
->ctx
;
801 if (i915
.enable_guc_submission
)
802 i915_guc_submit(request
);
804 execlists_context_queue(request
);
810 * execlists_submission() - submit a batchbuffer for execution, Execlists style
811 * @params: execbuffer call parameters.
812 * @args: execbuffer call arguments.
813 * @vmas: list of vmas.
815 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
816 * away the submission details of the execbuffer ioctl call.
818 * Return: non-zero if the submission fails.
820 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
821 struct drm_i915_gem_execbuffer2
*args
,
822 struct list_head
*vmas
)
824 struct drm_device
*dev
= params
->dev
;
825 struct intel_engine_cs
*engine
= params
->engine
;
826 struct drm_i915_private
*dev_priv
= to_i915(dev
);
827 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
833 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
834 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
835 switch (instp_mode
) {
836 case I915_EXEC_CONSTANTS_REL_GENERAL
:
837 case I915_EXEC_CONSTANTS_ABSOLUTE
:
838 case I915_EXEC_CONSTANTS_REL_SURFACE
:
839 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
840 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
844 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
845 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
846 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
850 /* The HW changed the meaning on this bit on gen6 */
851 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
855 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
859 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
860 DRM_DEBUG("sol reset is gen7 only\n");
864 ret
= execlists_move_to_gpu(params
->request
, vmas
);
868 if (engine
== &dev_priv
->engine
[RCS
] &&
869 instp_mode
!= dev_priv
->relative_constants_mode
) {
870 ret
= intel_ring_begin(params
->request
, 4);
874 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
875 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
876 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
877 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
878 intel_logical_ring_advance(ringbuf
);
880 dev_priv
->relative_constants_mode
= instp_mode
;
883 exec_start
= params
->batch_obj_vm_offset
+
884 args
->batch_start_offset
;
886 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
890 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
892 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
897 void intel_execlists_cancel_requests(struct intel_engine_cs
*engine
)
899 struct drm_i915_gem_request
*req
, *tmp
;
900 LIST_HEAD(cancel_list
);
902 WARN_ON(!mutex_is_locked(&engine
->i915
->drm
.struct_mutex
));
904 spin_lock_bh(&engine
->execlist_lock
);
905 list_replace_init(&engine
->execlist_queue
, &cancel_list
);
906 spin_unlock_bh(&engine
->execlist_lock
);
908 list_for_each_entry_safe(req
, tmp
, &cancel_list
, execlist_link
) {
909 list_del(&req
->execlist_link
);
910 i915_gem_request_unreference(req
);
914 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
916 struct drm_i915_private
*dev_priv
= engine
->i915
;
919 if (!intel_engine_initialized(engine
))
922 ret
= intel_engine_idle(engine
);
924 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
927 /* TODO: Is this correct with Execlists enabled? */
928 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
929 if (intel_wait_for_register(dev_priv
,
930 RING_MI_MODE(engine
->mmio_base
),
931 MODE_IDLE
, MODE_IDLE
,
933 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
936 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
939 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
941 struct intel_engine_cs
*engine
= req
->engine
;
944 if (!engine
->gpu_caches_dirty
)
947 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
951 engine
->gpu_caches_dirty
= false;
955 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
956 struct intel_engine_cs
*engine
)
958 struct drm_i915_private
*dev_priv
= ctx
->i915
;
959 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
964 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
969 ret
= i915_gem_obj_ggtt_pin(ce
->state
, GEN8_LR_CONTEXT_ALIGN
,
970 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
974 vaddr
= i915_gem_object_pin_map(ce
->state
);
976 ret
= PTR_ERR(vaddr
);
980 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
982 ret
= intel_pin_and_map_ringbuffer_obj(dev_priv
, ce
->ringbuf
);
986 i915_gem_context_reference(ctx
);
987 ce
->lrc_vma
= i915_gem_obj_to_ggtt(ce
->state
);
988 intel_lr_context_descriptor_update(ctx
, engine
);
990 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ce
->ringbuf
->vma
->node
.start
;
991 ce
->lrc_reg_state
= lrc_reg_state
;
992 ce
->state
->dirty
= true;
994 /* Invalidate GuC TLB. */
995 if (i915
.enable_guc_submission
)
996 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1001 i915_gem_object_unpin_map(ce
->state
);
1003 i915_gem_object_ggtt_unpin(ce
->state
);
1009 void intel_lr_context_unpin(struct i915_gem_context
*ctx
,
1010 struct intel_engine_cs
*engine
)
1012 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
1014 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
1015 GEM_BUG_ON(ce
->pin_count
== 0);
1017 if (--ce
->pin_count
)
1020 intel_unpin_ringbuffer_obj(ce
->ringbuf
);
1022 i915_gem_object_unpin_map(ce
->state
);
1023 i915_gem_object_ggtt_unpin(ce
->state
);
1027 ce
->lrc_reg_state
= NULL
;
1029 i915_gem_context_unreference(ctx
);
1032 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1035 struct intel_engine_cs
*engine
= req
->engine
;
1036 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1037 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
1042 engine
->gpu_caches_dirty
= true;
1043 ret
= logical_ring_flush_all_caches(req
);
1047 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
1051 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1052 for (i
= 0; i
< w
->count
; i
++) {
1053 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1054 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1056 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1058 intel_logical_ring_advance(ringbuf
);
1060 engine
->gpu_caches_dirty
= true;
1061 ret
= logical_ring_flush_all_caches(req
);
1068 #define wa_ctx_emit(batch, index, cmd) \
1070 int __index = (index)++; \
1071 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1074 batch[__index] = (cmd); \
1077 #define wa_ctx_emit_reg(batch, index, reg) \
1078 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1081 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1082 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1083 * but there is a slight complication as this is applied in WA batch where the
1084 * values are only initialized once so we cannot take register value at the
1085 * beginning and reuse it further; hence we save its value to memory, upload a
1086 * constant value with bit21 set and then we restore it back with the saved value.
1087 * To simplify the WA, a constant value is formed by using the default value
1088 * of this register. This shouldn't be a problem because we are only modifying
1089 * it for a short period and this batch in non-premptible. We can ofcourse
1090 * use additional instructions that read the actual value of the register
1091 * at that time and set our bit of interest but it makes the WA complicated.
1093 * This WA is also required for Gen9 so extracting as a function avoids
1096 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1097 uint32_t *const batch
,
1100 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1103 * WaDisableLSQCROPERFforOCL:skl,kbl
1104 * This WA is implemented in skl_init_clock_gating() but since
1105 * this batch updates GEN8_L3SQCREG4 with default value we need to
1106 * set this bit here to retain the WA during flush.
1108 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_E0
) ||
1109 IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_E0
))
1110 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1112 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1113 MI_SRM_LRM_GLOBAL_GTT
));
1114 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1115 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1116 wa_ctx_emit(batch
, index
, 0);
1118 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1119 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1120 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1122 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1123 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1124 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1125 wa_ctx_emit(batch
, index
, 0);
1126 wa_ctx_emit(batch
, index
, 0);
1127 wa_ctx_emit(batch
, index
, 0);
1128 wa_ctx_emit(batch
, index
, 0);
1130 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1131 MI_SRM_LRM_GLOBAL_GTT
));
1132 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1133 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1134 wa_ctx_emit(batch
, index
, 0);
1139 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1141 uint32_t start_alignment
)
1143 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1146 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1148 uint32_t size_alignment
)
1150 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1152 WARN(wa_ctx
->size
% size_alignment
,
1153 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1154 wa_ctx
->size
, size_alignment
);
1159 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1161 * @engine: only applicable for RCS
1162 * @wa_ctx: structure representing wa_ctx
1163 * offset: specifies start of the batch, should be cache-aligned. This is updated
1164 * with the offset value received as input.
1165 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1166 * @batch: page in which WA are loaded
1167 * @offset: This field specifies the start of the batch, it should be
1168 * cache-aligned otherwise it is adjusted accordingly.
1169 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1170 * initialized at the beginning and shared across all contexts but this field
1171 * helps us to have multiple batches at different offsets and select them based
1172 * on a criteria. At the moment this batch always start at the beginning of the page
1173 * and at this point we don't have multiple wa_ctx batch buffers.
1175 * The number of WA applied are not known at the beginning; we use this field
1176 * to return the no of DWORDS written.
1178 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1179 * so it adds NOOPs as padding to make it cacheline aligned.
1180 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1181 * makes a complete batch buffer.
1183 * Return: non-zero if we exceed the PAGE_SIZE limit.
1186 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1187 struct i915_wa_ctx_bb
*wa_ctx
,
1188 uint32_t *const batch
,
1191 uint32_t scratch_addr
;
1192 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1194 /* WaDisableCtxRestoreArbitration:bdw,chv */
1195 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1197 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1198 if (IS_BROADWELL(engine
->i915
)) {
1199 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1205 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1206 /* Actual scratch location is at 128 bytes offset */
1207 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1209 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1210 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1211 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1212 PIPE_CONTROL_CS_STALL
|
1213 PIPE_CONTROL_QW_WRITE
));
1214 wa_ctx_emit(batch
, index
, scratch_addr
);
1215 wa_ctx_emit(batch
, index
, 0);
1216 wa_ctx_emit(batch
, index
, 0);
1217 wa_ctx_emit(batch
, index
, 0);
1219 /* Pad to end of cacheline */
1220 while (index
% CACHELINE_DWORDS
)
1221 wa_ctx_emit(batch
, index
, MI_NOOP
);
1224 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1225 * execution depends on the length specified in terms of cache lines
1226 * in the register CTX_RCS_INDIRECT_CTX
1229 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1233 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1235 * @engine: only applicable for RCS
1236 * @wa_ctx: structure representing wa_ctx
1237 * offset: specifies start of the batch, should be cache-aligned.
1238 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1239 * @batch: page in which WA are loaded
1240 * @offset: This field specifies the start of this batch.
1241 * This batch is started immediately after indirect_ctx batch. Since we ensure
1242 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1244 * The number of DWORDS written are returned using this field.
1246 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1247 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1249 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1250 struct i915_wa_ctx_bb
*wa_ctx
,
1251 uint32_t *const batch
,
1254 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1256 /* WaDisableCtxRestoreArbitration:bdw,chv */
1257 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1259 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1261 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1264 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1265 struct i915_wa_ctx_bb
*wa_ctx
,
1266 uint32_t *const batch
,
1270 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1272 /* WaDisableCtxRestoreArbitration:skl,bxt */
1273 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1274 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1275 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1277 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1278 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1283 /* WaClearSlmSpaceAtContextSwitch:kbl */
1284 /* Actual scratch location is at 128 bytes offset */
1285 if (IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_A0
)) {
1286 uint32_t scratch_addr
1287 = engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1289 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1290 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1291 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1292 PIPE_CONTROL_CS_STALL
|
1293 PIPE_CONTROL_QW_WRITE
));
1294 wa_ctx_emit(batch
, index
, scratch_addr
);
1295 wa_ctx_emit(batch
, index
, 0);
1296 wa_ctx_emit(batch
, index
, 0);
1297 wa_ctx_emit(batch
, index
, 0);
1300 /* WaMediaPoolStateCmdInWABB:bxt */
1301 if (HAS_POOLED_EU(engine
->i915
)) {
1303 * EU pool configuration is setup along with golden context
1304 * during context initialization. This value depends on
1305 * device type (2x6 or 3x6) and needs to be updated based
1306 * on which subslice is disabled especially for 2x6
1307 * devices, however it is safe to load default
1308 * configuration of 3x6 device instead of masking off
1309 * corresponding bits because HW ignores bits of a disabled
1310 * subslice and drops down to appropriate config. Please
1311 * see render_state_setup() in i915_gem_render_state.c for
1312 * possible configurations, to avoid duplication they are
1313 * not shown here again.
1315 u32 eu_pool_config
= 0x00777000;
1316 wa_ctx_emit(batch
, index
, GEN9_MEDIA_POOL_STATE
);
1317 wa_ctx_emit(batch
, index
, GEN9_MEDIA_POOL_ENABLE
);
1318 wa_ctx_emit(batch
, index
, eu_pool_config
);
1319 wa_ctx_emit(batch
, index
, 0);
1320 wa_ctx_emit(batch
, index
, 0);
1321 wa_ctx_emit(batch
, index
, 0);
1324 /* Pad to end of cacheline */
1325 while (index
% CACHELINE_DWORDS
)
1326 wa_ctx_emit(batch
, index
, MI_NOOP
);
1328 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1331 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1332 struct i915_wa_ctx_bb
*wa_ctx
,
1333 uint32_t *const batch
,
1336 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1338 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1339 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_B0
) ||
1340 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
)) {
1341 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1342 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1343 wa_ctx_emit(batch
, index
,
1344 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1345 wa_ctx_emit(batch
, index
, MI_NOOP
);
1348 /* WaClearTdlStateAckDirtyBits:bxt */
1349 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_B0
)) {
1350 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1352 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1353 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1355 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1356 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1358 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1359 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1361 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1362 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1363 wa_ctx_emit(batch
, index
, 0x0);
1364 wa_ctx_emit(batch
, index
, MI_NOOP
);
1367 /* WaDisableCtxRestoreArbitration:skl,bxt */
1368 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1369 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1370 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1372 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1374 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1377 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1381 engine
->wa_ctx
.obj
= i915_gem_object_create(&engine
->i915
->drm
,
1383 if (IS_ERR(engine
->wa_ctx
.obj
)) {
1384 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1385 ret
= PTR_ERR(engine
->wa_ctx
.obj
);
1386 engine
->wa_ctx
.obj
= NULL
;
1390 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1392 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1394 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1401 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1403 if (engine
->wa_ctx
.obj
) {
1404 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1405 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1406 engine
->wa_ctx
.obj
= NULL
;
1410 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1416 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1418 WARN_ON(engine
->id
!= RCS
);
1420 /* update this when WA for higher Gen are added */
1421 if (INTEL_GEN(engine
->i915
) > 9) {
1422 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1423 INTEL_GEN(engine
->i915
));
1427 /* some WA perform writes to scratch page, ensure it is valid */
1428 if (engine
->scratch
.obj
== NULL
) {
1429 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1433 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1435 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1439 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1440 batch
= kmap_atomic(page
);
1443 if (IS_GEN8(engine
->i915
)) {
1444 ret
= gen8_init_indirectctx_bb(engine
,
1445 &wa_ctx
->indirect_ctx
,
1451 ret
= gen8_init_perctx_bb(engine
,
1457 } else if (IS_GEN9(engine
->i915
)) {
1458 ret
= gen9_init_indirectctx_bb(engine
,
1459 &wa_ctx
->indirect_ctx
,
1465 ret
= gen9_init_perctx_bb(engine
,
1474 kunmap_atomic(batch
);
1476 lrc_destroy_wa_ctx_obj(engine
);
1481 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1483 struct drm_i915_private
*dev_priv
= engine
->i915
;
1485 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1486 (u32
)engine
->status_page
.gfx_addr
);
1487 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1490 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1492 struct drm_i915_private
*dev_priv
= engine
->i915
;
1493 unsigned int next_context_status_buffer_hw
;
1495 lrc_init_hws(engine
);
1497 I915_WRITE_IMR(engine
,
1498 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1499 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1501 I915_WRITE(RING_MODE_GEN7(engine
),
1502 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1503 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1504 POSTING_READ(RING_MODE_GEN7(engine
));
1507 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1508 * zero, we need to read the write pointer from hardware and use its
1509 * value because "this register is power context save restored".
1510 * Effectively, these states have been observed:
1512 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1513 * BDW | CSB regs not reset | CSB regs reset |
1514 * CHT | CSB regs not reset | CSB regs not reset |
1518 next_context_status_buffer_hw
=
1519 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1522 * When the CSB registers are reset (also after power-up / gpu reset),
1523 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1524 * this special case, so the first element read is CSB[0].
1526 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1527 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1529 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1530 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1532 intel_engine_init_hangcheck(engine
);
1534 return intel_mocs_init_engine(engine
);
1537 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1539 struct drm_i915_private
*dev_priv
= engine
->i915
;
1542 ret
= gen8_init_common_ring(engine
);
1546 /* We need to disable the AsyncFlip performance optimisations in order
1547 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1548 * programmed to '1' on all products.
1550 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1552 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1554 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1556 return init_workarounds_ring(engine
);
1559 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1563 ret
= gen8_init_common_ring(engine
);
1567 return init_workarounds_ring(engine
);
1570 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1572 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1573 struct intel_engine_cs
*engine
= req
->engine
;
1574 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1575 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1578 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1582 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1583 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1584 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1586 intel_logical_ring_emit_reg(ringbuf
,
1587 GEN8_RING_PDP_UDW(engine
, i
));
1588 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1589 intel_logical_ring_emit_reg(ringbuf
,
1590 GEN8_RING_PDP_LDW(engine
, i
));
1591 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1594 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1595 intel_logical_ring_advance(ringbuf
);
1600 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1601 u64 offset
, unsigned dispatch_flags
)
1603 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1604 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1607 /* Don't rely in hw updating PDPs, specially in lite-restore.
1608 * Ideally, we should set Force PD Restore in ctx descriptor,
1609 * but we can't. Force Restore would be a second option, but
1610 * it is unsafe in case of lite-restore (because the ctx is
1611 * not idle). PML4 is allocated during ppgtt init so this is
1612 * not needed in 48-bit.*/
1613 if (req
->ctx
->ppgtt
&&
1614 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1615 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1616 !intel_vgpu_active(req
->i915
)) {
1617 ret
= intel_logical_ring_emit_pdps(req
);
1622 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1625 ret
= intel_ring_begin(req
, 4);
1629 /* FIXME(BDW): Address space and security selectors. */
1630 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1632 (dispatch_flags
& I915_DISPATCH_RS
?
1633 MI_BATCH_RESOURCE_STREAMER
: 0));
1634 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1635 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1636 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1637 intel_logical_ring_advance(ringbuf
);
1642 static void gen8_logical_ring_enable_irq(struct intel_engine_cs
*engine
)
1644 struct drm_i915_private
*dev_priv
= engine
->i915
;
1645 I915_WRITE_IMR(engine
,
1646 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1647 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1650 static void gen8_logical_ring_disable_irq(struct intel_engine_cs
*engine
)
1652 struct drm_i915_private
*dev_priv
= engine
->i915
;
1653 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1656 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1657 u32 invalidate_domains
,
1660 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1661 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1662 struct drm_i915_private
*dev_priv
= request
->i915
;
1666 ret
= intel_ring_begin(request
, 4);
1670 cmd
= MI_FLUSH_DW
+ 1;
1672 /* We always require a command barrier so that subsequent
1673 * commands, such as breadcrumb interrupts, are strictly ordered
1674 * wrt the contents of the write cache being flushed to memory
1675 * (and thus being coherent from the CPU).
1677 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1679 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1680 cmd
|= MI_INVALIDATE_TLB
;
1681 if (engine
== &dev_priv
->engine
[VCS
])
1682 cmd
|= MI_INVALIDATE_BSD
;
1685 intel_logical_ring_emit(ringbuf
, cmd
);
1686 intel_logical_ring_emit(ringbuf
,
1687 I915_GEM_HWS_SCRATCH_ADDR
|
1688 MI_FLUSH_DW_USE_GTT
);
1689 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1690 intel_logical_ring_emit(ringbuf
, 0); /* value */
1691 intel_logical_ring_advance(ringbuf
);
1696 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1697 u32 invalidate_domains
,
1700 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1701 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1702 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1703 bool vf_flush_wa
= false, dc_flush_wa
= false;
1708 flags
|= PIPE_CONTROL_CS_STALL
;
1710 if (flush_domains
) {
1711 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1712 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1713 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1714 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1717 if (invalidate_domains
) {
1718 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1719 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1720 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1721 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1722 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1723 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1724 flags
|= PIPE_CONTROL_QW_WRITE
;
1725 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1728 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1731 if (IS_GEN9(request
->i915
))
1734 /* WaForGAMHang:kbl */
1735 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1747 ret
= intel_ring_begin(request
, len
);
1752 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1753 intel_logical_ring_emit(ringbuf
, 0);
1754 intel_logical_ring_emit(ringbuf
, 0);
1755 intel_logical_ring_emit(ringbuf
, 0);
1756 intel_logical_ring_emit(ringbuf
, 0);
1757 intel_logical_ring_emit(ringbuf
, 0);
1761 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1762 intel_logical_ring_emit(ringbuf
, PIPE_CONTROL_DC_FLUSH_ENABLE
);
1763 intel_logical_ring_emit(ringbuf
, 0);
1764 intel_logical_ring_emit(ringbuf
, 0);
1765 intel_logical_ring_emit(ringbuf
, 0);
1766 intel_logical_ring_emit(ringbuf
, 0);
1769 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1770 intel_logical_ring_emit(ringbuf
, flags
);
1771 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1772 intel_logical_ring_emit(ringbuf
, 0);
1773 intel_logical_ring_emit(ringbuf
, 0);
1774 intel_logical_ring_emit(ringbuf
, 0);
1777 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1778 intel_logical_ring_emit(ringbuf
, PIPE_CONTROL_CS_STALL
);
1779 intel_logical_ring_emit(ringbuf
, 0);
1780 intel_logical_ring_emit(ringbuf
, 0);
1781 intel_logical_ring_emit(ringbuf
, 0);
1782 intel_logical_ring_emit(ringbuf
, 0);
1785 intel_logical_ring_advance(ringbuf
);
1790 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1793 * On BXT A steppings there is a HW coherency issue whereby the
1794 * MI_STORE_DATA_IMM storing the completed request's seqno
1795 * occasionally doesn't invalidate the CPU cache. Work around this by
1796 * clflushing the corresponding cacheline whenever the caller wants
1797 * the coherency to be guaranteed. Note that this cacheline is known
1798 * to be clean at this point, since we only write it in
1799 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1800 * this clflush in practice becomes an invalidate operation.
1802 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1806 * Reserve space for 2 NOOPs at the end of each request to be
1807 * used as a workaround for not being allowed to do lite
1808 * restore with HEAD==TAIL (WaIdleLiteRestore).
1810 #define WA_TAIL_DWORDS 2
1812 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1814 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1817 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1821 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1822 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1824 intel_logical_ring_emit(ringbuf
,
1825 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1826 intel_logical_ring_emit(ringbuf
,
1827 intel_hws_seqno_address(request
->engine
) |
1828 MI_FLUSH_DW_USE_GTT
);
1829 intel_logical_ring_emit(ringbuf
, 0);
1830 intel_logical_ring_emit(ringbuf
, request
->seqno
);
1831 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1832 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1833 return intel_logical_ring_advance_and_submit(request
);
1836 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1838 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1841 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1845 /* We're using qword write, seqno should be aligned to 8 bytes. */
1846 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1848 /* w/a for post sync ops following a GPGPU operation we
1849 * need a prior CS_STALL, which is emitted by the flush
1850 * following the batch.
1852 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1853 intel_logical_ring_emit(ringbuf
,
1854 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1855 PIPE_CONTROL_CS_STALL
|
1856 PIPE_CONTROL_QW_WRITE
));
1857 intel_logical_ring_emit(ringbuf
,
1858 intel_hws_seqno_address(request
->engine
));
1859 intel_logical_ring_emit(ringbuf
, 0);
1860 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1861 /* We're thrashing one dword of HWS. */
1862 intel_logical_ring_emit(ringbuf
, 0);
1863 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1864 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1865 return intel_logical_ring_advance_and_submit(request
);
1868 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1870 struct render_state so
;
1873 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1877 if (so
.rodata
== NULL
)
1880 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1881 I915_DISPATCH_SECURE
);
1885 ret
= req
->engine
->emit_bb_start(req
,
1886 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1887 I915_DISPATCH_SECURE
);
1891 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1894 i915_gem_render_state_fini(&so
);
1898 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1902 ret
= intel_logical_ring_workarounds_emit(req
);
1906 ret
= intel_rcs_context_init_mocs(req
);
1908 * Failing to program the MOCS is non-fatal.The system will not
1909 * run at peak performance. So generate an error and carry on.
1912 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1914 return intel_lr_context_render_state_init(req
);
1918 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1920 * @engine: Engine Command Streamer.
1923 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1925 struct drm_i915_private
*dev_priv
;
1927 if (!intel_engine_initialized(engine
))
1931 * Tasklet cannot be active at this point due intel_mark_active/idle
1932 * so this is just for documentation.
1934 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1935 tasklet_kill(&engine
->irq_tasklet
);
1937 dev_priv
= engine
->i915
;
1939 if (engine
->buffer
) {
1940 intel_logical_ring_stop(engine
);
1941 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1944 if (engine
->cleanup
)
1945 engine
->cleanup(engine
);
1947 i915_cmd_parser_fini_ring(engine
);
1948 i915_gem_batch_pool_fini(&engine
->batch_pool
);
1950 intel_engine_fini_breadcrumbs(engine
);
1952 if (engine
->status_page
.obj
) {
1953 i915_gem_object_unpin_map(engine
->status_page
.obj
);
1954 engine
->status_page
.obj
= NULL
;
1956 intel_lr_context_unpin(dev_priv
->kernel_context
, engine
);
1958 engine
->idle_lite_restore_wa
= 0;
1959 engine
->disable_lite_restore_wa
= false;
1960 engine
->ctx_desc_template
= 0;
1962 lrc_destroy_wa_ctx_obj(engine
);
1963 engine
->i915
= NULL
;
1967 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1969 /* Default vfuncs which can be overriden by each engine. */
1970 engine
->init_hw
= gen8_init_common_ring
;
1971 engine
->emit_request
= gen8_emit_request
;
1972 engine
->emit_flush
= gen8_emit_flush
;
1973 engine
->irq_enable
= gen8_logical_ring_enable_irq
;
1974 engine
->irq_disable
= gen8_logical_ring_disable_irq
;
1975 engine
->emit_bb_start
= gen8_emit_bb_start
;
1976 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1977 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1981 logical_ring_default_irqs(struct intel_engine_cs
*engine
)
1983 unsigned shift
= engine
->irq_shift
;
1984 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1985 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1989 lrc_setup_hws(struct intel_engine_cs
*engine
,
1990 struct drm_i915_gem_object
*dctx_obj
)
1994 /* The HWSP is part of the default context object in LRC mode. */
1995 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
) +
1996 LRC_PPHWSP_PN
* PAGE_SIZE
;
1997 hws
= i915_gem_object_pin_map(dctx_obj
);
1999 return PTR_ERR(hws
);
2000 engine
->status_page
.page_addr
= hws
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
2001 engine
->status_page
.obj
= dctx_obj
;
2007 logical_ring_setup(struct intel_engine_cs
*engine
)
2009 struct drm_i915_private
*dev_priv
= engine
->i915
;
2010 enum forcewake_domains fw_domains
;
2012 intel_engine_setup_common(engine
);
2014 /* Intentionally left blank. */
2015 engine
->buffer
= NULL
;
2017 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
2021 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2022 RING_CONTEXT_STATUS_PTR(engine
),
2023 FW_REG_READ
| FW_REG_WRITE
);
2025 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2026 RING_CONTEXT_STATUS_BUF_BASE(engine
),
2029 engine
->fw_domains
= fw_domains
;
2031 tasklet_init(&engine
->irq_tasklet
,
2032 intel_lrc_irq_handler
, (unsigned long)engine
);
2034 logical_ring_init_platform_invariants(engine
);
2035 logical_ring_default_vfuncs(engine
);
2036 logical_ring_default_irqs(engine
);
2040 logical_ring_init(struct intel_engine_cs
*engine
)
2042 struct i915_gem_context
*dctx
= engine
->i915
->kernel_context
;
2045 ret
= intel_engine_init_common(engine
);
2049 ret
= execlists_context_deferred_alloc(dctx
, engine
);
2053 /* As this is the default context, always pin it */
2054 ret
= intel_lr_context_pin(dctx
, engine
);
2056 DRM_ERROR("Failed to pin context for %s: %d\n",
2061 /* And setup the hardware status page. */
2062 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
2064 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
2071 intel_logical_ring_cleanup(engine
);
2075 int logical_render_ring_init(struct intel_engine_cs
*engine
)
2077 struct drm_i915_private
*dev_priv
= engine
->i915
;
2080 logical_ring_setup(engine
);
2082 if (HAS_L3_DPF(dev_priv
))
2083 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2085 /* Override some for render ring. */
2086 if (INTEL_GEN(dev_priv
) >= 9)
2087 engine
->init_hw
= gen9_init_render_ring
;
2089 engine
->init_hw
= gen8_init_render_ring
;
2090 engine
->init_context
= gen8_init_rcs_context
;
2091 engine
->cleanup
= intel_fini_pipe_control
;
2092 engine
->emit_flush
= gen8_emit_flush_render
;
2093 engine
->emit_request
= gen8_emit_request_render
;
2095 ret
= intel_init_pipe_control(engine
, 4096);
2099 ret
= intel_init_workaround_bb(engine
);
2102 * We continue even if we fail to initialize WA batch
2103 * because we only expect rare glitches but nothing
2104 * critical to prevent us from using GPU
2106 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2110 ret
= logical_ring_init(engine
);
2112 lrc_destroy_wa_ctx_obj(engine
);
2118 int logical_xcs_ring_init(struct intel_engine_cs
*engine
)
2120 logical_ring_setup(engine
);
2122 return logical_ring_init(engine
);
2126 make_rpcs(struct drm_i915_private
*dev_priv
)
2131 * No explicit RPCS request is needed to ensure full
2132 * slice/subslice/EU enablement prior to Gen9.
2134 if (INTEL_GEN(dev_priv
) < 9)
2138 * Starting in Gen9, render power gating can leave
2139 * slice/subslice/EU in a partially enabled state. We
2140 * must make an explicit request through RPCS for full
2143 if (INTEL_INFO(dev_priv
)->has_slice_pg
) {
2144 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2145 rpcs
|= INTEL_INFO(dev_priv
)->slice_total
<<
2146 GEN8_RPCS_S_CNT_SHIFT
;
2147 rpcs
|= GEN8_RPCS_ENABLE
;
2150 if (INTEL_INFO(dev_priv
)->has_subslice_pg
) {
2151 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2152 rpcs
|= INTEL_INFO(dev_priv
)->subslice_per_slice
<<
2153 GEN8_RPCS_SS_CNT_SHIFT
;
2154 rpcs
|= GEN8_RPCS_ENABLE
;
2157 if (INTEL_INFO(dev_priv
)->has_eu_pg
) {
2158 rpcs
|= INTEL_INFO(dev_priv
)->eu_per_subslice
<<
2159 GEN8_RPCS_EU_MIN_SHIFT
;
2160 rpcs
|= INTEL_INFO(dev_priv
)->eu_per_subslice
<<
2161 GEN8_RPCS_EU_MAX_SHIFT
;
2162 rpcs
|= GEN8_RPCS_ENABLE
;
2168 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2170 u32 indirect_ctx_offset
;
2172 switch (INTEL_GEN(engine
->i915
)) {
2174 MISSING_CASE(INTEL_GEN(engine
->i915
));
2177 indirect_ctx_offset
=
2178 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2181 indirect_ctx_offset
=
2182 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2186 return indirect_ctx_offset
;
2190 populate_lr_context(struct i915_gem_context
*ctx
,
2191 struct drm_i915_gem_object
*ctx_obj
,
2192 struct intel_engine_cs
*engine
,
2193 struct intel_ringbuffer
*ringbuf
)
2195 struct drm_i915_private
*dev_priv
= ctx
->i915
;
2196 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2202 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2204 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2206 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2210 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2211 if (IS_ERR(vaddr
)) {
2212 ret
= PTR_ERR(vaddr
);
2213 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2216 ctx_obj
->dirty
= true;
2218 /* The second page of the context object contains some fields which must
2219 * be set up prior to the first execution. */
2220 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2222 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2223 * commands followed by (reg, value) pairs. The values we are setting here are
2224 * only for the first context restore: on a subsequent save, the GPU will
2225 * recreate this batchbuffer with new values (including all the missing
2226 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2227 reg_state
[CTX_LRI_HEADER_0
] =
2228 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2229 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2230 RING_CONTEXT_CONTROL(engine
),
2231 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2232 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2233 (HAS_RESOURCE_STREAMER(dev_priv
) ?
2234 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2235 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2237 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2239 /* Ring buffer start address is not known until the buffer is pinned.
2240 * It is written to the context image in execlists_update_context()
2242 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2243 RING_START(engine
->mmio_base
), 0);
2244 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2245 RING_CTL(engine
->mmio_base
),
2246 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2247 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2248 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2249 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2250 RING_BBADDR(engine
->mmio_base
), 0);
2251 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2252 RING_BBSTATE(engine
->mmio_base
),
2254 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2255 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2256 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2257 RING_SBBADDR(engine
->mmio_base
), 0);
2258 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2259 RING_SBBSTATE(engine
->mmio_base
), 0);
2260 if (engine
->id
== RCS
) {
2261 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2262 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2263 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2264 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2265 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2266 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2267 if (engine
->wa_ctx
.obj
) {
2268 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2269 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2271 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2272 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2273 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2275 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2276 intel_lr_indirect_ctx_offset(engine
) << 6;
2278 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2279 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2283 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2284 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2285 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2286 /* PDP values well be assigned later if needed */
2287 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2289 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2291 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2293 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2295 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2297 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2299 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2301 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2304 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2305 /* 64b PPGTT (48bit canonical)
2306 * PDP0_DESCRIPTOR contains the base address to PML4 and
2307 * other PDP Descriptors are ignored.
2309 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2312 * PDP*_DESCRIPTOR contains the base address of space supported.
2313 * With dynamic page allocation, PDPs may not be allocated at
2314 * this point. Point the unallocated PDPs to the scratch page
2316 execlists_update_context_pdps(ppgtt
, reg_state
);
2319 if (engine
->id
== RCS
) {
2320 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2321 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2322 make_rpcs(dev_priv
));
2325 i915_gem_object_unpin_map(ctx_obj
);
2331 * intel_lr_context_size() - return the size of the context for an engine
2332 * @engine: which engine to find the context size for
2334 * Each engine may require a different amount of space for a context image,
2335 * so when allocating (or copying) an image, this function can be used to
2336 * find the right size for the specific engine.
2338 * Return: size (in bytes) of an engine-specific context image
2340 * Note: this size includes the HWSP, which is part of the context image
2341 * in LRC mode, but does not include the "shared data page" used with
2342 * GuC submission. The caller should account for this if using the GuC.
2344 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2348 WARN_ON(INTEL_GEN(engine
->i915
) < 8);
2350 switch (engine
->id
) {
2352 if (INTEL_GEN(engine
->i915
) >= 9)
2353 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2355 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2361 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2369 * execlists_context_deferred_alloc() - create the LRC specific bits of a context
2370 * @ctx: LR context to create.
2371 * @engine: engine to be used with the context.
2373 * This function can be called more than once, with different engines, if we plan
2374 * to use the context with them. The context backing objects and the ringbuffers
2375 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2376 * the creation is a deferred call: it's better to make sure first that we need to use
2377 * a given ring with the context.
2379 * Return: non-zero on error.
2381 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
2382 struct intel_engine_cs
*engine
)
2384 struct drm_i915_gem_object
*ctx_obj
;
2385 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2386 uint32_t context_size
;
2387 struct intel_ringbuffer
*ringbuf
;
2392 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2394 /* One extra page as the sharing data between driver and GuC */
2395 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2397 ctx_obj
= i915_gem_object_create(&ctx
->i915
->drm
, context_size
);
2398 if (IS_ERR(ctx_obj
)) {
2399 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2400 return PTR_ERR(ctx_obj
);
2403 ringbuf
= intel_engine_create_ringbuffer(engine
, ctx
->ring_size
);
2404 if (IS_ERR(ringbuf
)) {
2405 ret
= PTR_ERR(ringbuf
);
2406 goto error_deref_obj
;
2409 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2411 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2415 ce
->ringbuf
= ringbuf
;
2416 ce
->state
= ctx_obj
;
2417 ce
->initialised
= engine
->init_context
== NULL
;
2422 intel_ringbuffer_free(ringbuf
);
2424 drm_gem_object_unreference(&ctx_obj
->base
);
2430 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2431 struct i915_gem_context
*ctx
)
2433 struct intel_engine_cs
*engine
;
2435 for_each_engine(engine
, dev_priv
) {
2436 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2437 struct drm_i915_gem_object
*ctx_obj
= ce
->state
;
2439 uint32_t *reg_state
;
2444 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2445 if (WARN_ON(IS_ERR(vaddr
)))
2448 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2449 ctx_obj
->dirty
= true;
2451 reg_state
[CTX_RING_HEAD
+1] = 0;
2452 reg_state
[CTX_RING_TAIL
+1] = 0;
2454 i915_gem_object_unpin_map(ctx_obj
);
2456 ce
->ringbuf
->head
= 0;
2457 ce
->ringbuf
->tail
= 0;