2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
194 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
199 #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \
200 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
201 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 ADVANCED_CONTEXT
= 0,
210 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
211 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
212 LEGACY_64B_CONTEXT :\
216 FAULT_AND_HALT
, /* Debug only */
218 FAULT_AND_CONTINUE
/* Unsupported */
220 #define GEN8_CTX_ID_SHIFT 32
221 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
223 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
);
226 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
228 * @enable_execlists: value of i915.enable_execlists module parameter.
230 * Only certain platforms support Execlists (the prerequisites being
231 * support for Logical Ring Contexts and Aliasing PPGTT or better).
233 * Return: 1 if Execlists is supported and has to be enabled.
235 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
237 WARN_ON(i915
.enable_ppgtt
== -1);
239 /* On platforms with execlist available, vGPU will only
240 * support execlist mode, no ring buffer mode.
242 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
245 if (INTEL_INFO(dev
)->gen
>= 9)
248 if (enable_execlists
== 0)
251 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
252 i915
.use_mmio_flip
>= 0)
259 * intel_execlists_ctx_id() - get the Execlists Context ID
260 * @ctx_obj: Logical Ring Context backing object.
262 * Do not confuse with ctx->id! Unfortunately we have a name overload
263 * here: the old context ID we pass to userspace as a handler so that
264 * they can refer to a context, and the new context ID we pass to the
265 * ELSP so that the GPU can inform us of the context status via
268 * Return: 20-bits globally unique context ID.
270 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
272 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
) +
273 LRC_PPHWSP_PN
* PAGE_SIZE
;
275 /* LRCA is required to be 4K aligned so the more significant 20 bits
276 * are globally unique */
280 static bool disable_lite_restore_wa(struct intel_engine_cs
*ring
)
282 struct drm_device
*dev
= ring
->dev
;
284 return ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
) ||
285 (IS_BROXTON(dev
) && INTEL_REVID(dev
) == BXT_REVID_A0
)) &&
286 (ring
->id
== VCS
|| ring
->id
== VCS2
);
289 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
290 struct intel_engine_cs
*ring
)
292 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
294 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
) +
295 LRC_PPHWSP_PN
* PAGE_SIZE
;
297 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
299 desc
= GEN8_CTX_VALID
;
300 desc
|= GEN8_CTX_ADDRESSING_MODE(dev
) << GEN8_CTX_ADDRESSING_MODE_SHIFT
;
301 if (IS_GEN8(ctx_obj
->base
.dev
))
302 desc
|= GEN8_CTX_L3LLC_COHERENT
;
303 desc
|= GEN8_CTX_PRIVILEGE
;
305 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
307 /* TODO: WaDisableLiteRestore when we start using semaphore
308 * signalling between Command Streamers */
309 /* desc |= GEN8_CTX_FORCE_RESTORE; */
311 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
312 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
313 if (disable_lite_restore_wa(ring
))
314 desc
|= GEN8_CTX_FORCE_RESTORE
;
319 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
320 struct drm_i915_gem_request
*rq1
)
323 struct intel_engine_cs
*ring
= rq0
->ring
;
324 struct drm_device
*dev
= ring
->dev
;
325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
329 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->ring
);
330 rq1
->elsp_submitted
++;
335 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->ring
);
336 rq0
->elsp_submitted
++;
338 /* You must always write both descriptors in the order below. */
339 spin_lock(&dev_priv
->uncore
.lock
);
340 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
341 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[1]));
342 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[1]));
344 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[0]));
345 /* The context is automatically loaded after the following */
346 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[0]));
348 /* ELSP is a wo register, use another nearby reg for posting */
349 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
350 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
351 spin_unlock(&dev_priv
->uncore
.lock
);
354 static int execlists_update_context(struct drm_i915_gem_request
*rq
)
356 struct intel_engine_cs
*ring
= rq
->ring
;
357 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
358 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
359 struct drm_i915_gem_object
*rb_obj
= rq
->ringbuf
->obj
;
364 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj
));
365 WARN_ON(!i915_gem_obj_is_pinned(rb_obj
));
367 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
368 reg_state
= kmap_atomic(page
);
370 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
371 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(rb_obj
);
373 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
374 /* True 32b PPGTT with dynamic page allocation: update PDP
375 * registers and point the unallocated PDPs to scratch page.
376 * PML4 is allocated during ppgtt init, so this is not needed
379 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
380 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
381 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
382 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
385 kunmap_atomic(reg_state
);
390 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
391 struct drm_i915_gem_request
*rq1
)
393 execlists_update_context(rq0
);
396 execlists_update_context(rq1
);
398 execlists_elsp_write(rq0
, rq1
);
401 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
403 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
404 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
406 assert_spin_locked(&ring
->execlist_lock
);
409 * If irqs are not active generate a warning as batches that finish
410 * without the irqs may get lost and a GPU Hang may occur.
412 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
414 if (list_empty(&ring
->execlist_queue
))
417 /* Try to read in pairs */
418 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
422 } else if (req0
->ctx
== cursor
->ctx
) {
423 /* Same ctx: ignore first request, as second request
424 * will update tail past first request's workload */
425 cursor
->elsp_submitted
= req0
->elsp_submitted
;
426 list_del(&req0
->execlist_link
);
427 list_add_tail(&req0
->execlist_link
,
428 &ring
->execlist_retired_req_list
);
436 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
438 * WaIdleLiteRestore: make sure we never cause a lite
439 * restore with HEAD==TAIL
441 if (req0
->elsp_submitted
) {
443 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
444 * as we resubmit the request. See gen8_emit_request()
445 * for where we prepare the padding after the end of the
448 struct intel_ringbuffer
*ringbuf
;
450 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
452 req0
->tail
&= ringbuf
->size
- 1;
456 WARN_ON(req1
&& req1
->elsp_submitted
);
458 execlists_submit_requests(req0
, req1
);
461 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
464 struct drm_i915_gem_request
*head_req
;
466 assert_spin_locked(&ring
->execlist_lock
);
468 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
469 struct drm_i915_gem_request
,
472 if (head_req
!= NULL
) {
473 struct drm_i915_gem_object
*ctx_obj
=
474 head_req
->ctx
->engine
[ring
->id
].state
;
475 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
476 WARN(head_req
->elsp_submitted
== 0,
477 "Never submitted head request\n");
479 if (--head_req
->elsp_submitted
<= 0) {
480 list_del(&head_req
->execlist_link
);
481 list_add_tail(&head_req
->execlist_link
,
482 &ring
->execlist_retired_req_list
);
492 * intel_lrc_irq_handler() - handle Context Switch interrupts
493 * @ring: Engine Command Streamer to handle.
495 * Check the unread Context Status Buffers and manage the submission of new
496 * contexts to the ELSP accordingly.
498 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
500 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
506 u32 submit_contexts
= 0;
508 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
510 read_pointer
= ring
->next_context_status_buffer
;
511 write_pointer
= status_pointer
& 0x07;
512 if (read_pointer
> write_pointer
)
515 spin_lock(&ring
->execlist_lock
);
517 while (read_pointer
< write_pointer
) {
519 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
520 (read_pointer
% 6) * 8);
521 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
522 (read_pointer
% 6) * 8 + 4);
524 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
527 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
528 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
529 if (execlists_check_remove_request(ring
, status_id
))
530 WARN(1, "Lite Restored request removed from queue\n");
532 WARN(1, "Preemption without Lite Restore\n");
535 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
536 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
537 if (execlists_check_remove_request(ring
, status_id
))
542 if (disable_lite_restore_wa(ring
)) {
543 /* Prevent a ctx to preempt itself */
544 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) &&
545 (submit_contexts
!= 0))
546 execlists_context_unqueue(ring
);
547 } else if (submit_contexts
!= 0) {
548 execlists_context_unqueue(ring
);
551 spin_unlock(&ring
->execlist_lock
);
553 WARN(submit_contexts
> 2, "More than two context complete events?\n");
554 ring
->next_context_status_buffer
= write_pointer
% 6;
556 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
557 _MASKED_FIELD(0x07 << 8, ((u32
)ring
->next_context_status_buffer
& 0x07) << 8));
560 static int execlists_context_queue(struct drm_i915_gem_request
*request
)
562 struct intel_engine_cs
*ring
= request
->ring
;
563 struct drm_i915_gem_request
*cursor
;
564 int num_elements
= 0;
566 if (request
->ctx
!= ring
->default_context
)
567 intel_lr_context_pin(request
);
569 i915_gem_request_reference(request
);
571 spin_lock_irq(&ring
->execlist_lock
);
573 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
574 if (++num_elements
> 2)
577 if (num_elements
> 2) {
578 struct drm_i915_gem_request
*tail_req
;
580 tail_req
= list_last_entry(&ring
->execlist_queue
,
581 struct drm_i915_gem_request
,
584 if (request
->ctx
== tail_req
->ctx
) {
585 WARN(tail_req
->elsp_submitted
!= 0,
586 "More than 2 already-submitted reqs queued\n");
587 list_del(&tail_req
->execlist_link
);
588 list_add_tail(&tail_req
->execlist_link
,
589 &ring
->execlist_retired_req_list
);
593 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
594 if (num_elements
== 0)
595 execlists_context_unqueue(ring
);
597 spin_unlock_irq(&ring
->execlist_lock
);
602 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
604 struct intel_engine_cs
*ring
= req
->ring
;
605 uint32_t flush_domains
;
609 if (ring
->gpu_caches_dirty
)
610 flush_domains
= I915_GEM_GPU_DOMAINS
;
612 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
616 ring
->gpu_caches_dirty
= false;
620 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
621 struct list_head
*vmas
)
623 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
624 struct i915_vma
*vma
;
625 uint32_t flush_domains
= 0;
626 bool flush_chipset
= false;
629 list_for_each_entry(vma
, vmas
, exec_list
) {
630 struct drm_i915_gem_object
*obj
= vma
->obj
;
632 if (obj
->active
& other_rings
) {
633 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
638 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
639 flush_chipset
|= i915_gem_clflush_object(obj
, false);
641 flush_domains
|= obj
->base
.write_domain
;
644 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
647 /* Unconditionally invalidate gpu caches and ensure that we do flush
648 * any residual writes from the previous batch.
650 return logical_ring_invalidate_all_caches(req
);
653 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
657 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
659 if (request
->ctx
!= request
->ring
->default_context
) {
660 ret
= intel_lr_context_pin(request
);
668 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
671 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
672 struct intel_engine_cs
*ring
= req
->ring
;
673 struct drm_i915_gem_request
*target
;
677 if (intel_ring_space(ringbuf
) >= bytes
)
680 /* The whole point of reserving space is to not wait! */
681 WARN_ON(ringbuf
->reserved_in_use
);
683 list_for_each_entry(target
, &ring
->request_list
, list
) {
685 * The request queue is per-engine, so can contain requests
686 * from multiple ringbuffers. Here, we must ignore any that
687 * aren't from the ringbuffer we're considering.
689 if (target
->ringbuf
!= ringbuf
)
692 /* Would completion of this request free enough space? */
693 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
699 if (WARN_ON(&target
->list
== &ring
->request_list
))
702 ret
= i915_wait_request(target
);
706 ringbuf
->space
= space
;
711 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
712 * @request: Request to advance the logical ringbuffer of.
714 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
715 * really happens during submission is that the context and current tail will be placed
716 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
717 * point, the tail *inside* the context is updated and the ELSP written to.
720 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
722 struct intel_engine_cs
*ring
= request
->ring
;
723 struct drm_i915_private
*dev_priv
= request
->i915
;
725 intel_logical_ring_advance(request
->ringbuf
);
727 request
->tail
= request
->ringbuf
->tail
;
729 if (intel_ring_stopped(ring
))
732 if (dev_priv
->guc
.execbuf_client
)
733 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
735 execlists_context_queue(request
);
738 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
740 uint32_t __iomem
*virt
;
741 int rem
= ringbuf
->size
- ringbuf
->tail
;
743 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
746 iowrite32(MI_NOOP
, virt
++);
749 intel_ring_update_space(ringbuf
);
752 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
754 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
755 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
756 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
757 int ret
, total_bytes
, wait_bytes
= 0;
758 bool need_wrap
= false;
760 if (ringbuf
->reserved_in_use
)
763 total_bytes
= bytes
+ ringbuf
->reserved_size
;
765 if (unlikely(bytes
> remain_usable
)) {
767 * Not enough space for the basic request. So need to flush
768 * out the remainder and then wait for base + reserved.
770 wait_bytes
= remain_actual
+ total_bytes
;
773 if (unlikely(total_bytes
> remain_usable
)) {
775 * The base request will fit but the reserved space
776 * falls off the end. So only need to to wait for the
777 * reserved size after flushing out the remainder.
779 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
781 } else if (total_bytes
> ringbuf
->space
) {
782 /* No wrapping required, just waiting. */
783 wait_bytes
= total_bytes
;
788 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
793 __wrap_ring_buffer(ringbuf
);
800 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
802 * @request: The request to start some new work for
803 * @ctx: Logical ring context whose ringbuffer is being prepared.
804 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
806 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
807 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
808 * and also preallocates a request (every workload submission is still mediated through
809 * requests, same as it did with legacy ringbuffer submission).
811 * Return: non-zero if the ringbuffer is not ready to be written to.
813 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
815 struct drm_i915_private
*dev_priv
;
818 WARN_ON(req
== NULL
);
819 dev_priv
= req
->ring
->dev
->dev_private
;
821 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
822 dev_priv
->mm
.interruptible
);
826 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
830 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
834 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
837 * The first call merely notes the reserve request and is common for
838 * all back ends. The subsequent localised _begin() call actually
839 * ensures that the reservation is available. Without the begin, if
840 * the request creator immediately submitted the request without
841 * adding any commands to it then there might not actually be
842 * sufficient room for the submission commands.
844 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
846 return intel_logical_ring_begin(request
, 0);
850 * execlists_submission() - submit a batchbuffer for execution, Execlists style
853 * @ring: Engine Command Streamer to submit to.
854 * @ctx: Context to employ for this submission.
855 * @args: execbuffer call arguments.
856 * @vmas: list of vmas.
857 * @batch_obj: the batchbuffer to submit.
858 * @exec_start: batchbuffer start virtual address pointer.
859 * @dispatch_flags: translated execbuffer call flags.
861 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
862 * away the submission details of the execbuffer ioctl call.
864 * Return: non-zero if the submission fails.
866 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
867 struct drm_i915_gem_execbuffer2
*args
,
868 struct list_head
*vmas
)
870 struct drm_device
*dev
= params
->dev
;
871 struct intel_engine_cs
*ring
= params
->ring
;
872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
873 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
879 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
880 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
881 switch (instp_mode
) {
882 case I915_EXEC_CONSTANTS_REL_GENERAL
:
883 case I915_EXEC_CONSTANTS_ABSOLUTE
:
884 case I915_EXEC_CONSTANTS_REL_SURFACE
:
885 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
886 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
890 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
891 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
892 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
896 /* The HW changed the meaning on this bit on gen6 */
897 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
901 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
905 if (args
->num_cliprects
!= 0) {
906 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
909 if (args
->DR4
== 0xffffffff) {
910 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
914 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
915 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
920 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
921 DRM_DEBUG("sol reset is gen7 only\n");
925 ret
= execlists_move_to_gpu(params
->request
, vmas
);
929 if (ring
== &dev_priv
->ring
[RCS
] &&
930 instp_mode
!= dev_priv
->relative_constants_mode
) {
931 ret
= intel_logical_ring_begin(params
->request
, 4);
935 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
936 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
937 intel_logical_ring_emit(ringbuf
, INSTPM
);
938 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
939 intel_logical_ring_advance(ringbuf
);
941 dev_priv
->relative_constants_mode
= instp_mode
;
944 exec_start
= params
->batch_obj_vm_offset
+
945 args
->batch_start_offset
;
947 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
951 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
953 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
954 i915_gem_execbuffer_retire_commands(params
);
959 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
961 struct drm_i915_gem_request
*req
, *tmp
;
962 struct list_head retired_list
;
964 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
965 if (list_empty(&ring
->execlist_retired_req_list
))
968 INIT_LIST_HEAD(&retired_list
);
969 spin_lock_irq(&ring
->execlist_lock
);
970 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
971 spin_unlock_irq(&ring
->execlist_lock
);
973 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
974 struct intel_context
*ctx
= req
->ctx
;
975 struct drm_i915_gem_object
*ctx_obj
=
976 ctx
->engine
[ring
->id
].state
;
978 if (ctx_obj
&& (ctx
!= ring
->default_context
))
979 intel_lr_context_unpin(req
);
980 list_del(&req
->execlist_link
);
981 i915_gem_request_unreference(req
);
985 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
987 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
990 if (!intel_ring_initialized(ring
))
993 ret
= intel_ring_idle(ring
);
994 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
995 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
998 /* TODO: Is this correct with Execlists enabled? */
999 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
1000 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
1001 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
1004 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
1007 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
1009 struct intel_engine_cs
*ring
= req
->ring
;
1012 if (!ring
->gpu_caches_dirty
)
1015 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
1019 ring
->gpu_caches_dirty
= false;
1023 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
)
1025 struct drm_i915_private
*dev_priv
= rq
->i915
;
1026 struct intel_engine_cs
*ring
= rq
->ring
;
1027 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1028 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1031 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1032 if (rq
->ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1033 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
1034 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
1036 goto reset_pin_count
;
1038 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1042 ctx_obj
->dirty
= true;
1044 /* Invalidate GuC TLB. */
1045 if (i915
.enable_guc_submission
)
1046 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1052 i915_gem_object_ggtt_unpin(ctx_obj
);
1054 rq
->ctx
->engine
[ring
->id
].pin_count
= 0;
1059 void intel_lr_context_unpin(struct drm_i915_gem_request
*rq
)
1061 struct intel_engine_cs
*ring
= rq
->ring
;
1062 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1063 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1066 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1067 if (--rq
->ctx
->engine
[ring
->id
].pin_count
== 0) {
1068 intel_unpin_ringbuffer_obj(ringbuf
);
1069 i915_gem_object_ggtt_unpin(ctx_obj
);
1074 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1077 struct intel_engine_cs
*ring
= req
->ring
;
1078 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1079 struct drm_device
*dev
= ring
->dev
;
1080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1081 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1083 if (WARN_ON_ONCE(w
->count
== 0))
1086 ring
->gpu_caches_dirty
= true;
1087 ret
= logical_ring_flush_all_caches(req
);
1091 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1095 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1096 for (i
= 0; i
< w
->count
; i
++) {
1097 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1098 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1100 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1102 intel_logical_ring_advance(ringbuf
);
1104 ring
->gpu_caches_dirty
= true;
1105 ret
= logical_ring_flush_all_caches(req
);
1112 #define wa_ctx_emit(batch, index, cmd) \
1114 int __index = (index)++; \
1115 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1118 batch[__index] = (cmd); \
1123 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1124 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1125 * but there is a slight complication as this is applied in WA batch where the
1126 * values are only initialized once so we cannot take register value at the
1127 * beginning and reuse it further; hence we save its value to memory, upload a
1128 * constant value with bit21 set and then we restore it back with the saved value.
1129 * To simplify the WA, a constant value is formed by using the default value
1130 * of this register. This shouldn't be a problem because we are only modifying
1131 * it for a short period and this batch in non-premptible. We can ofcourse
1132 * use additional instructions that read the actual value of the register
1133 * at that time and set our bit of interest but it makes the WA complicated.
1135 * This WA is also required for Gen9 so extracting as a function avoids
1138 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*ring
,
1139 uint32_t *const batch
,
1142 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1145 * WaDisableLSQCROPERFforOCL:skl
1146 * This WA is implemented in skl_init_clock_gating() but since
1147 * this batch updates GEN8_L3SQCREG4 with default value we need to
1148 * set this bit here to retain the WA during flush.
1150 if (IS_SKYLAKE(ring
->dev
) && INTEL_REVID(ring
->dev
) <= SKL_REVID_E0
)
1151 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1153 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1154 MI_SRM_LRM_GLOBAL_GTT
));
1155 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1156 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1157 wa_ctx_emit(batch
, index
, 0);
1159 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1160 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1161 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1163 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1164 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1165 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1166 wa_ctx_emit(batch
, index
, 0);
1167 wa_ctx_emit(batch
, index
, 0);
1168 wa_ctx_emit(batch
, index
, 0);
1169 wa_ctx_emit(batch
, index
, 0);
1171 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1172 MI_SRM_LRM_GLOBAL_GTT
));
1173 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1174 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1175 wa_ctx_emit(batch
, index
, 0);
1180 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1182 uint32_t start_alignment
)
1184 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1187 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1189 uint32_t size_alignment
)
1191 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1193 WARN(wa_ctx
->size
% size_alignment
,
1194 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1195 wa_ctx
->size
, size_alignment
);
1200 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1202 * @ring: only applicable for RCS
1203 * @wa_ctx: structure representing wa_ctx
1204 * offset: specifies start of the batch, should be cache-aligned. This is updated
1205 * with the offset value received as input.
1206 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1207 * @batch: page in which WA are loaded
1208 * @offset: This field specifies the start of the batch, it should be
1209 * cache-aligned otherwise it is adjusted accordingly.
1210 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1211 * initialized at the beginning and shared across all contexts but this field
1212 * helps us to have multiple batches at different offsets and select them based
1213 * on a criteria. At the moment this batch always start at the beginning of the page
1214 * and at this point we don't have multiple wa_ctx batch buffers.
1216 * The number of WA applied are not known at the beginning; we use this field
1217 * to return the no of DWORDS written.
1219 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1220 * so it adds NOOPs as padding to make it cacheline aligned.
1221 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1222 * makes a complete batch buffer.
1224 * Return: non-zero if we exceed the PAGE_SIZE limit.
1227 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1228 struct i915_wa_ctx_bb
*wa_ctx
,
1229 uint32_t *const batch
,
1232 uint32_t scratch_addr
;
1233 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1235 /* WaDisableCtxRestoreArbitration:bdw,chv */
1236 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1238 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1239 if (IS_BROADWELL(ring
->dev
)) {
1240 index
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1245 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1246 /* Actual scratch location is at 128 bytes offset */
1247 scratch_addr
= ring
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1249 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1250 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1251 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1252 PIPE_CONTROL_CS_STALL
|
1253 PIPE_CONTROL_QW_WRITE
));
1254 wa_ctx_emit(batch
, index
, scratch_addr
);
1255 wa_ctx_emit(batch
, index
, 0);
1256 wa_ctx_emit(batch
, index
, 0);
1257 wa_ctx_emit(batch
, index
, 0);
1259 /* Pad to end of cacheline */
1260 while (index
% CACHELINE_DWORDS
)
1261 wa_ctx_emit(batch
, index
, MI_NOOP
);
1264 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1265 * execution depends on the length specified in terms of cache lines
1266 * in the register CTX_RCS_INDIRECT_CTX
1269 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1273 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1275 * @ring: only applicable for RCS
1276 * @wa_ctx: structure representing wa_ctx
1277 * offset: specifies start of the batch, should be cache-aligned.
1278 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1279 * @batch: page in which WA are loaded
1280 * @offset: This field specifies the start of this batch.
1281 * This batch is started immediately after indirect_ctx batch. Since we ensure
1282 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1284 * The number of DWORDS written are returned using this field.
1286 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1287 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1289 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1290 struct i915_wa_ctx_bb
*wa_ctx
,
1291 uint32_t *const batch
,
1294 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1296 /* WaDisableCtxRestoreArbitration:bdw,chv */
1297 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1299 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1301 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1304 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1305 struct i915_wa_ctx_bb
*wa_ctx
,
1306 uint32_t *const batch
,
1310 struct drm_device
*dev
= ring
->dev
;
1311 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1313 /* WaDisableCtxRestoreArbitration:skl,bxt */
1314 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1315 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1316 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1318 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1319 ret
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1324 /* Pad to end of cacheline */
1325 while (index
% CACHELINE_DWORDS
)
1326 wa_ctx_emit(batch
, index
, MI_NOOP
);
1328 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1331 static int gen9_init_perctx_bb(struct intel_engine_cs
*ring
,
1332 struct i915_wa_ctx_bb
*wa_ctx
,
1333 uint32_t *const batch
,
1336 struct drm_device
*dev
= ring
->dev
;
1337 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1339 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1340 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_B0
)) ||
1341 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
))) {
1342 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1343 wa_ctx_emit(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1344 wa_ctx_emit(batch
, index
,
1345 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1346 wa_ctx_emit(batch
, index
, MI_NOOP
);
1349 /* WaDisableCtxRestoreArbitration:skl,bxt */
1350 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1351 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1352 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1354 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1356 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1359 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1363 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1364 if (!ring
->wa_ctx
.obj
) {
1365 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1369 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1371 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1373 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1380 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1382 if (ring
->wa_ctx
.obj
) {
1383 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1384 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1385 ring
->wa_ctx
.obj
= NULL
;
1389 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1395 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1397 WARN_ON(ring
->id
!= RCS
);
1399 /* update this when WA for higher Gen are added */
1400 if (INTEL_INFO(ring
->dev
)->gen
> 9) {
1401 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1402 INTEL_INFO(ring
->dev
)->gen
);
1406 /* some WA perform writes to scratch page, ensure it is valid */
1407 if (ring
->scratch
.obj
== NULL
) {
1408 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1412 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1414 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1418 page
= i915_gem_object_get_page(wa_ctx
->obj
, 0);
1419 batch
= kmap_atomic(page
);
1422 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1423 ret
= gen8_init_indirectctx_bb(ring
,
1424 &wa_ctx
->indirect_ctx
,
1430 ret
= gen8_init_perctx_bb(ring
,
1436 } else if (INTEL_INFO(ring
->dev
)->gen
== 9) {
1437 ret
= gen9_init_indirectctx_bb(ring
,
1438 &wa_ctx
->indirect_ctx
,
1444 ret
= gen9_init_perctx_bb(ring
,
1453 kunmap_atomic(batch
);
1455 lrc_destroy_wa_ctx_obj(ring
);
1460 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1462 struct drm_device
*dev
= ring
->dev
;
1463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1466 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1468 if (ring
->status_page
.obj
) {
1469 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1470 (u32
)ring
->status_page
.gfx_addr
);
1471 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1474 I915_WRITE(RING_MODE_GEN7(ring
),
1475 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1476 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1477 POSTING_READ(RING_MODE_GEN7(ring
));
1478 ring
->next_context_status_buffer
= 0;
1479 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1481 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1486 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1488 struct drm_device
*dev
= ring
->dev
;
1489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1492 ret
= gen8_init_common_ring(ring
);
1496 /* We need to disable the AsyncFlip performance optimisations in order
1497 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1498 * programmed to '1' on all products.
1500 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1502 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1504 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1506 return init_workarounds_ring(ring
);
1509 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1513 ret
= gen8_init_common_ring(ring
);
1517 return init_workarounds_ring(ring
);
1520 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1522 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1523 struct intel_engine_cs
*ring
= req
->ring
;
1524 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1525 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1528 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1532 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1533 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1534 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1536 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_UDW(ring
, i
));
1537 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1538 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_LDW(ring
, i
));
1539 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1542 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1543 intel_logical_ring_advance(ringbuf
);
1548 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1549 u64 offset
, unsigned dispatch_flags
)
1551 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1552 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1555 /* Don't rely in hw updating PDPs, specially in lite-restore.
1556 * Ideally, we should set Force PD Restore in ctx descriptor,
1557 * but we can't. Force Restore would be a second option, but
1558 * it is unsafe in case of lite-restore (because the ctx is
1559 * not idle). PML4 is allocated during ppgtt init so this is
1560 * not needed in 48-bit.*/
1561 if (req
->ctx
->ppgtt
&&
1562 (intel_ring_flag(req
->ring
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1563 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1564 !intel_vgpu_active(req
->i915
->dev
)) {
1565 ret
= intel_logical_ring_emit_pdps(req
);
1570 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(req
->ring
);
1573 ret
= intel_logical_ring_begin(req
, 4);
1577 /* FIXME(BDW): Address space and security selectors. */
1578 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1580 (dispatch_flags
& I915_DISPATCH_RS
?
1581 MI_BATCH_RESOURCE_STREAMER
: 0));
1582 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1583 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1584 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1585 intel_logical_ring_advance(ringbuf
);
1590 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1592 struct drm_device
*dev
= ring
->dev
;
1593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1594 unsigned long flags
;
1596 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1599 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1600 if (ring
->irq_refcount
++ == 0) {
1601 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1602 POSTING_READ(RING_IMR(ring
->mmio_base
));
1604 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1609 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1611 struct drm_device
*dev
= ring
->dev
;
1612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1613 unsigned long flags
;
1615 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1616 if (--ring
->irq_refcount
== 0) {
1617 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1618 POSTING_READ(RING_IMR(ring
->mmio_base
));
1620 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1623 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1624 u32 invalidate_domains
,
1627 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1628 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1629 struct drm_device
*dev
= ring
->dev
;
1630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1634 ret
= intel_logical_ring_begin(request
, 4);
1638 cmd
= MI_FLUSH_DW
+ 1;
1640 /* We always require a command barrier so that subsequent
1641 * commands, such as breadcrumb interrupts, are strictly ordered
1642 * wrt the contents of the write cache being flushed to memory
1643 * (and thus being coherent from the CPU).
1645 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1647 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1648 cmd
|= MI_INVALIDATE_TLB
;
1649 if (ring
== &dev_priv
->ring
[VCS
])
1650 cmd
|= MI_INVALIDATE_BSD
;
1653 intel_logical_ring_emit(ringbuf
, cmd
);
1654 intel_logical_ring_emit(ringbuf
,
1655 I915_GEM_HWS_SCRATCH_ADDR
|
1656 MI_FLUSH_DW_USE_GTT
);
1657 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1658 intel_logical_ring_emit(ringbuf
, 0); /* value */
1659 intel_logical_ring_advance(ringbuf
);
1664 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1665 u32 invalidate_domains
,
1668 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1669 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1670 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1675 flags
|= PIPE_CONTROL_CS_STALL
;
1677 if (flush_domains
) {
1678 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1679 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1682 if (invalidate_domains
) {
1683 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1684 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1685 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1686 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1687 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1688 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1689 flags
|= PIPE_CONTROL_QW_WRITE
;
1690 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1694 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1697 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1698 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1700 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1705 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1706 intel_logical_ring_emit(ringbuf
, 0);
1707 intel_logical_ring_emit(ringbuf
, 0);
1708 intel_logical_ring_emit(ringbuf
, 0);
1709 intel_logical_ring_emit(ringbuf
, 0);
1710 intel_logical_ring_emit(ringbuf
, 0);
1713 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1714 intel_logical_ring_emit(ringbuf
, flags
);
1715 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1716 intel_logical_ring_emit(ringbuf
, 0);
1717 intel_logical_ring_emit(ringbuf
, 0);
1718 intel_logical_ring_emit(ringbuf
, 0);
1719 intel_logical_ring_advance(ringbuf
);
1724 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1726 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1729 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1731 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1734 static u32
bxt_a_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1738 * On BXT A steppings there is a HW coherency issue whereby the
1739 * MI_STORE_DATA_IMM storing the completed request's seqno
1740 * occasionally doesn't invalidate the CPU cache. Work around this by
1741 * clflushing the corresponding cacheline whenever the caller wants
1742 * the coherency to be guaranteed. Note that this cacheline is known
1743 * to be clean at this point, since we only write it in
1744 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1745 * this clflush in practice becomes an invalidate operation.
1748 if (!lazy_coherency
)
1749 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1751 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1754 static void bxt_a_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1756 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1758 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1759 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1762 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1764 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1765 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1770 * Reserve space for 2 NOOPs at the end of each request to be
1771 * used as a workaround for not being allowed to do lite
1772 * restore with HEAD==TAIL (WaIdleLiteRestore).
1774 ret
= intel_logical_ring_begin(request
, 8);
1778 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1779 cmd
|= MI_GLOBAL_GTT
;
1781 intel_logical_ring_emit(ringbuf
, cmd
);
1782 intel_logical_ring_emit(ringbuf
,
1783 (ring
->status_page
.gfx_addr
+
1784 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1785 intel_logical_ring_emit(ringbuf
, 0);
1786 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1787 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1788 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1789 intel_logical_ring_advance_and_submit(request
);
1792 * Here we add two extra NOOPs as padding to avoid
1793 * lite restore of a context with HEAD==TAIL.
1795 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1796 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1797 intel_logical_ring_advance(ringbuf
);
1802 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1804 struct render_state so
;
1807 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1811 if (so
.rodata
== NULL
)
1814 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1815 I915_DISPATCH_SECURE
);
1819 ret
= req
->ring
->emit_bb_start(req
,
1820 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1821 I915_DISPATCH_SECURE
);
1825 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1828 i915_gem_render_state_fini(&so
);
1832 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1836 ret
= intel_logical_ring_workarounds_emit(req
);
1840 ret
= intel_rcs_context_init_mocs(req
);
1842 * Failing to program the MOCS is non-fatal.The system will not
1843 * run at peak performance. So generate an error and carry on.
1846 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1848 return intel_lr_context_render_state_init(req
);
1852 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1854 * @ring: Engine Command Streamer.
1857 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1859 struct drm_i915_private
*dev_priv
;
1861 if (!intel_ring_initialized(ring
))
1864 dev_priv
= ring
->dev
->dev_private
;
1866 intel_logical_ring_stop(ring
);
1867 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1870 ring
->cleanup(ring
);
1872 i915_cmd_parser_fini_ring(ring
);
1873 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1875 if (ring
->status_page
.obj
) {
1876 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1877 ring
->status_page
.obj
= NULL
;
1880 lrc_destroy_wa_ctx_obj(ring
);
1883 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1887 /* Intentionally left blank. */
1888 ring
->buffer
= NULL
;
1891 INIT_LIST_HEAD(&ring
->active_list
);
1892 INIT_LIST_HEAD(&ring
->request_list
);
1893 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1894 init_waitqueue_head(&ring
->irq_queue
);
1896 INIT_LIST_HEAD(&ring
->execlist_queue
);
1897 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1898 spin_lock_init(&ring
->execlist_lock
);
1900 ret
= i915_cmd_parser_init_ring(ring
);
1904 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1909 static int logical_render_ring_init(struct drm_device
*dev
)
1911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1912 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1915 ring
->name
= "render ring";
1917 ring
->mmio_base
= RENDER_RING_BASE
;
1918 ring
->irq_enable_mask
=
1919 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1920 ring
->irq_keep_mask
=
1921 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1922 if (HAS_L3_DPF(dev
))
1923 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1925 if (INTEL_INFO(dev
)->gen
>= 9)
1926 ring
->init_hw
= gen9_init_render_ring
;
1928 ring
->init_hw
= gen8_init_render_ring
;
1929 ring
->init_context
= gen8_init_rcs_context
;
1930 ring
->cleanup
= intel_fini_pipe_control
;
1931 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
1932 ring
->get_seqno
= bxt_a_get_seqno
;
1933 ring
->set_seqno
= bxt_a_set_seqno
;
1935 ring
->get_seqno
= gen8_get_seqno
;
1936 ring
->set_seqno
= gen8_set_seqno
;
1938 ring
->emit_request
= gen8_emit_request
;
1939 ring
->emit_flush
= gen8_emit_flush_render
;
1940 ring
->irq_get
= gen8_logical_ring_get_irq
;
1941 ring
->irq_put
= gen8_logical_ring_put_irq
;
1942 ring
->emit_bb_start
= gen8_emit_bb_start
;
1946 ret
= intel_init_pipe_control(ring
);
1950 ret
= intel_init_workaround_bb(ring
);
1953 * We continue even if we fail to initialize WA batch
1954 * because we only expect rare glitches but nothing
1955 * critical to prevent us from using GPU
1957 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1961 ret
= logical_ring_init(dev
, ring
);
1963 lrc_destroy_wa_ctx_obj(ring
);
1969 static int logical_bsd_ring_init(struct drm_device
*dev
)
1971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1972 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1974 ring
->name
= "bsd ring";
1976 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1977 ring
->irq_enable_mask
=
1978 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1979 ring
->irq_keep_mask
=
1980 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1982 ring
->init_hw
= gen8_init_common_ring
;
1983 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
1984 ring
->get_seqno
= bxt_a_get_seqno
;
1985 ring
->set_seqno
= bxt_a_set_seqno
;
1987 ring
->get_seqno
= gen8_get_seqno
;
1988 ring
->set_seqno
= gen8_set_seqno
;
1990 ring
->emit_request
= gen8_emit_request
;
1991 ring
->emit_flush
= gen8_emit_flush
;
1992 ring
->irq_get
= gen8_logical_ring_get_irq
;
1993 ring
->irq_put
= gen8_logical_ring_put_irq
;
1994 ring
->emit_bb_start
= gen8_emit_bb_start
;
1996 return logical_ring_init(dev
, ring
);
1999 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2002 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2004 ring
->name
= "bds2 ring";
2006 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2007 ring
->irq_enable_mask
=
2008 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2009 ring
->irq_keep_mask
=
2010 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2012 ring
->init_hw
= gen8_init_common_ring
;
2013 ring
->get_seqno
= gen8_get_seqno
;
2014 ring
->set_seqno
= gen8_set_seqno
;
2015 ring
->emit_request
= gen8_emit_request
;
2016 ring
->emit_flush
= gen8_emit_flush
;
2017 ring
->irq_get
= gen8_logical_ring_get_irq
;
2018 ring
->irq_put
= gen8_logical_ring_put_irq
;
2019 ring
->emit_bb_start
= gen8_emit_bb_start
;
2021 return logical_ring_init(dev
, ring
);
2024 static int logical_blt_ring_init(struct drm_device
*dev
)
2026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2027 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2029 ring
->name
= "blitter ring";
2031 ring
->mmio_base
= BLT_RING_BASE
;
2032 ring
->irq_enable_mask
=
2033 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2034 ring
->irq_keep_mask
=
2035 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2037 ring
->init_hw
= gen8_init_common_ring
;
2038 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
2039 ring
->get_seqno
= bxt_a_get_seqno
;
2040 ring
->set_seqno
= bxt_a_set_seqno
;
2042 ring
->get_seqno
= gen8_get_seqno
;
2043 ring
->set_seqno
= gen8_set_seqno
;
2045 ring
->emit_request
= gen8_emit_request
;
2046 ring
->emit_flush
= gen8_emit_flush
;
2047 ring
->irq_get
= gen8_logical_ring_get_irq
;
2048 ring
->irq_put
= gen8_logical_ring_put_irq
;
2049 ring
->emit_bb_start
= gen8_emit_bb_start
;
2051 return logical_ring_init(dev
, ring
);
2054 static int logical_vebox_ring_init(struct drm_device
*dev
)
2056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2057 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2059 ring
->name
= "video enhancement ring";
2061 ring
->mmio_base
= VEBOX_RING_BASE
;
2062 ring
->irq_enable_mask
=
2063 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2064 ring
->irq_keep_mask
=
2065 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2067 ring
->init_hw
= gen8_init_common_ring
;
2068 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
2069 ring
->get_seqno
= bxt_a_get_seqno
;
2070 ring
->set_seqno
= bxt_a_set_seqno
;
2072 ring
->get_seqno
= gen8_get_seqno
;
2073 ring
->set_seqno
= gen8_set_seqno
;
2075 ring
->emit_request
= gen8_emit_request
;
2076 ring
->emit_flush
= gen8_emit_flush
;
2077 ring
->irq_get
= gen8_logical_ring_get_irq
;
2078 ring
->irq_put
= gen8_logical_ring_put_irq
;
2079 ring
->emit_bb_start
= gen8_emit_bb_start
;
2081 return logical_ring_init(dev
, ring
);
2085 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2088 * This function inits the engines for an Execlists submission style (the equivalent in the
2089 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2090 * those engines that are present in the hardware.
2092 * Return: non-zero if the initialization failed.
2094 int intel_logical_rings_init(struct drm_device
*dev
)
2096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2099 ret
= logical_render_ring_init(dev
);
2104 ret
= logical_bsd_ring_init(dev
);
2106 goto cleanup_render_ring
;
2110 ret
= logical_blt_ring_init(dev
);
2112 goto cleanup_bsd_ring
;
2115 if (HAS_VEBOX(dev
)) {
2116 ret
= logical_vebox_ring_init(dev
);
2118 goto cleanup_blt_ring
;
2121 if (HAS_BSD2(dev
)) {
2122 ret
= logical_bsd2_ring_init(dev
);
2124 goto cleanup_vebox_ring
;
2127 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
2129 goto cleanup_bsd2_ring
;
2134 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
2136 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
2138 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
2140 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
2141 cleanup_render_ring
:
2142 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
2148 make_rpcs(struct drm_device
*dev
)
2153 * No explicit RPCS request is needed to ensure full
2154 * slice/subslice/EU enablement prior to Gen9.
2156 if (INTEL_INFO(dev
)->gen
< 9)
2160 * Starting in Gen9, render power gating can leave
2161 * slice/subslice/EU in a partially enabled state. We
2162 * must make an explicit request through RPCS for full
2165 if (INTEL_INFO(dev
)->has_slice_pg
) {
2166 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2167 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2168 GEN8_RPCS_S_CNT_SHIFT
;
2169 rpcs
|= GEN8_RPCS_ENABLE
;
2172 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2173 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2174 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2175 GEN8_RPCS_SS_CNT_SHIFT
;
2176 rpcs
|= GEN8_RPCS_ENABLE
;
2179 if (INTEL_INFO(dev
)->has_eu_pg
) {
2180 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2181 GEN8_RPCS_EU_MIN_SHIFT
;
2182 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2183 GEN8_RPCS_EU_MAX_SHIFT
;
2184 rpcs
|= GEN8_RPCS_ENABLE
;
2191 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2192 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
2194 struct drm_device
*dev
= ring
->dev
;
2195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2196 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2198 uint32_t *reg_state
;
2202 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2204 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2206 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2210 ret
= i915_gem_object_get_pages(ctx_obj
);
2212 DRM_DEBUG_DRIVER("Could not get object pages\n");
2216 i915_gem_object_pin_pages(ctx_obj
);
2218 /* The second page of the context object contains some fields which must
2219 * be set up prior to the first execution. */
2220 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2221 reg_state
= kmap_atomic(page
);
2223 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2224 * commands followed by (reg, value) pairs. The values we are setting here are
2225 * only for the first context restore: on a subsequent save, the GPU will
2226 * recreate this batchbuffer with new values (including all the missing
2227 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2228 if (ring
->id
== RCS
)
2229 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
2231 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
2232 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
2233 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
2234 reg_state
[CTX_CONTEXT_CONTROL
+1] =
2235 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2236 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2237 CTX_CTRL_RS_CTX_ENABLE
);
2238 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
2239 reg_state
[CTX_RING_HEAD
+1] = 0;
2240 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
2241 reg_state
[CTX_RING_TAIL
+1] = 0;
2242 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
2243 /* Ring buffer start address is not known until the buffer is pinned.
2244 * It is written to the context image in execlists_update_context()
2246 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
2247 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
2248 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
2249 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
2250 reg_state
[CTX_BB_HEAD_U
+1] = 0;
2251 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
2252 reg_state
[CTX_BB_HEAD_L
+1] = 0;
2253 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
2254 reg_state
[CTX_BB_STATE
+1] = (1<<5);
2255 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
2256 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
2257 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
2258 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
2259 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
2260 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
2261 if (ring
->id
== RCS
) {
2262 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
2263 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
2264 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
2265 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
2266 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
2267 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
2268 if (ring
->wa_ctx
.obj
) {
2269 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2270 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2272 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2273 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2274 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2276 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2277 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2279 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2280 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2284 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
2285 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
2286 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
2287 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
2288 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
2289 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
2290 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
2291 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
2292 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
2293 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
2294 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
2295 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
2297 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2298 /* 64b PPGTT (48bit canonical)
2299 * PDP0_DESCRIPTOR contains the base address to PML4 and
2300 * other PDP Descriptors are ignored.
2302 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2305 * PDP*_DESCRIPTOR contains the base address of space supported.
2306 * With dynamic page allocation, PDPs may not be allocated at
2307 * this point. Point the unallocated PDPs to the scratch page
2309 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2310 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2311 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2312 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2315 if (ring
->id
== RCS
) {
2316 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2317 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
2318 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
2321 kunmap_atomic(reg_state
);
2324 set_page_dirty(page
);
2325 i915_gem_object_unpin_pages(ctx_obj
);
2331 * intel_lr_context_free() - free the LRC specific bits of a context
2332 * @ctx: the LR context to free.
2334 * The real context freeing is done in i915_gem_context_free: this only
2335 * takes care of the bits that are LRC related: the per-engine backing
2336 * objects and the logical ringbuffer.
2338 void intel_lr_context_free(struct intel_context
*ctx
)
2342 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2343 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2346 struct intel_ringbuffer
*ringbuf
=
2347 ctx
->engine
[i
].ringbuf
;
2348 struct intel_engine_cs
*ring
= ringbuf
->ring
;
2350 if (ctx
== ring
->default_context
) {
2351 intel_unpin_ringbuffer_obj(ringbuf
);
2352 i915_gem_object_ggtt_unpin(ctx_obj
);
2354 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
2355 intel_ringbuffer_free(ringbuf
);
2356 drm_gem_object_unreference(&ctx_obj
->base
);
2361 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
2365 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2369 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2370 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2372 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2378 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2385 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2386 struct drm_i915_gem_object
*default_ctx_obj
)
2388 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2391 /* The HWSP is part of the default context object in LRC mode. */
2392 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
)
2393 + LRC_PPHWSP_PN
* PAGE_SIZE
;
2394 page
= i915_gem_object_get_page(default_ctx_obj
, LRC_PPHWSP_PN
);
2395 ring
->status_page
.page_addr
= kmap(page
);
2396 ring
->status_page
.obj
= default_ctx_obj
;
2398 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2399 (u32
)ring
->status_page
.gfx_addr
);
2400 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2404 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2405 * @ctx: LR context to create.
2406 * @ring: engine to be used with the context.
2408 * This function can be called more than once, with different engines, if we plan
2409 * to use the context with them. The context backing objects and the ringbuffers
2410 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2411 * the creation is a deferred call: it's better to make sure first that we need to use
2412 * a given ring with the context.
2414 * Return: non-zero on error.
2416 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
2417 struct intel_engine_cs
*ring
)
2419 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
2420 struct drm_device
*dev
= ring
->dev
;
2421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2422 struct drm_i915_gem_object
*ctx_obj
;
2423 uint32_t context_size
;
2424 struct intel_ringbuffer
*ringbuf
;
2427 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2428 WARN_ON(ctx
->engine
[ring
->id
].state
);
2430 context_size
= round_up(get_lr_context_size(ring
), 4096);
2432 /* One extra page as the sharing data between driver and GuC */
2433 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2435 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2437 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2441 if (is_global_default_ctx
) {
2442 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
2443 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
2445 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2447 drm_gem_object_unreference(&ctx_obj
->base
);
2451 /* Invalidate GuC TLB. */
2452 if (i915
.enable_guc_submission
)
2453 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
2456 ringbuf
= intel_engine_create_ringbuffer(ring
, 4 * PAGE_SIZE
);
2457 if (IS_ERR(ringbuf
)) {
2458 ret
= PTR_ERR(ringbuf
);
2459 goto error_unpin_ctx
;
2462 if (is_global_default_ctx
) {
2463 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2466 "Failed to pin and map ringbuffer %s: %d\n",
2472 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2474 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2478 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2479 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2481 if (ctx
== ring
->default_context
)
2482 lrc_setup_hardware_status_page(ring
, ctx_obj
);
2483 else if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
2484 if (ring
->init_context
) {
2485 struct drm_i915_gem_request
*req
;
2487 ret
= i915_gem_request_alloc(ring
, ctx
, &req
);
2491 ret
= ring
->init_context(req
);
2493 DRM_ERROR("ring init context: %d\n", ret
);
2494 i915_gem_request_cancel(req
);
2495 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2496 ctx
->engine
[ring
->id
].state
= NULL
;
2500 i915_add_request_no_flush(req
);
2503 ctx
->rcs_initialized
= true;
2509 if (is_global_default_ctx
)
2510 intel_unpin_ringbuffer_obj(ringbuf
);
2512 intel_ringbuffer_free(ringbuf
);
2514 if (is_global_default_ctx
)
2515 i915_gem_object_ggtt_unpin(ctx_obj
);
2516 drm_gem_object_unreference(&ctx_obj
->base
);
2520 void intel_lr_context_reset(struct drm_device
*dev
,
2521 struct intel_context
*ctx
)
2523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2524 struct intel_engine_cs
*ring
;
2527 for_each_ring(ring
, dev_priv
, i
) {
2528 struct drm_i915_gem_object
*ctx_obj
=
2529 ctx
->engine
[ring
->id
].state
;
2530 struct intel_ringbuffer
*ringbuf
=
2531 ctx
->engine
[ring
->id
].ringbuf
;
2532 uint32_t *reg_state
;
2538 if (i915_gem_object_get_pages(ctx_obj
)) {
2539 WARN(1, "Failed get_pages for context obj\n");
2542 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2543 reg_state
= kmap_atomic(page
);
2545 reg_state
[CTX_RING_HEAD
+1] = 0;
2546 reg_state
[CTX_RING_TAIL
+1] = 0;
2548 kunmap_atomic(reg_state
);