2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_ALIGN 4096
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 ADVANCED_CONTEXT
= 0,
198 #define GEN8_CTX_MODE_SHIFT 3
201 FAULT_AND_HALT
, /* Debug only */
203 FAULT_AND_CONTINUE
/* Unsupported */
205 #define GEN8_CTX_ID_SHIFT 32
208 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
210 * @enable_execlists: value of i915.enable_execlists module parameter.
212 * Only certain platforms support Execlists (the prerequisites being
213 * support for Logical Ring Contexts and Aliasing PPGTT or better),
214 * and only when enabled via module parameter.
216 * Return: 1 if Execlists is supported and has to be enabled.
218 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
220 WARN_ON(i915
.enable_ppgtt
== -1);
222 if (enable_execlists
== 0)
225 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
226 i915
.use_mmio_flip
>= 0)
233 * intel_execlists_ctx_id() - get the Execlists Context ID
234 * @ctx_obj: Logical Ring Context backing object.
236 * Do not confuse with ctx->id! Unfortunately we have a name overload
237 * here: the old context ID we pass to userspace as a handler so that
238 * they can refer to a context, and the new context ID we pass to the
239 * ELSP so that the GPU can inform us of the context status via
242 * Return: 20-bits globally unique context ID.
244 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
246 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
248 /* LRCA is required to be 4K aligned so the more significant 20 bits
249 * are globally unique */
253 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object
*ctx_obj
)
256 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
258 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
260 desc
= GEN8_CTX_VALID
;
261 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
262 desc
|= GEN8_CTX_L3LLC_COHERENT
;
263 desc
|= GEN8_CTX_PRIVILEGE
;
265 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
267 /* TODO: WaDisableLiteRestore when we start using semaphore
268 * signalling between Command Streamers */
269 /* desc |= GEN8_CTX_FORCE_RESTORE; */
274 static void execlists_elsp_write(struct intel_engine_cs
*ring
,
275 struct drm_i915_gem_object
*ctx_obj0
,
276 struct drm_i915_gem_object
*ctx_obj1
)
278 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
283 /* XXX: You must always write both descriptors in the order below. */
285 temp
= execlists_ctx_descriptor(ctx_obj1
);
288 desc
[1] = (u32
)(temp
>> 32);
291 temp
= execlists_ctx_descriptor(ctx_obj0
);
292 desc
[3] = (u32
)(temp
>> 32);
295 /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
298 * The other problem is that we can't just call gen6_gt_force_wake_get()
299 * because that function calls intel_runtime_pm_get(), which might sleep.
300 * Instead, we do the runtime_pm_get/put when creating/destroying requests.
302 spin_lock_irqsave(&dev_priv
->uncore
.lock
, flags
);
303 if (dev_priv
->uncore
.forcewake_count
++ == 0)
304 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
305 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, flags
);
307 I915_WRITE(RING_ELSP(ring
), desc
[1]);
308 I915_WRITE(RING_ELSP(ring
), desc
[0]);
309 I915_WRITE(RING_ELSP(ring
), desc
[3]);
310 /* The context is automatically loaded after the following */
311 I915_WRITE(RING_ELSP(ring
), desc
[2]);
313 /* ELSP is a wo register, so use another nearby reg for posting instead */
314 POSTING_READ(RING_EXECLIST_STATUS(ring
));
316 /* Release Force Wakeup (see the big comment above). */
317 spin_lock_irqsave(&dev_priv
->uncore
.lock
, flags
);
318 if (--dev_priv
->uncore
.forcewake_count
== 0)
319 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
320 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, flags
);
323 static int execlists_ctx_write_tail(struct drm_i915_gem_object
*ctx_obj
, u32 tail
)
328 page
= i915_gem_object_get_page(ctx_obj
, 1);
329 reg_state
= kmap_atomic(page
);
331 reg_state
[CTX_RING_TAIL
+1] = tail
;
333 kunmap_atomic(reg_state
);
338 static int execlists_submit_context(struct intel_engine_cs
*ring
,
339 struct intel_context
*to0
, u32 tail0
,
340 struct intel_context
*to1
, u32 tail1
)
342 struct drm_i915_gem_object
*ctx_obj0
;
343 struct drm_i915_gem_object
*ctx_obj1
= NULL
;
345 ctx_obj0
= to0
->engine
[ring
->id
].state
;
347 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0
));
349 execlists_ctx_write_tail(ctx_obj0
, tail0
);
352 ctx_obj1
= to1
->engine
[ring
->id
].state
;
354 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1
));
356 execlists_ctx_write_tail(ctx_obj1
, tail1
);
359 execlists_elsp_write(ring
, ctx_obj0
, ctx_obj1
);
364 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
366 struct intel_ctx_submit_request
*req0
= NULL
, *req1
= NULL
;
367 struct intel_ctx_submit_request
*cursor
= NULL
, *tmp
= NULL
;
368 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
370 assert_spin_locked(&ring
->execlist_lock
);
372 if (list_empty(&ring
->execlist_queue
))
375 /* Try to read in pairs */
376 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
380 } else if (req0
->ctx
== cursor
->ctx
) {
381 /* Same ctx: ignore first request, as second request
382 * will update tail past first request's workload */
383 cursor
->elsp_submitted
= req0
->elsp_submitted
;
384 list_del(&req0
->execlist_link
);
385 queue_work(dev_priv
->wq
, &req0
->work
);
393 WARN_ON(req1
&& req1
->elsp_submitted
);
395 WARN_ON(execlists_submit_context(ring
, req0
->ctx
, req0
->tail
,
396 req1
? req1
->ctx
: NULL
,
397 req1
? req1
->tail
: 0));
399 req0
->elsp_submitted
++;
401 req1
->elsp_submitted
++;
404 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
407 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
408 struct intel_ctx_submit_request
*head_req
;
410 assert_spin_locked(&ring
->execlist_lock
);
412 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
413 struct intel_ctx_submit_request
,
416 if (head_req
!= NULL
) {
417 struct drm_i915_gem_object
*ctx_obj
=
418 head_req
->ctx
->engine
[ring
->id
].state
;
419 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
420 WARN(head_req
->elsp_submitted
== 0,
421 "Never submitted head request\n");
423 if (--head_req
->elsp_submitted
<= 0) {
424 list_del(&head_req
->execlist_link
);
425 queue_work(dev_priv
->wq
, &head_req
->work
);
435 * intel_execlists_handle_ctx_events() - handle Context Switch interrupts
436 * @ring: Engine Command Streamer to handle.
438 * Check the unread Context Status Buffers and manage the submission of new
439 * contexts to the ELSP accordingly.
441 void intel_execlists_handle_ctx_events(struct intel_engine_cs
*ring
)
443 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
449 u32 submit_contexts
= 0;
451 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
453 read_pointer
= ring
->next_context_status_buffer
;
454 write_pointer
= status_pointer
& 0x07;
455 if (read_pointer
> write_pointer
)
458 spin_lock(&ring
->execlist_lock
);
460 while (read_pointer
< write_pointer
) {
462 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
463 (read_pointer
% 6) * 8);
464 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
465 (read_pointer
% 6) * 8 + 4);
467 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
468 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
469 if (execlists_check_remove_request(ring
, status_id
))
470 WARN(1, "Lite Restored request removed from queue\n");
472 WARN(1, "Preemption without Lite Restore\n");
475 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
476 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
477 if (execlists_check_remove_request(ring
, status_id
))
482 if (submit_contexts
!= 0)
483 execlists_context_unqueue(ring
);
485 spin_unlock(&ring
->execlist_lock
);
487 WARN(submit_contexts
> 2, "More than two context complete events?\n");
488 ring
->next_context_status_buffer
= write_pointer
% 6;
490 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
491 ((u32
)ring
->next_context_status_buffer
& 0x07) << 8);
494 static void execlists_free_request_task(struct work_struct
*work
)
496 struct intel_ctx_submit_request
*req
=
497 container_of(work
, struct intel_ctx_submit_request
, work
);
498 struct drm_device
*dev
= req
->ring
->dev
;
499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
501 intel_runtime_pm_put(dev_priv
);
503 mutex_lock(&dev
->struct_mutex
);
504 i915_gem_context_unreference(req
->ctx
);
505 mutex_unlock(&dev
->struct_mutex
);
510 static int execlists_context_queue(struct intel_engine_cs
*ring
,
511 struct intel_context
*to
,
514 struct intel_ctx_submit_request
*req
= NULL
, *cursor
;
515 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
517 int num_elements
= 0;
519 req
= kzalloc(sizeof(*req
), GFP_KERNEL
);
523 i915_gem_context_reference(req
->ctx
);
526 INIT_WORK(&req
->work
, execlists_free_request_task
);
528 intel_runtime_pm_get(dev_priv
);
530 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
532 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
533 if (++num_elements
> 2)
536 if (num_elements
> 2) {
537 struct intel_ctx_submit_request
*tail_req
;
539 tail_req
= list_last_entry(&ring
->execlist_queue
,
540 struct intel_ctx_submit_request
,
543 if (to
== tail_req
->ctx
) {
544 WARN(tail_req
->elsp_submitted
!= 0,
545 "More than 2 already-submitted reqs queued\n");
546 list_del(&tail_req
->execlist_link
);
547 queue_work(dev_priv
->wq
, &tail_req
->work
);
551 list_add_tail(&req
->execlist_link
, &ring
->execlist_queue
);
552 if (num_elements
== 0)
553 execlists_context_unqueue(ring
);
555 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
560 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer
*ringbuf
)
562 struct intel_engine_cs
*ring
= ringbuf
->ring
;
563 uint32_t flush_domains
;
567 if (ring
->gpu_caches_dirty
)
568 flush_domains
= I915_GEM_GPU_DOMAINS
;
570 ret
= ring
->emit_flush(ringbuf
, I915_GEM_GPU_DOMAINS
, flush_domains
);
574 ring
->gpu_caches_dirty
= false;
578 static int execlists_move_to_gpu(struct intel_ringbuffer
*ringbuf
,
579 struct list_head
*vmas
)
581 struct intel_engine_cs
*ring
= ringbuf
->ring
;
582 struct i915_vma
*vma
;
583 uint32_t flush_domains
= 0;
584 bool flush_chipset
= false;
587 list_for_each_entry(vma
, vmas
, exec_list
) {
588 struct drm_i915_gem_object
*obj
= vma
->obj
;
590 ret
= i915_gem_object_sync(obj
, ring
);
594 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
595 flush_chipset
|= i915_gem_clflush_object(obj
, false);
597 flush_domains
|= obj
->base
.write_domain
;
600 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
603 /* Unconditionally invalidate gpu caches and ensure that we do flush
604 * any residual writes from the previous batch.
606 return logical_ring_invalidate_all_caches(ringbuf
);
610 * execlists_submission() - submit a batchbuffer for execution, Execlists style
613 * @ring: Engine Command Streamer to submit to.
614 * @ctx: Context to employ for this submission.
615 * @args: execbuffer call arguments.
616 * @vmas: list of vmas.
617 * @batch_obj: the batchbuffer to submit.
618 * @exec_start: batchbuffer start virtual address pointer.
619 * @flags: translated execbuffer call flags.
621 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
622 * away the submission details of the execbuffer ioctl call.
624 * Return: non-zero if the submission fails.
626 int intel_execlists_submission(struct drm_device
*dev
, struct drm_file
*file
,
627 struct intel_engine_cs
*ring
,
628 struct intel_context
*ctx
,
629 struct drm_i915_gem_execbuffer2
*args
,
630 struct list_head
*vmas
,
631 struct drm_i915_gem_object
*batch_obj
,
632 u64 exec_start
, u32 flags
)
634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
635 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
640 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
641 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
642 switch (instp_mode
) {
643 case I915_EXEC_CONSTANTS_REL_GENERAL
:
644 case I915_EXEC_CONSTANTS_ABSOLUTE
:
645 case I915_EXEC_CONSTANTS_REL_SURFACE
:
646 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
647 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
651 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
652 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
653 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
657 /* The HW changed the meaning on this bit on gen6 */
658 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
662 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
666 if (args
->num_cliprects
!= 0) {
667 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
670 if (args
->DR4
== 0xffffffff) {
671 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
675 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
676 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
681 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
682 DRM_DEBUG("sol reset is gen7 only\n");
686 ret
= execlists_move_to_gpu(ringbuf
, vmas
);
690 if (ring
== &dev_priv
->ring
[RCS
] &&
691 instp_mode
!= dev_priv
->relative_constants_mode
) {
692 ret
= intel_logical_ring_begin(ringbuf
, 4);
696 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
697 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
698 intel_logical_ring_emit(ringbuf
, INSTPM
);
699 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
700 intel_logical_ring_advance(ringbuf
);
702 dev_priv
->relative_constants_mode
= instp_mode
;
705 ret
= ring
->emit_bb_start(ringbuf
, exec_start
, flags
);
709 i915_gem_execbuffer_move_to_active(vmas
, ring
);
710 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
715 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
717 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
720 if (!intel_ring_initialized(ring
))
723 ret
= intel_ring_idle(ring
);
724 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
725 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
728 /* TODO: Is this correct with Execlists enabled? */
729 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
730 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
731 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
734 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
737 int logical_ring_flush_all_caches(struct intel_ringbuffer
*ringbuf
)
739 struct intel_engine_cs
*ring
= ringbuf
->ring
;
742 if (!ring
->gpu_caches_dirty
)
745 ret
= ring
->emit_flush(ringbuf
, 0, I915_GEM_GPU_DOMAINS
);
749 ring
->gpu_caches_dirty
= false;
754 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
755 * @ringbuf: Logical Ringbuffer to advance.
757 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
758 * really happens during submission is that the context and current tail will be placed
759 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
760 * point, the tail *inside* the context is updated and the ELSP written to.
762 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer
*ringbuf
)
764 struct intel_engine_cs
*ring
= ringbuf
->ring
;
765 struct intel_context
*ctx
= ringbuf
->FIXME_lrc_ctx
;
767 intel_logical_ring_advance(ringbuf
);
769 if (intel_ring_stopped(ring
))
772 execlists_context_queue(ring
, ctx
, ringbuf
->tail
);
775 static int logical_ring_alloc_seqno(struct intel_engine_cs
*ring
,
776 struct intel_context
*ctx
)
778 if (ring
->outstanding_lazy_seqno
)
781 if (ring
->preallocated_lazy_request
== NULL
) {
782 struct drm_i915_gem_request
*request
;
784 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
788 /* Hold a reference to the context this request belongs to
789 * (we will need it when the time comes to emit/retire the
793 i915_gem_context_reference(request
->ctx
);
795 ring
->preallocated_lazy_request
= request
;
798 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
801 static int logical_ring_wait_request(struct intel_ringbuffer
*ringbuf
,
804 struct intel_engine_cs
*ring
= ringbuf
->ring
;
805 struct drm_i915_gem_request
*request
;
809 if (ringbuf
->last_retired_head
!= -1) {
810 ringbuf
->head
= ringbuf
->last_retired_head
;
811 ringbuf
->last_retired_head
= -1;
813 ringbuf
->space
= intel_ring_space(ringbuf
);
814 if (ringbuf
->space
>= bytes
)
818 list_for_each_entry(request
, &ring
->request_list
, list
) {
819 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
820 ringbuf
->size
) >= bytes
) {
821 seqno
= request
->seqno
;
829 ret
= i915_wait_seqno(ring
, seqno
);
833 i915_gem_retire_requests_ring(ring
);
834 ringbuf
->head
= ringbuf
->last_retired_head
;
835 ringbuf
->last_retired_head
= -1;
837 ringbuf
->space
= intel_ring_space(ringbuf
);
841 static int logical_ring_wait_for_space(struct intel_ringbuffer
*ringbuf
,
844 struct intel_engine_cs
*ring
= ringbuf
->ring
;
845 struct drm_device
*dev
= ring
->dev
;
846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
850 ret
= logical_ring_wait_request(ringbuf
, bytes
);
854 /* Force the context submission in case we have been skipping it */
855 intel_logical_ring_advance_and_submit(ringbuf
);
857 /* With GEM the hangcheck timer should kick us out of the loop,
858 * leaving it early runs the risk of corrupting GEM state (due
859 * to running on almost untested codepaths). But on resume
860 * timers don't work yet, so prevent a complete hang in that
861 * case by choosing an insanely large timeout. */
862 end
= jiffies
+ 60 * HZ
;
865 ringbuf
->head
= I915_READ_HEAD(ring
);
866 ringbuf
->space
= intel_ring_space(ringbuf
);
867 if (ringbuf
->space
>= bytes
) {
874 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
879 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
880 dev_priv
->mm
.interruptible
);
884 if (time_after(jiffies
, end
)) {
893 static int logical_ring_wrap_buffer(struct intel_ringbuffer
*ringbuf
)
895 uint32_t __iomem
*virt
;
896 int rem
= ringbuf
->size
- ringbuf
->tail
;
898 if (ringbuf
->space
< rem
) {
899 int ret
= logical_ring_wait_for_space(ringbuf
, rem
);
905 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
908 iowrite32(MI_NOOP
, virt
++);
911 ringbuf
->space
= intel_ring_space(ringbuf
);
916 static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf
, int bytes
)
920 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
921 ret
= logical_ring_wrap_buffer(ringbuf
);
926 if (unlikely(ringbuf
->space
< bytes
)) {
927 ret
= logical_ring_wait_for_space(ringbuf
, bytes
);
936 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
938 * @ringbuf: Logical ringbuffer.
939 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
941 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
942 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
943 * and also preallocates a request (every workload submission is still mediated through
944 * requests, same as it did with legacy ringbuffer submission).
946 * Return: non-zero if the ringbuffer is not ready to be written to.
948 int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf
, int num_dwords
)
950 struct intel_engine_cs
*ring
= ringbuf
->ring
;
951 struct drm_device
*dev
= ring
->dev
;
952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
955 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
956 dev_priv
->mm
.interruptible
);
960 ret
= logical_ring_prepare(ringbuf
, num_dwords
* sizeof(uint32_t));
964 /* Preallocate the olr before touching the ring */
965 ret
= logical_ring_alloc_seqno(ring
, ringbuf
->FIXME_lrc_ctx
);
969 ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
973 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
975 struct drm_device
*dev
= ring
->dev
;
976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
978 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
979 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
981 I915_WRITE(RING_MODE_GEN7(ring
),
982 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
983 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
984 POSTING_READ(RING_MODE_GEN7(ring
));
985 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
987 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
992 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
994 struct drm_device
*dev
= ring
->dev
;
995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
998 ret
= gen8_init_common_ring(ring
);
1002 /* We need to disable the AsyncFlip performance optimisations in order
1003 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1004 * programmed to '1' on all products.
1006 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1008 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1010 ret
= intel_init_pipe_control(ring
);
1014 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1019 static int gen8_emit_bb_start(struct intel_ringbuffer
*ringbuf
,
1020 u64 offset
, unsigned flags
)
1022 bool ppgtt
= !(flags
& I915_DISPATCH_SECURE
);
1025 ret
= intel_logical_ring_begin(ringbuf
, 4);
1029 /* FIXME(BDW): Address space and security selectors. */
1030 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
1031 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1032 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1033 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1034 intel_logical_ring_advance(ringbuf
);
1039 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1041 struct drm_device
*dev
= ring
->dev
;
1042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1043 unsigned long flags
;
1045 if (!dev
->irq_enabled
)
1048 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1049 if (ring
->irq_refcount
++ == 0) {
1050 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1051 POSTING_READ(RING_IMR(ring
->mmio_base
));
1053 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1058 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1060 struct drm_device
*dev
= ring
->dev
;
1061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1062 unsigned long flags
;
1064 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1065 if (--ring
->irq_refcount
== 0) {
1066 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1067 POSTING_READ(RING_IMR(ring
->mmio_base
));
1069 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1072 static int gen8_emit_flush(struct intel_ringbuffer
*ringbuf
,
1073 u32 invalidate_domains
,
1076 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1077 struct drm_device
*dev
= ring
->dev
;
1078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1082 ret
= intel_logical_ring_begin(ringbuf
, 4);
1086 cmd
= MI_FLUSH_DW
+ 1;
1088 if (ring
== &dev_priv
->ring
[VCS
]) {
1089 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
1090 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1091 MI_FLUSH_DW_STORE_INDEX
|
1092 MI_FLUSH_DW_OP_STOREDW
;
1094 if (invalidate_domains
& I915_GEM_DOMAIN_RENDER
)
1095 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1096 MI_FLUSH_DW_OP_STOREDW
;
1099 intel_logical_ring_emit(ringbuf
, cmd
);
1100 intel_logical_ring_emit(ringbuf
,
1101 I915_GEM_HWS_SCRATCH_ADDR
|
1102 MI_FLUSH_DW_USE_GTT
);
1103 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1104 intel_logical_ring_emit(ringbuf
, 0); /* value */
1105 intel_logical_ring_advance(ringbuf
);
1110 static int gen8_emit_flush_render(struct intel_ringbuffer
*ringbuf
,
1111 u32 invalidate_domains
,
1114 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1115 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1119 flags
|= PIPE_CONTROL_CS_STALL
;
1121 if (flush_domains
) {
1122 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1123 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1126 if (invalidate_domains
) {
1127 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1128 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1129 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1130 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1131 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1132 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1133 flags
|= PIPE_CONTROL_QW_WRITE
;
1134 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1137 ret
= intel_logical_ring_begin(ringbuf
, 6);
1141 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1142 intel_logical_ring_emit(ringbuf
, flags
);
1143 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1144 intel_logical_ring_emit(ringbuf
, 0);
1145 intel_logical_ring_emit(ringbuf
, 0);
1146 intel_logical_ring_emit(ringbuf
, 0);
1147 intel_logical_ring_advance(ringbuf
);
1152 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1154 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1157 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1159 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1162 static int gen8_emit_request(struct intel_ringbuffer
*ringbuf
)
1164 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1168 ret
= intel_logical_ring_begin(ringbuf
, 6);
1172 cmd
= MI_STORE_DWORD_IMM_GEN8
;
1173 cmd
|= MI_GLOBAL_GTT
;
1175 intel_logical_ring_emit(ringbuf
, cmd
);
1176 intel_logical_ring_emit(ringbuf
,
1177 (ring
->status_page
.gfx_addr
+
1178 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1179 intel_logical_ring_emit(ringbuf
, 0);
1180 intel_logical_ring_emit(ringbuf
, ring
->outstanding_lazy_seqno
);
1181 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1182 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1183 intel_logical_ring_advance_and_submit(ringbuf
);
1189 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1191 * @ring: Engine Command Streamer.
1194 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1196 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1198 if (!intel_ring_initialized(ring
))
1201 intel_logical_ring_stop(ring
);
1202 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1203 ring
->preallocated_lazy_request
= NULL
;
1204 ring
->outstanding_lazy_seqno
= 0;
1207 ring
->cleanup(ring
);
1209 i915_cmd_parser_fini_ring(ring
);
1211 if (ring
->status_page
.obj
) {
1212 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1213 ring
->status_page
.obj
= NULL
;
1217 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1220 struct intel_context
*dctx
= ring
->default_context
;
1221 struct drm_i915_gem_object
*dctx_obj
;
1223 /* Intentionally left blank. */
1224 ring
->buffer
= NULL
;
1227 INIT_LIST_HEAD(&ring
->active_list
);
1228 INIT_LIST_HEAD(&ring
->request_list
);
1229 init_waitqueue_head(&ring
->irq_queue
);
1231 INIT_LIST_HEAD(&ring
->execlist_queue
);
1232 spin_lock_init(&ring
->execlist_lock
);
1233 ring
->next_context_status_buffer
= 0;
1235 ret
= intel_lr_context_deferred_create(dctx
, ring
);
1239 /* The status page is offset 0 from the context object in LRCs. */
1240 dctx_obj
= dctx
->engine
[ring
->id
].state
;
1241 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
);
1242 ring
->status_page
.page_addr
= kmap(sg_page(dctx_obj
->pages
->sgl
));
1243 if (ring
->status_page
.page_addr
== NULL
)
1245 ring
->status_page
.obj
= dctx_obj
;
1247 ret
= i915_cmd_parser_init_ring(ring
);
1252 ret
= ring
->init(ring
);
1260 static int logical_render_ring_init(struct drm_device
*dev
)
1262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1263 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1265 ring
->name
= "render ring";
1267 ring
->mmio_base
= RENDER_RING_BASE
;
1268 ring
->irq_enable_mask
=
1269 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1270 ring
->irq_keep_mask
=
1271 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1272 if (HAS_L3_DPF(dev
))
1273 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1275 ring
->init
= gen8_init_render_ring
;
1276 ring
->cleanup
= intel_fini_pipe_control
;
1277 ring
->get_seqno
= gen8_get_seqno
;
1278 ring
->set_seqno
= gen8_set_seqno
;
1279 ring
->emit_request
= gen8_emit_request
;
1280 ring
->emit_flush
= gen8_emit_flush_render
;
1281 ring
->irq_get
= gen8_logical_ring_get_irq
;
1282 ring
->irq_put
= gen8_logical_ring_put_irq
;
1283 ring
->emit_bb_start
= gen8_emit_bb_start
;
1285 return logical_ring_init(dev
, ring
);
1288 static int logical_bsd_ring_init(struct drm_device
*dev
)
1290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1291 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1293 ring
->name
= "bsd ring";
1295 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1296 ring
->irq_enable_mask
=
1297 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1298 ring
->irq_keep_mask
=
1299 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1301 ring
->init
= gen8_init_common_ring
;
1302 ring
->get_seqno
= gen8_get_seqno
;
1303 ring
->set_seqno
= gen8_set_seqno
;
1304 ring
->emit_request
= gen8_emit_request
;
1305 ring
->emit_flush
= gen8_emit_flush
;
1306 ring
->irq_get
= gen8_logical_ring_get_irq
;
1307 ring
->irq_put
= gen8_logical_ring_put_irq
;
1308 ring
->emit_bb_start
= gen8_emit_bb_start
;
1310 return logical_ring_init(dev
, ring
);
1313 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1316 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1318 ring
->name
= "bds2 ring";
1320 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1321 ring
->irq_enable_mask
=
1322 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1323 ring
->irq_keep_mask
=
1324 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1326 ring
->init
= gen8_init_common_ring
;
1327 ring
->get_seqno
= gen8_get_seqno
;
1328 ring
->set_seqno
= gen8_set_seqno
;
1329 ring
->emit_request
= gen8_emit_request
;
1330 ring
->emit_flush
= gen8_emit_flush
;
1331 ring
->irq_get
= gen8_logical_ring_get_irq
;
1332 ring
->irq_put
= gen8_logical_ring_put_irq
;
1333 ring
->emit_bb_start
= gen8_emit_bb_start
;
1335 return logical_ring_init(dev
, ring
);
1338 static int logical_blt_ring_init(struct drm_device
*dev
)
1340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1341 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1343 ring
->name
= "blitter ring";
1345 ring
->mmio_base
= BLT_RING_BASE
;
1346 ring
->irq_enable_mask
=
1347 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1348 ring
->irq_keep_mask
=
1349 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1351 ring
->init
= gen8_init_common_ring
;
1352 ring
->get_seqno
= gen8_get_seqno
;
1353 ring
->set_seqno
= gen8_set_seqno
;
1354 ring
->emit_request
= gen8_emit_request
;
1355 ring
->emit_flush
= gen8_emit_flush
;
1356 ring
->irq_get
= gen8_logical_ring_get_irq
;
1357 ring
->irq_put
= gen8_logical_ring_put_irq
;
1358 ring
->emit_bb_start
= gen8_emit_bb_start
;
1360 return logical_ring_init(dev
, ring
);
1363 static int logical_vebox_ring_init(struct drm_device
*dev
)
1365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1366 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1368 ring
->name
= "video enhancement ring";
1370 ring
->mmio_base
= VEBOX_RING_BASE
;
1371 ring
->irq_enable_mask
=
1372 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1373 ring
->irq_keep_mask
=
1374 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1376 ring
->init
= gen8_init_common_ring
;
1377 ring
->get_seqno
= gen8_get_seqno
;
1378 ring
->set_seqno
= gen8_set_seqno
;
1379 ring
->emit_request
= gen8_emit_request
;
1380 ring
->emit_flush
= gen8_emit_flush
;
1381 ring
->irq_get
= gen8_logical_ring_get_irq
;
1382 ring
->irq_put
= gen8_logical_ring_put_irq
;
1383 ring
->emit_bb_start
= gen8_emit_bb_start
;
1385 return logical_ring_init(dev
, ring
);
1389 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1392 * This function inits the engines for an Execlists submission style (the equivalent in the
1393 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1394 * those engines that are present in the hardware.
1396 * Return: non-zero if the initialization failed.
1398 int intel_logical_rings_init(struct drm_device
*dev
)
1400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1403 ret
= logical_render_ring_init(dev
);
1408 ret
= logical_bsd_ring_init(dev
);
1410 goto cleanup_render_ring
;
1414 ret
= logical_blt_ring_init(dev
);
1416 goto cleanup_bsd_ring
;
1419 if (HAS_VEBOX(dev
)) {
1420 ret
= logical_vebox_ring_init(dev
);
1422 goto cleanup_blt_ring
;
1425 if (HAS_BSD2(dev
)) {
1426 ret
= logical_bsd2_ring_init(dev
);
1428 goto cleanup_vebox_ring
;
1431 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
1433 goto cleanup_bsd2_ring
;
1438 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
1440 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
1442 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
1444 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
1445 cleanup_render_ring
:
1446 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
1452 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
1453 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
1455 struct drm_i915_gem_object
*ring_obj
= ringbuf
->obj
;
1456 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1458 uint32_t *reg_state
;
1461 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1463 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1467 ret
= i915_gem_object_get_pages(ctx_obj
);
1469 DRM_DEBUG_DRIVER("Could not get object pages\n");
1473 i915_gem_object_pin_pages(ctx_obj
);
1475 /* The second page of the context object contains some fields which must
1476 * be set up prior to the first execution. */
1477 page
= i915_gem_object_get_page(ctx_obj
, 1);
1478 reg_state
= kmap_atomic(page
);
1480 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1481 * commands followed by (reg, value) pairs. The values we are setting here are
1482 * only for the first context restore: on a subsequent save, the GPU will
1483 * recreate this batchbuffer with new values (including all the missing
1484 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1485 if (ring
->id
== RCS
)
1486 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
1488 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
1489 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
1490 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
1491 reg_state
[CTX_CONTEXT_CONTROL
+1] =
1492 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT
);
1493 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
1494 reg_state
[CTX_RING_HEAD
+1] = 0;
1495 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
1496 reg_state
[CTX_RING_TAIL
+1] = 0;
1497 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
1498 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(ring_obj
);
1499 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
1500 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
1501 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
1502 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
1503 reg_state
[CTX_BB_HEAD_U
+1] = 0;
1504 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
1505 reg_state
[CTX_BB_HEAD_L
+1] = 0;
1506 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
1507 reg_state
[CTX_BB_STATE
+1] = (1<<5);
1508 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
1509 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
1510 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
1511 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
1512 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
1513 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
1514 if (ring
->id
== RCS
) {
1515 /* TODO: according to BSpec, the register state context
1516 * for CHV does not have these. OTOH, these registers do
1517 * exist in CHV. I'm waiting for a clarification */
1518 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
1519 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
1520 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
1521 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
1522 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
1523 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
1525 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
1526 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
1527 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
1528 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
1529 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
1530 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
1531 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
1532 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
1533 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
1534 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
1535 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
1536 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
1537 reg_state
[CTX_PDP3_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[3]);
1538 reg_state
[CTX_PDP3_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[3]);
1539 reg_state
[CTX_PDP2_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[2]);
1540 reg_state
[CTX_PDP2_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[2]);
1541 reg_state
[CTX_PDP1_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[1]);
1542 reg_state
[CTX_PDP1_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[1]);
1543 reg_state
[CTX_PDP0_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[0]);
1544 reg_state
[CTX_PDP0_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[0]);
1545 if (ring
->id
== RCS
) {
1546 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
1547 reg_state
[CTX_R_PWR_CLK_STATE
] = 0x20c8;
1548 reg_state
[CTX_R_PWR_CLK_STATE
+1] = 0;
1551 kunmap_atomic(reg_state
);
1554 set_page_dirty(page
);
1555 i915_gem_object_unpin_pages(ctx_obj
);
1561 * intel_lr_context_free() - free the LRC specific bits of a context
1562 * @ctx: the LR context to free.
1564 * The real context freeing is done in i915_gem_context_free: this only
1565 * takes care of the bits that are LRC related: the per-engine backing
1566 * objects and the logical ringbuffer.
1568 void intel_lr_context_free(struct intel_context
*ctx
)
1572 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1573 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
1574 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
1577 intel_destroy_ringbuffer_obj(ringbuf
);
1579 i915_gem_object_ggtt_unpin(ctx_obj
);
1580 drm_gem_object_unreference(&ctx_obj
->base
);
1585 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
1589 WARN_ON(INTEL_INFO(ring
->dev
)->gen
!= 8);
1593 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
1599 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
1607 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1608 * @ctx: LR context to create.
1609 * @ring: engine to be used with the context.
1611 * This function can be called more than once, with different engines, if we plan
1612 * to use the context with them. The context backing objects and the ringbuffers
1613 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1614 * the creation is a deferred call: it's better to make sure first that we need to use
1615 * a given ring with the context.
1617 * Return: non-zero on eror.
1619 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
1620 struct intel_engine_cs
*ring
)
1622 struct drm_device
*dev
= ring
->dev
;
1623 struct drm_i915_gem_object
*ctx_obj
;
1624 uint32_t context_size
;
1625 struct intel_ringbuffer
*ringbuf
;
1628 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
1629 if (ctx
->engine
[ring
->id
].state
)
1632 context_size
= round_up(get_lr_context_size(ring
), 4096);
1634 ctx_obj
= i915_gem_alloc_context_obj(dev
, context_size
);
1635 if (IS_ERR(ctx_obj
)) {
1636 ret
= PTR_ERR(ctx_obj
);
1637 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret
);
1641 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
1643 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret
);
1644 drm_gem_object_unreference(&ctx_obj
->base
);
1648 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1650 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1652 i915_gem_object_ggtt_unpin(ctx_obj
);
1653 drm_gem_object_unreference(&ctx_obj
->base
);
1658 ringbuf
->ring
= ring
;
1659 ringbuf
->FIXME_lrc_ctx
= ctx
;
1661 ringbuf
->size
= 32 * PAGE_SIZE
;
1662 ringbuf
->effective_size
= ringbuf
->size
;
1665 ringbuf
->space
= ringbuf
->size
;
1666 ringbuf
->last_retired_head
= -1;
1668 /* TODO: For now we put this in the mappable region so that we can reuse
1669 * the existing ringbuffer code which ioremaps it. When we start
1670 * creating many contexts, this will no longer work and we must switch
1671 * to a kmapish interface.
1673 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1675 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
1680 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
1682 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
1683 intel_destroy_ringbuffer_obj(ringbuf
);
1687 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
1688 ctx
->engine
[ring
->id
].state
= ctx_obj
;
1694 i915_gem_object_ggtt_unpin(ctx_obj
);
1695 drm_gem_object_unreference(&ctx_obj
->base
);