2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT
= 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT
, /* Debug only */
224 FAULT_AND_CONTINUE
/* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
230 static int intel_lr_context_pin(struct intel_context
*ctx
,
231 struct intel_engine_cs
*engine
);
234 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
236 * @enable_execlists: value of i915.enable_execlists module parameter.
238 * Only certain platforms support Execlists (the prerequisites being
239 * support for Logical Ring Contexts and Aliasing PPGTT or better).
241 * Return: 1 if Execlists is supported and has to be enabled.
243 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
245 WARN_ON(i915
.enable_ppgtt
== -1);
247 /* On platforms with execlist available, vGPU will only
248 * support execlist mode, no ring buffer mode.
250 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
253 if (INTEL_INFO(dev
)->gen
>= 9)
256 if (enable_execlists
== 0)
259 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
260 i915
.use_mmio_flip
>= 0)
267 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
269 struct drm_device
*dev
= engine
->dev
;
271 if (IS_GEN8(dev
) || IS_GEN9(dev
))
272 engine
->idle_lite_restore_wa
= ~0;
274 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
275 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) &&
276 (engine
->id
== VCS
|| engine
->id
== VCS2
);
278 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
279 engine
->ctx_desc_template
|= GEN8_CTX_ADDRESSING_MODE(dev
) <<
280 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
282 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
283 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
285 /* TODO: WaDisableLiteRestore when we start using semaphore
286 * signalling between Command Streamers */
287 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
289 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
290 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
291 if (engine
->disable_lite_restore_wa
)
292 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
296 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
297 * descriptor for a pinned context
299 * @ctx: Context to work on
300 * @ring: Engine the descriptor will be used with
302 * The context descriptor encodes various attributes of a context,
303 * including its GTT address and some flags. Because it's fairly
304 * expensive to calculate, we'll just do it once and cache the result,
305 * which remains valid until the context is unpinned.
307 * This is what a descriptor looks like, from LSB to MSB:
308 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
309 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
310 * bits 32-51: ctx ID, a globally unique tag (the LRCA again!)
311 * bits 52-63: reserved, may encode the engine ID (for GuC)
314 intel_lr_context_descriptor_update(struct intel_context
*ctx
,
315 struct intel_engine_cs
*engine
)
319 lrca
= ctx
->engine
[engine
->id
].lrc_vma
->node
.start
+
320 LRC_PPHWSP_PN
* PAGE_SIZE
;
322 desc
= engine
->ctx_desc_template
; /* bits 0-11 */
323 desc
|= lrca
; /* bits 12-31 */
324 desc
|= (lrca
>> PAGE_SHIFT
) << GEN8_CTX_ID_SHIFT
; /* bits 32-51 */
326 ctx
->engine
[engine
->id
].lrc_desc
= desc
;
329 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
330 struct intel_engine_cs
*engine
)
332 return ctx
->engine
[engine
->id
].lrc_desc
;
336 * intel_execlists_ctx_id() - get the Execlists Context ID
337 * @ctx: Context to get the ID for
338 * @ring: Engine to get the ID for
340 * Do not confuse with ctx->id! Unfortunately we have a name overload
341 * here: the old context ID we pass to userspace as a handler so that
342 * they can refer to a context, and the new context ID we pass to the
343 * ELSP so that the GPU can inform us of the context status via
346 * The context ID is a portion of the context descriptor, so we can
347 * just extract the required part from the cached descriptor.
349 * Return: 20-bits globally unique context ID.
351 u32
intel_execlists_ctx_id(struct intel_context
*ctx
,
352 struct intel_engine_cs
*engine
)
354 return intel_lr_context_descriptor(ctx
, engine
) >> GEN8_CTX_ID_SHIFT
;
357 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
358 struct drm_i915_gem_request
*rq1
)
361 struct intel_engine_cs
*engine
= rq0
->engine
;
362 struct drm_device
*dev
= engine
->dev
;
363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
367 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
368 rq1
->elsp_submitted
++;
373 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
374 rq0
->elsp_submitted
++;
376 /* You must always write both descriptors in the order below. */
377 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
378 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
380 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
381 /* The context is automatically loaded after the following */
382 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
384 /* ELSP is a wo register, use another nearby reg for posting */
385 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
389 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
391 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
392 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
393 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
394 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
397 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
399 struct intel_engine_cs
*engine
= rq
->engine
;
400 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
401 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
403 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
405 /* True 32b PPGTT with dynamic page allocation: update PDP
406 * registers and point the unallocated PDPs to scratch page.
407 * PML4 is allocated during ppgtt init, so this is not needed
410 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
411 execlists_update_context_pdps(ppgtt
, reg_state
);
414 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
415 struct drm_i915_gem_request
*rq1
)
417 struct drm_i915_private
*dev_priv
= rq0
->i915
;
418 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
420 execlists_update_context(rq0
);
423 execlists_update_context(rq1
);
425 spin_lock_irq(&dev_priv
->uncore
.lock
);
426 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
428 execlists_elsp_write(rq0
, rq1
);
430 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
431 spin_unlock_irq(&dev_priv
->uncore
.lock
);
434 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
436 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
437 struct drm_i915_gem_request
*cursor
, *tmp
;
439 assert_spin_locked(&engine
->execlist_lock
);
442 * If irqs are not active generate a warning as batches that finish
443 * without the irqs may get lost and a GPU Hang may occur.
445 WARN_ON(!intel_irqs_enabled(engine
->dev
->dev_private
));
447 /* Try to read in pairs */
448 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
452 } else if (req0
->ctx
== cursor
->ctx
) {
453 /* Same ctx: ignore first request, as second request
454 * will update tail past first request's workload */
455 cursor
->elsp_submitted
= req0
->elsp_submitted
;
456 list_move_tail(&req0
->execlist_link
,
457 &engine
->execlist_retired_req_list
);
461 WARN_ON(req1
->elsp_submitted
);
469 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
471 * WaIdleLiteRestore: make sure we never cause a lite restore
474 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
475 * resubmit the request. See gen8_emit_request() for where we
476 * prepare the padding after the end of the request.
478 struct intel_ringbuffer
*ringbuf
;
480 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
482 req0
->tail
&= ringbuf
->size
- 1;
485 execlists_submit_requests(req0
, req1
);
489 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 request_id
)
491 struct drm_i915_gem_request
*head_req
;
493 assert_spin_locked(&engine
->execlist_lock
);
495 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
496 struct drm_i915_gem_request
,
502 if (unlikely(intel_execlists_ctx_id(head_req
->ctx
, engine
) != request_id
))
505 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
507 if (--head_req
->elsp_submitted
> 0)
510 list_move_tail(&head_req
->execlist_link
,
511 &engine
->execlist_retired_req_list
);
517 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
520 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
523 read_pointer
%= GEN8_CSB_ENTRIES
;
525 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
527 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
530 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
537 * intel_lrc_irq_handler() - handle Context Switch interrupts
538 * @engine: Engine Command Streamer to handle.
540 * Check the unread Context Status Buffers and manage the submission of new
541 * contexts to the ELSP accordingly.
543 static void intel_lrc_irq_handler(unsigned long data
)
545 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
546 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
548 unsigned int read_pointer
, write_pointer
;
549 u32 csb
[GEN8_CSB_ENTRIES
][2];
550 unsigned int csb_read
= 0, i
;
551 unsigned int submit_contexts
= 0;
553 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
555 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
557 read_pointer
= engine
->next_context_status_buffer
;
558 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
559 if (read_pointer
> write_pointer
)
560 write_pointer
+= GEN8_CSB_ENTRIES
;
562 while (read_pointer
< write_pointer
) {
563 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
565 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
570 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
572 /* Update the read pointer to the old write pointer. Manual ringbuffer
573 * management ftw </sarcasm> */
574 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
575 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
576 engine
->next_context_status_buffer
<< 8));
578 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
580 spin_lock(&engine
->execlist_lock
);
582 for (i
= 0; i
< csb_read
; i
++) {
583 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
584 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
585 if (execlists_check_remove_request(engine
, csb
[i
][1]))
586 WARN(1, "Lite Restored request removed from queue\n");
588 WARN(1, "Preemption without Lite Restore\n");
591 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
592 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
594 execlists_check_remove_request(engine
, csb
[i
][1]);
597 if (submit_contexts
) {
598 if (!engine
->disable_lite_restore_wa
||
599 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
600 execlists_context_unqueue(engine
);
603 spin_unlock(&engine
->execlist_lock
);
605 if (unlikely(submit_contexts
> 2))
606 DRM_ERROR("More than two context complete events?\n");
609 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
611 struct intel_engine_cs
*engine
= request
->engine
;
612 struct drm_i915_gem_request
*cursor
;
613 int num_elements
= 0;
615 if (request
->ctx
!= request
->i915
->kernel_context
)
616 intel_lr_context_pin(request
->ctx
, engine
);
618 i915_gem_request_reference(request
);
620 spin_lock_bh(&engine
->execlist_lock
);
622 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
623 if (++num_elements
> 2)
626 if (num_elements
> 2) {
627 struct drm_i915_gem_request
*tail_req
;
629 tail_req
= list_last_entry(&engine
->execlist_queue
,
630 struct drm_i915_gem_request
,
633 if (request
->ctx
== tail_req
->ctx
) {
634 WARN(tail_req
->elsp_submitted
!= 0,
635 "More than 2 already-submitted reqs queued\n");
636 list_move_tail(&tail_req
->execlist_link
,
637 &engine
->execlist_retired_req_list
);
641 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
642 if (num_elements
== 0)
643 execlists_context_unqueue(engine
);
645 spin_unlock_bh(&engine
->execlist_lock
);
648 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
650 struct intel_engine_cs
*engine
= req
->engine
;
651 uint32_t flush_domains
;
655 if (engine
->gpu_caches_dirty
)
656 flush_domains
= I915_GEM_GPU_DOMAINS
;
658 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
662 engine
->gpu_caches_dirty
= false;
666 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
667 struct list_head
*vmas
)
669 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
670 struct i915_vma
*vma
;
671 uint32_t flush_domains
= 0;
672 bool flush_chipset
= false;
675 list_for_each_entry(vma
, vmas
, exec_list
) {
676 struct drm_i915_gem_object
*obj
= vma
->obj
;
678 if (obj
->active
& other_rings
) {
679 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
684 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
685 flush_chipset
|= i915_gem_clflush_object(obj
, false);
687 flush_domains
|= obj
->base
.write_domain
;
690 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
693 /* Unconditionally invalidate gpu caches and ensure that we do flush
694 * any residual writes from the previous batch.
696 return logical_ring_invalidate_all_caches(req
);
699 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
703 request
->ringbuf
= request
->ctx
->engine
[request
->engine
->id
].ringbuf
;
705 if (i915
.enable_guc_submission
) {
707 * Check that the GuC has space for the request before
708 * going any further, as the i915_add_request() call
709 * later on mustn't fail ...
711 struct intel_guc
*guc
= &request
->i915
->guc
;
713 ret
= i915_guc_wq_check_space(guc
->execbuf_client
);
718 if (request
->ctx
!= request
->i915
->kernel_context
)
719 ret
= intel_lr_context_pin(request
->ctx
, request
->engine
);
725 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
726 * @request: Request to advance the logical ringbuffer of.
728 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
729 * really happens during submission is that the context and current tail will be placed
730 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
731 * point, the tail *inside* the context is updated and the ELSP written to.
734 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
736 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
737 struct drm_i915_private
*dev_priv
= request
->i915
;
738 struct intel_engine_cs
*engine
= request
->engine
;
740 intel_logical_ring_advance(ringbuf
);
741 request
->tail
= ringbuf
->tail
;
744 * Here we add two extra NOOPs as padding to avoid
745 * lite restore of a context with HEAD==TAIL.
747 * Caller must reserve WA_TAIL_DWORDS for us!
749 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
750 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
751 intel_logical_ring_advance(ringbuf
);
753 if (intel_engine_stopped(engine
))
756 if (engine
->last_context
!= request
->ctx
) {
757 if (engine
->last_context
)
758 intel_lr_context_unpin(engine
->last_context
, engine
);
759 if (request
->ctx
!= request
->i915
->kernel_context
) {
760 intel_lr_context_pin(request
->ctx
, engine
);
761 engine
->last_context
= request
->ctx
;
763 engine
->last_context
= NULL
;
767 if (dev_priv
->guc
.execbuf_client
)
768 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
770 execlists_context_queue(request
);
775 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
778 * The first call merely notes the reserve request and is common for
779 * all back ends. The subsequent localised _begin() call actually
780 * ensures that the reservation is available. Without the begin, if
781 * the request creator immediately submitted the request without
782 * adding any commands to it then there might not actually be
783 * sufficient room for the submission commands.
785 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
787 return intel_ring_begin(request
, 0);
791 * execlists_submission() - submit a batchbuffer for execution, Execlists style
794 * @ring: Engine Command Streamer to submit to.
795 * @ctx: Context to employ for this submission.
796 * @args: execbuffer call arguments.
797 * @vmas: list of vmas.
798 * @batch_obj: the batchbuffer to submit.
799 * @exec_start: batchbuffer start virtual address pointer.
800 * @dispatch_flags: translated execbuffer call flags.
802 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
803 * away the submission details of the execbuffer ioctl call.
805 * Return: non-zero if the submission fails.
807 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
808 struct drm_i915_gem_execbuffer2
*args
,
809 struct list_head
*vmas
)
811 struct drm_device
*dev
= params
->dev
;
812 struct intel_engine_cs
*engine
= params
->engine
;
813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
814 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
820 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
821 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
822 switch (instp_mode
) {
823 case I915_EXEC_CONSTANTS_REL_GENERAL
:
824 case I915_EXEC_CONSTANTS_ABSOLUTE
:
825 case I915_EXEC_CONSTANTS_REL_SURFACE
:
826 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
827 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
831 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
832 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
833 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
837 /* The HW changed the meaning on this bit on gen6 */
838 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
842 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
846 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
847 DRM_DEBUG("sol reset is gen7 only\n");
851 ret
= execlists_move_to_gpu(params
->request
, vmas
);
855 if (engine
== &dev_priv
->engine
[RCS
] &&
856 instp_mode
!= dev_priv
->relative_constants_mode
) {
857 ret
= intel_ring_begin(params
->request
, 4);
861 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
862 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
863 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
864 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
865 intel_logical_ring_advance(ringbuf
);
867 dev_priv
->relative_constants_mode
= instp_mode
;
870 exec_start
= params
->batch_obj_vm_offset
+
871 args
->batch_start_offset
;
873 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
877 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
879 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
884 void intel_execlists_retire_requests(struct intel_engine_cs
*engine
)
886 struct drm_i915_gem_request
*req
, *tmp
;
887 struct list_head retired_list
;
889 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
890 if (list_empty(&engine
->execlist_retired_req_list
))
893 INIT_LIST_HEAD(&retired_list
);
894 spin_lock_bh(&engine
->execlist_lock
);
895 list_replace_init(&engine
->execlist_retired_req_list
, &retired_list
);
896 spin_unlock_bh(&engine
->execlist_lock
);
898 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
899 struct intel_context
*ctx
= req
->ctx
;
900 struct drm_i915_gem_object
*ctx_obj
=
901 ctx
->engine
[engine
->id
].state
;
903 if (ctx_obj
&& (ctx
!= req
->i915
->kernel_context
))
904 intel_lr_context_unpin(ctx
, engine
);
906 list_del(&req
->execlist_link
);
907 i915_gem_request_unreference(req
);
911 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
913 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
916 if (!intel_engine_initialized(engine
))
919 ret
= intel_engine_idle(engine
);
921 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
924 /* TODO: Is this correct with Execlists enabled? */
925 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
926 if (wait_for((I915_READ_MODE(engine
) & MODE_IDLE
) != 0, 1000)) {
927 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
930 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
933 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
935 struct intel_engine_cs
*engine
= req
->engine
;
938 if (!engine
->gpu_caches_dirty
)
941 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
945 engine
->gpu_caches_dirty
= false;
949 static int intel_lr_context_do_pin(struct intel_context
*ctx
,
950 struct intel_engine_cs
*engine
)
952 struct drm_device
*dev
= engine
->dev
;
953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
954 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
955 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[engine
->id
].ringbuf
;
960 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
962 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
963 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
967 vaddr
= i915_gem_object_pin_map(ctx_obj
);
969 ret
= PTR_ERR(vaddr
);
973 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
975 ret
= intel_pin_and_map_ringbuffer_obj(engine
->dev
, ringbuf
);
979 ctx
->engine
[engine
->id
].lrc_vma
= i915_gem_obj_to_ggtt(ctx_obj
);
980 intel_lr_context_descriptor_update(ctx
, engine
);
981 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ringbuf
->vma
->node
.start
;
982 ctx
->engine
[engine
->id
].lrc_reg_state
= lrc_reg_state
;
983 ctx_obj
->dirty
= true;
985 /* Invalidate GuC TLB. */
986 if (i915
.enable_guc_submission
)
987 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
992 i915_gem_object_unpin_map(ctx_obj
);
994 i915_gem_object_ggtt_unpin(ctx_obj
);
999 static int intel_lr_context_pin(struct intel_context
*ctx
,
1000 struct intel_engine_cs
*engine
)
1004 if (ctx
->engine
[engine
->id
].pin_count
++ == 0) {
1005 ret
= intel_lr_context_do_pin(ctx
, engine
);
1007 goto reset_pin_count
;
1009 i915_gem_context_reference(ctx
);
1014 ctx
->engine
[engine
->id
].pin_count
= 0;
1018 void intel_lr_context_unpin(struct intel_context
*ctx
,
1019 struct intel_engine_cs
*engine
)
1021 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
1023 WARN_ON(!mutex_is_locked(&ctx
->i915
->dev
->struct_mutex
));
1024 if (--ctx
->engine
[engine
->id
].pin_count
== 0) {
1025 i915_gem_object_unpin_map(ctx_obj
);
1026 intel_unpin_ringbuffer_obj(ctx
->engine
[engine
->id
].ringbuf
);
1027 i915_gem_object_ggtt_unpin(ctx_obj
);
1028 ctx
->engine
[engine
->id
].lrc_vma
= NULL
;
1029 ctx
->engine
[engine
->id
].lrc_desc
= 0;
1030 ctx
->engine
[engine
->id
].lrc_reg_state
= NULL
;
1032 i915_gem_context_unreference(ctx
);
1036 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1039 struct intel_engine_cs
*engine
= req
->engine
;
1040 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1041 struct drm_device
*dev
= engine
->dev
;
1042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1043 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1048 engine
->gpu_caches_dirty
= true;
1049 ret
= logical_ring_flush_all_caches(req
);
1053 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
1057 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1058 for (i
= 0; i
< w
->count
; i
++) {
1059 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1060 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1062 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1064 intel_logical_ring_advance(ringbuf
);
1066 engine
->gpu_caches_dirty
= true;
1067 ret
= logical_ring_flush_all_caches(req
);
1074 #define wa_ctx_emit(batch, index, cmd) \
1076 int __index = (index)++; \
1077 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1080 batch[__index] = (cmd); \
1083 #define wa_ctx_emit_reg(batch, index, reg) \
1084 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1087 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1088 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1089 * but there is a slight complication as this is applied in WA batch where the
1090 * values are only initialized once so we cannot take register value at the
1091 * beginning and reuse it further; hence we save its value to memory, upload a
1092 * constant value with bit21 set and then we restore it back with the saved value.
1093 * To simplify the WA, a constant value is formed by using the default value
1094 * of this register. This shouldn't be a problem because we are only modifying
1095 * it for a short period and this batch in non-premptible. We can ofcourse
1096 * use additional instructions that read the actual value of the register
1097 * at that time and set our bit of interest but it makes the WA complicated.
1099 * This WA is also required for Gen9 so extracting as a function avoids
1102 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1103 uint32_t *const batch
,
1106 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1109 * WaDisableLSQCROPERFforOCL:skl
1110 * This WA is implemented in skl_init_clock_gating() but since
1111 * this batch updates GEN8_L3SQCREG4 with default value we need to
1112 * set this bit here to retain the WA during flush.
1114 if (IS_SKL_REVID(engine
->dev
, 0, SKL_REVID_E0
))
1115 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1117 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1118 MI_SRM_LRM_GLOBAL_GTT
));
1119 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1120 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1121 wa_ctx_emit(batch
, index
, 0);
1123 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1124 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1125 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1127 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1128 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1129 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1130 wa_ctx_emit(batch
, index
, 0);
1131 wa_ctx_emit(batch
, index
, 0);
1132 wa_ctx_emit(batch
, index
, 0);
1133 wa_ctx_emit(batch
, index
, 0);
1135 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1136 MI_SRM_LRM_GLOBAL_GTT
));
1137 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1138 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1139 wa_ctx_emit(batch
, index
, 0);
1144 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1146 uint32_t start_alignment
)
1148 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1151 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1153 uint32_t size_alignment
)
1155 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1157 WARN(wa_ctx
->size
% size_alignment
,
1158 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1159 wa_ctx
->size
, size_alignment
);
1164 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1166 * @ring: only applicable for RCS
1167 * @wa_ctx: structure representing wa_ctx
1168 * offset: specifies start of the batch, should be cache-aligned. This is updated
1169 * with the offset value received as input.
1170 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1171 * @batch: page in which WA are loaded
1172 * @offset: This field specifies the start of the batch, it should be
1173 * cache-aligned otherwise it is adjusted accordingly.
1174 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1175 * initialized at the beginning and shared across all contexts but this field
1176 * helps us to have multiple batches at different offsets and select them based
1177 * on a criteria. At the moment this batch always start at the beginning of the page
1178 * and at this point we don't have multiple wa_ctx batch buffers.
1180 * The number of WA applied are not known at the beginning; we use this field
1181 * to return the no of DWORDS written.
1183 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1184 * so it adds NOOPs as padding to make it cacheline aligned.
1185 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1186 * makes a complete batch buffer.
1188 * Return: non-zero if we exceed the PAGE_SIZE limit.
1191 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1192 struct i915_wa_ctx_bb
*wa_ctx
,
1193 uint32_t *const batch
,
1196 uint32_t scratch_addr
;
1197 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1199 /* WaDisableCtxRestoreArbitration:bdw,chv */
1200 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1202 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1203 if (IS_BROADWELL(engine
->dev
)) {
1204 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1210 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1211 /* Actual scratch location is at 128 bytes offset */
1212 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1214 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1215 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1216 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1217 PIPE_CONTROL_CS_STALL
|
1218 PIPE_CONTROL_QW_WRITE
));
1219 wa_ctx_emit(batch
, index
, scratch_addr
);
1220 wa_ctx_emit(batch
, index
, 0);
1221 wa_ctx_emit(batch
, index
, 0);
1222 wa_ctx_emit(batch
, index
, 0);
1224 /* Pad to end of cacheline */
1225 while (index
% CACHELINE_DWORDS
)
1226 wa_ctx_emit(batch
, index
, MI_NOOP
);
1229 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1230 * execution depends on the length specified in terms of cache lines
1231 * in the register CTX_RCS_INDIRECT_CTX
1234 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1238 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1240 * @ring: only applicable for RCS
1241 * @wa_ctx: structure representing wa_ctx
1242 * offset: specifies start of the batch, should be cache-aligned.
1243 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1244 * @batch: page in which WA are loaded
1245 * @offset: This field specifies the start of this batch.
1246 * This batch is started immediately after indirect_ctx batch. Since we ensure
1247 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1249 * The number of DWORDS written are returned using this field.
1251 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1252 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1254 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1255 struct i915_wa_ctx_bb
*wa_ctx
,
1256 uint32_t *const batch
,
1259 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1261 /* WaDisableCtxRestoreArbitration:bdw,chv */
1262 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1264 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1266 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1269 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1270 struct i915_wa_ctx_bb
*wa_ctx
,
1271 uint32_t *const batch
,
1275 struct drm_device
*dev
= engine
->dev
;
1276 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1278 /* WaDisableCtxRestoreArbitration:skl,bxt */
1279 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1280 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1281 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1283 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1284 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1289 /* Pad to end of cacheline */
1290 while (index
% CACHELINE_DWORDS
)
1291 wa_ctx_emit(batch
, index
, MI_NOOP
);
1293 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1296 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1297 struct i915_wa_ctx_bb
*wa_ctx
,
1298 uint32_t *const batch
,
1301 struct drm_device
*dev
= engine
->dev
;
1302 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1304 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1305 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
1306 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1307 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1308 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1309 wa_ctx_emit(batch
, index
,
1310 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1311 wa_ctx_emit(batch
, index
, MI_NOOP
);
1314 /* WaClearTdlStateAckDirtyBits:bxt */
1315 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1316 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1318 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1319 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1321 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1322 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1324 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1325 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1327 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1328 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1329 wa_ctx_emit(batch
, index
, 0x0);
1330 wa_ctx_emit(batch
, index
, MI_NOOP
);
1333 /* WaDisableCtxRestoreArbitration:skl,bxt */
1334 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1335 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1336 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1338 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1340 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1343 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1347 engine
->wa_ctx
.obj
= i915_gem_alloc_object(engine
->dev
,
1349 if (!engine
->wa_ctx
.obj
) {
1350 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1354 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1356 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1358 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1365 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1367 if (engine
->wa_ctx
.obj
) {
1368 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1369 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1370 engine
->wa_ctx
.obj
= NULL
;
1374 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1380 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1382 WARN_ON(engine
->id
!= RCS
);
1384 /* update this when WA for higher Gen are added */
1385 if (INTEL_INFO(engine
->dev
)->gen
> 9) {
1386 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1387 INTEL_INFO(engine
->dev
)->gen
);
1391 /* some WA perform writes to scratch page, ensure it is valid */
1392 if (engine
->scratch
.obj
== NULL
) {
1393 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1397 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1399 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1403 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1404 batch
= kmap_atomic(page
);
1407 if (INTEL_INFO(engine
->dev
)->gen
== 8) {
1408 ret
= gen8_init_indirectctx_bb(engine
,
1409 &wa_ctx
->indirect_ctx
,
1415 ret
= gen8_init_perctx_bb(engine
,
1421 } else if (INTEL_INFO(engine
->dev
)->gen
== 9) {
1422 ret
= gen9_init_indirectctx_bb(engine
,
1423 &wa_ctx
->indirect_ctx
,
1429 ret
= gen9_init_perctx_bb(engine
,
1438 kunmap_atomic(batch
);
1440 lrc_destroy_wa_ctx_obj(engine
);
1445 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1447 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
1449 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1450 (u32
)engine
->status_page
.gfx_addr
);
1451 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1454 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1456 struct drm_device
*dev
= engine
->dev
;
1457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1458 unsigned int next_context_status_buffer_hw
;
1460 lrc_init_hws(engine
);
1462 I915_WRITE_IMR(engine
,
1463 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1464 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1466 I915_WRITE(RING_MODE_GEN7(engine
),
1467 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1468 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1469 POSTING_READ(RING_MODE_GEN7(engine
));
1472 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1473 * zero, we need to read the write pointer from hardware and use its
1474 * value because "this register is power context save restored".
1475 * Effectively, these states have been observed:
1477 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1478 * BDW | CSB regs not reset | CSB regs reset |
1479 * CHT | CSB regs not reset | CSB regs not reset |
1483 next_context_status_buffer_hw
=
1484 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1487 * When the CSB registers are reset (also after power-up / gpu reset),
1488 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1489 * this special case, so the first element read is CSB[0].
1491 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1492 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1494 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1495 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1497 intel_engine_init_hangcheck(engine
);
1499 return intel_mocs_init_engine(engine
);
1502 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1504 struct drm_device
*dev
= engine
->dev
;
1505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1508 ret
= gen8_init_common_ring(engine
);
1512 /* We need to disable the AsyncFlip performance optimisations in order
1513 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1514 * programmed to '1' on all products.
1516 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1518 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1520 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1522 return init_workarounds_ring(engine
);
1525 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1529 ret
= gen8_init_common_ring(engine
);
1533 return init_workarounds_ring(engine
);
1536 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1538 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1539 struct intel_engine_cs
*engine
= req
->engine
;
1540 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1541 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1544 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1548 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1549 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1550 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1552 intel_logical_ring_emit_reg(ringbuf
,
1553 GEN8_RING_PDP_UDW(engine
, i
));
1554 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1555 intel_logical_ring_emit_reg(ringbuf
,
1556 GEN8_RING_PDP_LDW(engine
, i
));
1557 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1560 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1561 intel_logical_ring_advance(ringbuf
);
1566 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1567 u64 offset
, unsigned dispatch_flags
)
1569 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1570 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1573 /* Don't rely in hw updating PDPs, specially in lite-restore.
1574 * Ideally, we should set Force PD Restore in ctx descriptor,
1575 * but we can't. Force Restore would be a second option, but
1576 * it is unsafe in case of lite-restore (because the ctx is
1577 * not idle). PML4 is allocated during ppgtt init so this is
1578 * not needed in 48-bit.*/
1579 if (req
->ctx
->ppgtt
&&
1580 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1581 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1582 !intel_vgpu_active(req
->i915
->dev
)) {
1583 ret
= intel_logical_ring_emit_pdps(req
);
1588 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1591 ret
= intel_ring_begin(req
, 4);
1595 /* FIXME(BDW): Address space and security selectors. */
1596 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1598 (dispatch_flags
& I915_DISPATCH_RS
?
1599 MI_BATCH_RESOURCE_STREAMER
: 0));
1600 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1601 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1602 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1603 intel_logical_ring_advance(ringbuf
);
1608 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*engine
)
1610 struct drm_device
*dev
= engine
->dev
;
1611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1612 unsigned long flags
;
1614 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1617 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1618 if (engine
->irq_refcount
++ == 0) {
1619 I915_WRITE_IMR(engine
,
1620 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1621 POSTING_READ(RING_IMR(engine
->mmio_base
));
1623 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1628 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*engine
)
1630 struct drm_device
*dev
= engine
->dev
;
1631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 unsigned long flags
;
1634 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1635 if (--engine
->irq_refcount
== 0) {
1636 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1637 POSTING_READ(RING_IMR(engine
->mmio_base
));
1639 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1642 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1643 u32 invalidate_domains
,
1646 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1647 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1648 struct drm_device
*dev
= engine
->dev
;
1649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 ret
= intel_ring_begin(request
, 4);
1657 cmd
= MI_FLUSH_DW
+ 1;
1659 /* We always require a command barrier so that subsequent
1660 * commands, such as breadcrumb interrupts, are strictly ordered
1661 * wrt the contents of the write cache being flushed to memory
1662 * (and thus being coherent from the CPU).
1664 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1666 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1667 cmd
|= MI_INVALIDATE_TLB
;
1668 if (engine
== &dev_priv
->engine
[VCS
])
1669 cmd
|= MI_INVALIDATE_BSD
;
1672 intel_logical_ring_emit(ringbuf
, cmd
);
1673 intel_logical_ring_emit(ringbuf
,
1674 I915_GEM_HWS_SCRATCH_ADDR
|
1675 MI_FLUSH_DW_USE_GTT
);
1676 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1677 intel_logical_ring_emit(ringbuf
, 0); /* value */
1678 intel_logical_ring_advance(ringbuf
);
1683 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1684 u32 invalidate_domains
,
1687 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1688 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1689 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1690 bool vf_flush_wa
= false;
1694 flags
|= PIPE_CONTROL_CS_STALL
;
1696 if (flush_domains
) {
1697 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1698 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1699 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1700 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1703 if (invalidate_domains
) {
1704 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1705 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1706 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1707 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1708 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1709 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1710 flags
|= PIPE_CONTROL_QW_WRITE
;
1711 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1714 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1717 if (IS_GEN9(engine
->dev
))
1721 ret
= intel_ring_begin(request
, vf_flush_wa
? 12 : 6);
1726 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1727 intel_logical_ring_emit(ringbuf
, 0);
1728 intel_logical_ring_emit(ringbuf
, 0);
1729 intel_logical_ring_emit(ringbuf
, 0);
1730 intel_logical_ring_emit(ringbuf
, 0);
1731 intel_logical_ring_emit(ringbuf
, 0);
1734 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1735 intel_logical_ring_emit(ringbuf
, flags
);
1736 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1737 intel_logical_ring_emit(ringbuf
, 0);
1738 intel_logical_ring_emit(ringbuf
, 0);
1739 intel_logical_ring_emit(ringbuf
, 0);
1740 intel_logical_ring_advance(ringbuf
);
1745 static u32
gen8_get_seqno(struct intel_engine_cs
*engine
)
1747 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1750 static void gen8_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1752 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1755 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1758 * On BXT A steppings there is a HW coherency issue whereby the
1759 * MI_STORE_DATA_IMM storing the completed request's seqno
1760 * occasionally doesn't invalidate the CPU cache. Work around this by
1761 * clflushing the corresponding cacheline whenever the caller wants
1762 * the coherency to be guaranteed. Note that this cacheline is known
1763 * to be clean at this point, since we only write it in
1764 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1765 * this clflush in practice becomes an invalidate operation.
1767 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1770 static void bxt_a_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1772 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1774 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1775 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1779 * Reserve space for 2 NOOPs at the end of each request to be
1780 * used as a workaround for not being allowed to do lite
1781 * restore with HEAD==TAIL (WaIdleLiteRestore).
1783 #define WA_TAIL_DWORDS 2
1785 static inline u32
hws_seqno_address(struct intel_engine_cs
*engine
)
1787 return engine
->status_page
.gfx_addr
+ I915_GEM_HWS_INDEX_ADDR
;
1790 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1792 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1795 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1799 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1800 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1802 intel_logical_ring_emit(ringbuf
,
1803 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1804 intel_logical_ring_emit(ringbuf
,
1805 hws_seqno_address(request
->engine
) |
1806 MI_FLUSH_DW_USE_GTT
);
1807 intel_logical_ring_emit(ringbuf
, 0);
1808 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1809 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1810 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1811 return intel_logical_ring_advance_and_submit(request
);
1814 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1816 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1819 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1823 /* We're using qword write, seqno should be aligned to 8 bytes. */
1824 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1826 /* w/a for post sync ops following a GPGPU operation we
1827 * need a prior CS_STALL, which is emitted by the flush
1828 * following the batch.
1830 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1831 intel_logical_ring_emit(ringbuf
,
1832 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1833 PIPE_CONTROL_CS_STALL
|
1834 PIPE_CONTROL_QW_WRITE
));
1835 intel_logical_ring_emit(ringbuf
, hws_seqno_address(request
->engine
));
1836 intel_logical_ring_emit(ringbuf
, 0);
1837 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1838 /* We're thrashing one dword of HWS. */
1839 intel_logical_ring_emit(ringbuf
, 0);
1840 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1841 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1842 return intel_logical_ring_advance_and_submit(request
);
1845 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1847 struct render_state so
;
1850 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1854 if (so
.rodata
== NULL
)
1857 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1858 I915_DISPATCH_SECURE
);
1862 ret
= req
->engine
->emit_bb_start(req
,
1863 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1864 I915_DISPATCH_SECURE
);
1868 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1871 i915_gem_render_state_fini(&so
);
1875 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1879 ret
= intel_logical_ring_workarounds_emit(req
);
1883 ret
= intel_rcs_context_init_mocs(req
);
1885 * Failing to program the MOCS is non-fatal.The system will not
1886 * run at peak performance. So generate an error and carry on.
1889 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1891 return intel_lr_context_render_state_init(req
);
1895 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1897 * @ring: Engine Command Streamer.
1900 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1902 struct drm_i915_private
*dev_priv
;
1904 if (!intel_engine_initialized(engine
))
1908 * Tasklet cannot be active at this point due intel_mark_active/idle
1909 * so this is just for documentation.
1911 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1912 tasklet_kill(&engine
->irq_tasklet
);
1914 dev_priv
= engine
->dev
->dev_private
;
1916 if (engine
->buffer
) {
1917 intel_logical_ring_stop(engine
);
1918 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1921 if (engine
->cleanup
)
1922 engine
->cleanup(engine
);
1924 i915_cmd_parser_fini_ring(engine
);
1925 i915_gem_batch_pool_fini(&engine
->batch_pool
);
1927 if (engine
->status_page
.obj
) {
1928 i915_gem_object_unpin_map(engine
->status_page
.obj
);
1929 engine
->status_page
.obj
= NULL
;
1932 engine
->idle_lite_restore_wa
= 0;
1933 engine
->disable_lite_restore_wa
= false;
1934 engine
->ctx_desc_template
= 0;
1936 lrc_destroy_wa_ctx_obj(engine
);
1941 logical_ring_default_vfuncs(struct drm_device
*dev
,
1942 struct intel_engine_cs
*engine
)
1944 /* Default vfuncs which can be overriden by each engine. */
1945 engine
->init_hw
= gen8_init_common_ring
;
1946 engine
->emit_request
= gen8_emit_request
;
1947 engine
->emit_flush
= gen8_emit_flush
;
1948 engine
->irq_get
= gen8_logical_ring_get_irq
;
1949 engine
->irq_put
= gen8_logical_ring_put_irq
;
1950 engine
->emit_bb_start
= gen8_emit_bb_start
;
1951 engine
->get_seqno
= gen8_get_seqno
;
1952 engine
->set_seqno
= gen8_set_seqno
;
1953 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1954 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1955 engine
->set_seqno
= bxt_a_set_seqno
;
1960 logical_ring_default_irqs(struct intel_engine_cs
*engine
, unsigned shift
)
1962 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1963 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1967 lrc_setup_hws(struct intel_engine_cs
*engine
,
1968 struct drm_i915_gem_object
*dctx_obj
)
1972 /* The HWSP is part of the default context object in LRC mode. */
1973 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
) +
1974 LRC_PPHWSP_PN
* PAGE_SIZE
;
1975 hws
= i915_gem_object_pin_map(dctx_obj
);
1977 return PTR_ERR(hws
);
1978 engine
->status_page
.page_addr
= hws
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
1979 engine
->status_page
.obj
= dctx_obj
;
1985 logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*engine
)
1987 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1988 struct intel_context
*dctx
= dev_priv
->kernel_context
;
1989 enum forcewake_domains fw_domains
;
1992 /* Intentionally left blank. */
1993 engine
->buffer
= NULL
;
1996 INIT_LIST_HEAD(&engine
->active_list
);
1997 INIT_LIST_HEAD(&engine
->request_list
);
1998 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
1999 init_waitqueue_head(&engine
->irq_queue
);
2001 INIT_LIST_HEAD(&engine
->buffers
);
2002 INIT_LIST_HEAD(&engine
->execlist_queue
);
2003 INIT_LIST_HEAD(&engine
->execlist_retired_req_list
);
2004 spin_lock_init(&engine
->execlist_lock
);
2006 tasklet_init(&engine
->irq_tasklet
,
2007 intel_lrc_irq_handler
, (unsigned long)engine
);
2009 logical_ring_init_platform_invariants(engine
);
2011 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
2015 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2016 RING_CONTEXT_STATUS_PTR(engine
),
2017 FW_REG_READ
| FW_REG_WRITE
);
2019 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2020 RING_CONTEXT_STATUS_BUF_BASE(engine
),
2023 engine
->fw_domains
= fw_domains
;
2025 ret
= i915_cmd_parser_init_ring(engine
);
2029 ret
= intel_lr_context_deferred_alloc(dctx
, engine
);
2033 /* As this is the default context, always pin it */
2034 ret
= intel_lr_context_do_pin(dctx
, engine
);
2037 "Failed to pin and map ringbuffer %s: %d\n",
2042 /* And setup the hardware status page. */
2043 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
2045 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
2052 intel_logical_ring_cleanup(engine
);
2056 static int logical_render_ring_init(struct drm_device
*dev
)
2058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2059 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2062 engine
->name
= "render ring";
2064 engine
->exec_id
= I915_EXEC_RENDER
;
2065 engine
->guc_id
= GUC_RENDER_ENGINE
;
2066 engine
->mmio_base
= RENDER_RING_BASE
;
2068 logical_ring_default_irqs(engine
, GEN8_RCS_IRQ_SHIFT
);
2069 if (HAS_L3_DPF(dev
))
2070 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2072 logical_ring_default_vfuncs(dev
, engine
);
2074 /* Override some for render ring. */
2075 if (INTEL_INFO(dev
)->gen
>= 9)
2076 engine
->init_hw
= gen9_init_render_ring
;
2078 engine
->init_hw
= gen8_init_render_ring
;
2079 engine
->init_context
= gen8_init_rcs_context
;
2080 engine
->cleanup
= intel_fini_pipe_control
;
2081 engine
->emit_flush
= gen8_emit_flush_render
;
2082 engine
->emit_request
= gen8_emit_request_render
;
2086 ret
= intel_init_pipe_control(engine
);
2090 ret
= intel_init_workaround_bb(engine
);
2093 * We continue even if we fail to initialize WA batch
2094 * because we only expect rare glitches but nothing
2095 * critical to prevent us from using GPU
2097 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2101 ret
= logical_ring_init(dev
, engine
);
2103 lrc_destroy_wa_ctx_obj(engine
);
2109 static int logical_bsd_ring_init(struct drm_device
*dev
)
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2112 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2114 engine
->name
= "bsd ring";
2116 engine
->exec_id
= I915_EXEC_BSD
;
2117 engine
->guc_id
= GUC_VIDEO_ENGINE
;
2118 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2120 logical_ring_default_irqs(engine
, GEN8_VCS1_IRQ_SHIFT
);
2121 logical_ring_default_vfuncs(dev
, engine
);
2123 return logical_ring_init(dev
, engine
);
2126 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2129 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
2131 engine
->name
= "bsd2 ring";
2133 engine
->exec_id
= I915_EXEC_BSD
;
2134 engine
->guc_id
= GUC_VIDEO_ENGINE2
;
2135 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
2137 logical_ring_default_irqs(engine
, GEN8_VCS2_IRQ_SHIFT
);
2138 logical_ring_default_vfuncs(dev
, engine
);
2140 return logical_ring_init(dev
, engine
);
2143 static int logical_blt_ring_init(struct drm_device
*dev
)
2145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2146 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
2148 engine
->name
= "blitter ring";
2150 engine
->exec_id
= I915_EXEC_BLT
;
2151 engine
->guc_id
= GUC_BLITTER_ENGINE
;
2152 engine
->mmio_base
= BLT_RING_BASE
;
2154 logical_ring_default_irqs(engine
, GEN8_BCS_IRQ_SHIFT
);
2155 logical_ring_default_vfuncs(dev
, engine
);
2157 return logical_ring_init(dev
, engine
);
2160 static int logical_vebox_ring_init(struct drm_device
*dev
)
2162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2163 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
2165 engine
->name
= "video enhancement ring";
2167 engine
->exec_id
= I915_EXEC_VEBOX
;
2168 engine
->guc_id
= GUC_VIDEOENHANCE_ENGINE
;
2169 engine
->mmio_base
= VEBOX_RING_BASE
;
2171 logical_ring_default_irqs(engine
, GEN8_VECS_IRQ_SHIFT
);
2172 logical_ring_default_vfuncs(dev
, engine
);
2174 return logical_ring_init(dev
, engine
);
2178 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2181 * This function inits the engines for an Execlists submission style (the equivalent in the
2182 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2183 * those engines that are present in the hardware.
2185 * Return: non-zero if the initialization failed.
2187 int intel_logical_rings_init(struct drm_device
*dev
)
2189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2192 ret
= logical_render_ring_init(dev
);
2197 ret
= logical_bsd_ring_init(dev
);
2199 goto cleanup_render_ring
;
2203 ret
= logical_blt_ring_init(dev
);
2205 goto cleanup_bsd_ring
;
2208 if (HAS_VEBOX(dev
)) {
2209 ret
= logical_vebox_ring_init(dev
);
2211 goto cleanup_blt_ring
;
2214 if (HAS_BSD2(dev
)) {
2215 ret
= logical_bsd2_ring_init(dev
);
2217 goto cleanup_vebox_ring
;
2223 intel_logical_ring_cleanup(&dev_priv
->engine
[VECS
]);
2225 intel_logical_ring_cleanup(&dev_priv
->engine
[BCS
]);
2227 intel_logical_ring_cleanup(&dev_priv
->engine
[VCS
]);
2228 cleanup_render_ring
:
2229 intel_logical_ring_cleanup(&dev_priv
->engine
[RCS
]);
2235 make_rpcs(struct drm_device
*dev
)
2240 * No explicit RPCS request is needed to ensure full
2241 * slice/subslice/EU enablement prior to Gen9.
2243 if (INTEL_INFO(dev
)->gen
< 9)
2247 * Starting in Gen9, render power gating can leave
2248 * slice/subslice/EU in a partially enabled state. We
2249 * must make an explicit request through RPCS for full
2252 if (INTEL_INFO(dev
)->has_slice_pg
) {
2253 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2254 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2255 GEN8_RPCS_S_CNT_SHIFT
;
2256 rpcs
|= GEN8_RPCS_ENABLE
;
2259 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2260 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2261 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2262 GEN8_RPCS_SS_CNT_SHIFT
;
2263 rpcs
|= GEN8_RPCS_ENABLE
;
2266 if (INTEL_INFO(dev
)->has_eu_pg
) {
2267 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2268 GEN8_RPCS_EU_MIN_SHIFT
;
2269 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2270 GEN8_RPCS_EU_MAX_SHIFT
;
2271 rpcs
|= GEN8_RPCS_ENABLE
;
2277 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2279 u32 indirect_ctx_offset
;
2281 switch (INTEL_INFO(engine
->dev
)->gen
) {
2283 MISSING_CASE(INTEL_INFO(engine
->dev
)->gen
);
2286 indirect_ctx_offset
=
2287 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2290 indirect_ctx_offset
=
2291 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2295 return indirect_ctx_offset
;
2299 populate_lr_context(struct intel_context
*ctx
,
2300 struct drm_i915_gem_object
*ctx_obj
,
2301 struct intel_engine_cs
*engine
,
2302 struct intel_ringbuffer
*ringbuf
)
2304 struct drm_device
*dev
= engine
->dev
;
2305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2306 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2312 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2314 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2316 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2320 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2321 if (IS_ERR(vaddr
)) {
2322 ret
= PTR_ERR(vaddr
);
2323 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2326 ctx_obj
->dirty
= true;
2328 /* The second page of the context object contains some fields which must
2329 * be set up prior to the first execution. */
2330 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2332 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2333 * commands followed by (reg, value) pairs. The values we are setting here are
2334 * only for the first context restore: on a subsequent save, the GPU will
2335 * recreate this batchbuffer with new values (including all the missing
2336 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2337 reg_state
[CTX_LRI_HEADER_0
] =
2338 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2339 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2340 RING_CONTEXT_CONTROL(engine
),
2341 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2342 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2343 (HAS_RESOURCE_STREAMER(dev
) ?
2344 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2345 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2347 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2349 /* Ring buffer start address is not known until the buffer is pinned.
2350 * It is written to the context image in execlists_update_context()
2352 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2353 RING_START(engine
->mmio_base
), 0);
2354 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2355 RING_CTL(engine
->mmio_base
),
2356 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2357 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2358 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2359 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2360 RING_BBADDR(engine
->mmio_base
), 0);
2361 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2362 RING_BBSTATE(engine
->mmio_base
),
2364 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2365 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2366 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2367 RING_SBBADDR(engine
->mmio_base
), 0);
2368 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2369 RING_SBBSTATE(engine
->mmio_base
), 0);
2370 if (engine
->id
== RCS
) {
2371 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2372 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2373 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2374 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2375 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2376 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2377 if (engine
->wa_ctx
.obj
) {
2378 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2379 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2381 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2382 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2383 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2385 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2386 intel_lr_indirect_ctx_offset(engine
) << 6;
2388 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2389 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2393 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2394 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2395 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2396 /* PDP values well be assigned later if needed */
2397 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2399 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2401 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2403 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2405 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2407 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2409 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2411 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2414 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2415 /* 64b PPGTT (48bit canonical)
2416 * PDP0_DESCRIPTOR contains the base address to PML4 and
2417 * other PDP Descriptors are ignored.
2419 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2422 * PDP*_DESCRIPTOR contains the base address of space supported.
2423 * With dynamic page allocation, PDPs may not be allocated at
2424 * this point. Point the unallocated PDPs to the scratch page
2426 execlists_update_context_pdps(ppgtt
, reg_state
);
2429 if (engine
->id
== RCS
) {
2430 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2431 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2435 i915_gem_object_unpin_map(ctx_obj
);
2441 * intel_lr_context_free() - free the LRC specific bits of a context
2442 * @ctx: the LR context to free.
2444 * The real context freeing is done in i915_gem_context_free: this only
2445 * takes care of the bits that are LRC related: the per-engine backing
2446 * objects and the logical ringbuffer.
2448 void intel_lr_context_free(struct intel_context
*ctx
)
2452 for (i
= I915_NUM_ENGINES
; --i
>= 0; ) {
2453 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
2454 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2459 if (ctx
== ctx
->i915
->kernel_context
) {
2460 intel_unpin_ringbuffer_obj(ringbuf
);
2461 i915_gem_object_ggtt_unpin(ctx_obj
);
2462 i915_gem_object_unpin_map(ctx_obj
);
2465 WARN_ON(ctx
->engine
[i
].pin_count
);
2466 intel_ringbuffer_free(ringbuf
);
2467 drm_gem_object_unreference(&ctx_obj
->base
);
2472 * intel_lr_context_size() - return the size of the context for an engine
2473 * @ring: which engine to find the context size for
2475 * Each engine may require a different amount of space for a context image,
2476 * so when allocating (or copying) an image, this function can be used to
2477 * find the right size for the specific engine.
2479 * Return: size (in bytes) of an engine-specific context image
2481 * Note: this size includes the HWSP, which is part of the context image
2482 * in LRC mode, but does not include the "shared data page" used with
2483 * GuC submission. The caller should account for this if using the GuC.
2485 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2489 WARN_ON(INTEL_INFO(engine
->dev
)->gen
< 8);
2491 switch (engine
->id
) {
2493 if (INTEL_INFO(engine
->dev
)->gen
>= 9)
2494 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2496 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2502 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2510 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2511 * @ctx: LR context to create.
2512 * @ring: engine to be used with the context.
2514 * This function can be called more than once, with different engines, if we plan
2515 * to use the context with them. The context backing objects and the ringbuffers
2516 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2517 * the creation is a deferred call: it's better to make sure first that we need to use
2518 * a given ring with the context.
2520 * Return: non-zero on error.
2523 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
2524 struct intel_engine_cs
*engine
)
2526 struct drm_device
*dev
= engine
->dev
;
2527 struct drm_i915_gem_object
*ctx_obj
;
2528 uint32_t context_size
;
2529 struct intel_ringbuffer
*ringbuf
;
2532 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2533 WARN_ON(ctx
->engine
[engine
->id
].state
);
2535 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2537 /* One extra page as the sharing data between driver and GuC */
2538 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2540 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2542 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2546 ringbuf
= intel_engine_create_ringbuffer(engine
, 4 * PAGE_SIZE
);
2547 if (IS_ERR(ringbuf
)) {
2548 ret
= PTR_ERR(ringbuf
);
2549 goto error_deref_obj
;
2552 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2554 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2558 ctx
->engine
[engine
->id
].ringbuf
= ringbuf
;
2559 ctx
->engine
[engine
->id
].state
= ctx_obj
;
2561 if (ctx
!= ctx
->i915
->kernel_context
&& engine
->init_context
) {
2562 struct drm_i915_gem_request
*req
;
2564 req
= i915_gem_request_alloc(engine
, ctx
);
2567 DRM_ERROR("ring create req: %d\n", ret
);
2571 ret
= engine
->init_context(req
);
2572 i915_add_request_no_flush(req
);
2574 DRM_ERROR("ring init context: %d\n",
2582 intel_ringbuffer_free(ringbuf
);
2584 drm_gem_object_unreference(&ctx_obj
->base
);
2585 ctx
->engine
[engine
->id
].ringbuf
= NULL
;
2586 ctx
->engine
[engine
->id
].state
= NULL
;
2590 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2591 struct intel_context
*ctx
)
2593 struct intel_engine_cs
*engine
;
2595 for_each_engine(engine
, dev_priv
) {
2596 struct drm_i915_gem_object
*ctx_obj
=
2597 ctx
->engine
[engine
->id
].state
;
2598 struct intel_ringbuffer
*ringbuf
=
2599 ctx
->engine
[engine
->id
].ringbuf
;
2601 uint32_t *reg_state
;
2606 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2607 if (WARN_ON(IS_ERR(vaddr
)))
2610 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2611 ctx_obj
->dirty
= true;
2613 reg_state
[CTX_RING_HEAD
+1] = 0;
2614 reg_state
[CTX_RING_TAIL
+1] = 0;
2616 i915_gem_object_unpin_map(ctx_obj
);