2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT
= 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT
, /* Debug only */
224 FAULT_AND_CONTINUE
/* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
230 static int intel_lr_context_pin(struct intel_context
*ctx
,
231 struct intel_engine_cs
*engine
);
234 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
236 * @enable_execlists: value of i915.enable_execlists module parameter.
238 * Only certain platforms support Execlists (the prerequisites being
239 * support for Logical Ring Contexts and Aliasing PPGTT or better).
241 * Return: 1 if Execlists is supported and has to be enabled.
243 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
245 WARN_ON(i915
.enable_ppgtt
== -1);
247 /* On platforms with execlist available, vGPU will only
248 * support execlist mode, no ring buffer mode.
250 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
253 if (INTEL_INFO(dev
)->gen
>= 9)
256 if (enable_execlists
== 0)
259 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
260 i915
.use_mmio_flip
>= 0)
267 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
269 struct drm_device
*dev
= engine
->dev
;
271 if (IS_GEN8(dev
) || IS_GEN9(dev
))
272 engine
->idle_lite_restore_wa
= ~0;
274 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
275 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) &&
276 (engine
->id
== VCS
|| engine
->id
== VCS2
);
278 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
279 engine
->ctx_desc_template
|= GEN8_CTX_ADDRESSING_MODE(dev
) <<
280 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
282 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
283 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
285 /* TODO: WaDisableLiteRestore when we start using semaphore
286 * signalling between Command Streamers */
287 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
289 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
290 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
291 if (engine
->disable_lite_restore_wa
)
292 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
296 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
297 * descriptor for a pinned context
299 * @ctx: Context to work on
300 * @ring: Engine the descriptor will be used with
302 * The context descriptor encodes various attributes of a context,
303 * including its GTT address and some flags. Because it's fairly
304 * expensive to calculate, we'll just do it once and cache the result,
305 * which remains valid until the context is unpinned.
307 * This is what a descriptor looks like, from LSB to MSB:
308 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
309 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
310 * bits 32-52: ctx ID, a globally unique tag (the LRCA again!)
311 * bits 53-54: mbz, reserved for use by hardware
312 * bits 55-63: group ID, currently unused and set to 0
315 intel_lr_context_descriptor_update(struct intel_context
*ctx
,
316 struct intel_engine_cs
*engine
)
320 lrca
= ctx
->engine
[engine
->id
].lrc_vma
->node
.start
+
321 LRC_PPHWSP_PN
* PAGE_SIZE
;
323 desc
= engine
->ctx_desc_template
; /* bits 0-11 */
324 desc
|= lrca
; /* bits 12-31 */
325 desc
|= (lrca
>> PAGE_SHIFT
) << GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
327 ctx
->engine
[engine
->id
].lrc_desc
= desc
;
330 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
331 struct intel_engine_cs
*engine
)
333 return ctx
->engine
[engine
->id
].lrc_desc
;
337 * intel_execlists_ctx_id() - get the Execlists Context ID
338 * @ctx: Context to get the ID for
339 * @ring: Engine to get the ID for
341 * Do not confuse with ctx->id! Unfortunately we have a name overload
342 * here: the old context ID we pass to userspace as a handler so that
343 * they can refer to a context, and the new context ID we pass to the
344 * ELSP so that the GPU can inform us of the context status via
347 * The context ID is a portion of the context descriptor, so we can
348 * just extract the required part from the cached descriptor.
350 * Return: 20-bits globally unique context ID.
352 u32
intel_execlists_ctx_id(struct intel_context
*ctx
,
353 struct intel_engine_cs
*engine
)
355 return intel_lr_context_descriptor(ctx
, engine
) >> GEN8_CTX_ID_SHIFT
;
358 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
359 struct drm_i915_gem_request
*rq1
)
362 struct intel_engine_cs
*engine
= rq0
->engine
;
363 struct drm_device
*dev
= engine
->dev
;
364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
368 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
369 rq1
->elsp_submitted
++;
374 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
375 rq0
->elsp_submitted
++;
377 /* You must always write both descriptors in the order below. */
378 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
379 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
381 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
382 /* The context is automatically loaded after the following */
383 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
385 /* ELSP is a wo register, use another nearby reg for posting */
386 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
390 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
392 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
393 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
394 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
395 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
398 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
400 struct intel_engine_cs
*engine
= rq
->engine
;
401 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
402 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
404 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
406 /* True 32b PPGTT with dynamic page allocation: update PDP
407 * registers and point the unallocated PDPs to scratch page.
408 * PML4 is allocated during ppgtt init, so this is not needed
411 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
412 execlists_update_context_pdps(ppgtt
, reg_state
);
415 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
416 struct drm_i915_gem_request
*rq1
)
418 struct drm_i915_private
*dev_priv
= rq0
->i915
;
419 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
421 execlists_update_context(rq0
);
424 execlists_update_context(rq1
);
426 spin_lock_irq(&dev_priv
->uncore
.lock
);
427 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
429 execlists_elsp_write(rq0
, rq1
);
431 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
432 spin_unlock_irq(&dev_priv
->uncore
.lock
);
435 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
437 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
438 struct drm_i915_gem_request
*cursor
, *tmp
;
440 assert_spin_locked(&engine
->execlist_lock
);
443 * If irqs are not active generate a warning as batches that finish
444 * without the irqs may get lost and a GPU Hang may occur.
446 WARN_ON(!intel_irqs_enabled(engine
->dev
->dev_private
));
448 /* Try to read in pairs */
449 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
453 } else if (req0
->ctx
== cursor
->ctx
) {
454 /* Same ctx: ignore first request, as second request
455 * will update tail past first request's workload */
456 cursor
->elsp_submitted
= req0
->elsp_submitted
;
457 list_move_tail(&req0
->execlist_link
,
458 &engine
->execlist_retired_req_list
);
462 WARN_ON(req1
->elsp_submitted
);
470 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
472 * WaIdleLiteRestore: make sure we never cause a lite restore
475 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
476 * resubmit the request. See gen8_emit_request() for where we
477 * prepare the padding after the end of the request.
479 struct intel_ringbuffer
*ringbuf
;
481 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
483 req0
->tail
&= ringbuf
->size
- 1;
486 execlists_submit_requests(req0
, req1
);
490 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 request_id
)
492 struct drm_i915_gem_request
*head_req
;
494 assert_spin_locked(&engine
->execlist_lock
);
496 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
497 struct drm_i915_gem_request
,
503 if (unlikely(intel_execlists_ctx_id(head_req
->ctx
, engine
) != request_id
))
506 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
508 if (--head_req
->elsp_submitted
> 0)
511 list_move_tail(&head_req
->execlist_link
,
512 &engine
->execlist_retired_req_list
);
518 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
521 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
524 read_pointer
%= GEN8_CSB_ENTRIES
;
526 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
528 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
531 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
538 * intel_lrc_irq_handler() - handle Context Switch interrupts
539 * @engine: Engine Command Streamer to handle.
541 * Check the unread Context Status Buffers and manage the submission of new
542 * contexts to the ELSP accordingly.
544 static void intel_lrc_irq_handler(unsigned long data
)
546 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
547 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
549 unsigned int read_pointer
, write_pointer
;
550 u32 csb
[GEN8_CSB_ENTRIES
][2];
551 unsigned int csb_read
= 0, i
;
552 unsigned int submit_contexts
= 0;
554 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
556 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
558 read_pointer
= engine
->next_context_status_buffer
;
559 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
560 if (read_pointer
> write_pointer
)
561 write_pointer
+= GEN8_CSB_ENTRIES
;
563 while (read_pointer
< write_pointer
) {
564 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
566 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
571 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
573 /* Update the read pointer to the old write pointer. Manual ringbuffer
574 * management ftw </sarcasm> */
575 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
576 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
577 engine
->next_context_status_buffer
<< 8));
579 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
581 spin_lock(&engine
->execlist_lock
);
583 for (i
= 0; i
< csb_read
; i
++) {
584 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
585 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
586 if (execlists_check_remove_request(engine
, csb
[i
][1]))
587 WARN(1, "Lite Restored request removed from queue\n");
589 WARN(1, "Preemption without Lite Restore\n");
592 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
593 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
595 execlists_check_remove_request(engine
, csb
[i
][1]);
598 if (submit_contexts
) {
599 if (!engine
->disable_lite_restore_wa
||
600 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
601 execlists_context_unqueue(engine
);
604 spin_unlock(&engine
->execlist_lock
);
606 if (unlikely(submit_contexts
> 2))
607 DRM_ERROR("More than two context complete events?\n");
610 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
612 struct intel_engine_cs
*engine
= request
->engine
;
613 struct drm_i915_gem_request
*cursor
;
614 int num_elements
= 0;
616 if (request
->ctx
!= request
->i915
->kernel_context
)
617 intel_lr_context_pin(request
->ctx
, engine
);
619 i915_gem_request_reference(request
);
621 spin_lock_bh(&engine
->execlist_lock
);
623 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
624 if (++num_elements
> 2)
627 if (num_elements
> 2) {
628 struct drm_i915_gem_request
*tail_req
;
630 tail_req
= list_last_entry(&engine
->execlist_queue
,
631 struct drm_i915_gem_request
,
634 if (request
->ctx
== tail_req
->ctx
) {
635 WARN(tail_req
->elsp_submitted
!= 0,
636 "More than 2 already-submitted reqs queued\n");
637 list_move_tail(&tail_req
->execlist_link
,
638 &engine
->execlist_retired_req_list
);
642 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
643 if (num_elements
== 0)
644 execlists_context_unqueue(engine
);
646 spin_unlock_bh(&engine
->execlist_lock
);
649 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
651 struct intel_engine_cs
*engine
= req
->engine
;
652 uint32_t flush_domains
;
656 if (engine
->gpu_caches_dirty
)
657 flush_domains
= I915_GEM_GPU_DOMAINS
;
659 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
663 engine
->gpu_caches_dirty
= false;
667 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
668 struct list_head
*vmas
)
670 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
671 struct i915_vma
*vma
;
672 uint32_t flush_domains
= 0;
673 bool flush_chipset
= false;
676 list_for_each_entry(vma
, vmas
, exec_list
) {
677 struct drm_i915_gem_object
*obj
= vma
->obj
;
679 if (obj
->active
& other_rings
) {
680 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
685 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
686 flush_chipset
|= i915_gem_clflush_object(obj
, false);
688 flush_domains
|= obj
->base
.write_domain
;
691 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
694 /* Unconditionally invalidate gpu caches and ensure that we do flush
695 * any residual writes from the previous batch.
697 return logical_ring_invalidate_all_caches(req
);
700 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
704 /* Flush enough space to reduce the likelihood of waiting after
705 * we start building the request - in which case we will just
706 * have to repeat work.
708 request
->reserved_space
+= MIN_SPACE_FOR_ADD_REQUEST
;
710 request
->ringbuf
= request
->ctx
->engine
[request
->engine
->id
].ringbuf
;
712 if (i915
.enable_guc_submission
) {
714 * Check that the GuC has space for the request before
715 * going any further, as the i915_add_request() call
716 * later on mustn't fail ...
718 struct intel_guc
*guc
= &request
->i915
->guc
;
720 ret
= i915_guc_wq_check_space(guc
->execbuf_client
);
725 if (request
->ctx
!= request
->i915
->kernel_context
) {
726 ret
= intel_lr_context_pin(request
->ctx
, request
->engine
);
731 ret
= intel_ring_begin(request
, 0);
735 request
->reserved_space
-= MIN_SPACE_FOR_ADD_REQUEST
;
739 if (request
->ctx
!= request
->i915
->kernel_context
)
740 intel_lr_context_unpin(request
->ctx
, request
->engine
);
745 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
746 * @request: Request to advance the logical ringbuffer of.
748 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
749 * really happens during submission is that the context and current tail will be placed
750 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
751 * point, the tail *inside* the context is updated and the ELSP written to.
754 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
756 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
757 struct drm_i915_private
*dev_priv
= request
->i915
;
758 struct intel_engine_cs
*engine
= request
->engine
;
760 intel_logical_ring_advance(ringbuf
);
761 request
->tail
= ringbuf
->tail
;
764 * Here we add two extra NOOPs as padding to avoid
765 * lite restore of a context with HEAD==TAIL.
767 * Caller must reserve WA_TAIL_DWORDS for us!
769 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
770 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
771 intel_logical_ring_advance(ringbuf
);
773 if (intel_engine_stopped(engine
))
776 if (engine
->last_context
!= request
->ctx
) {
777 if (engine
->last_context
)
778 intel_lr_context_unpin(engine
->last_context
, engine
);
779 if (request
->ctx
!= request
->i915
->kernel_context
) {
780 intel_lr_context_pin(request
->ctx
, engine
);
781 engine
->last_context
= request
->ctx
;
783 engine
->last_context
= NULL
;
787 if (dev_priv
->guc
.execbuf_client
)
788 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
790 execlists_context_queue(request
);
796 * execlists_submission() - submit a batchbuffer for execution, Execlists style
799 * @ring: Engine Command Streamer to submit to.
800 * @ctx: Context to employ for this submission.
801 * @args: execbuffer call arguments.
802 * @vmas: list of vmas.
803 * @batch_obj: the batchbuffer to submit.
804 * @exec_start: batchbuffer start virtual address pointer.
805 * @dispatch_flags: translated execbuffer call flags.
807 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
808 * away the submission details of the execbuffer ioctl call.
810 * Return: non-zero if the submission fails.
812 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
813 struct drm_i915_gem_execbuffer2
*args
,
814 struct list_head
*vmas
)
816 struct drm_device
*dev
= params
->dev
;
817 struct intel_engine_cs
*engine
= params
->engine
;
818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
819 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
825 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
826 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
827 switch (instp_mode
) {
828 case I915_EXEC_CONSTANTS_REL_GENERAL
:
829 case I915_EXEC_CONSTANTS_ABSOLUTE
:
830 case I915_EXEC_CONSTANTS_REL_SURFACE
:
831 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
832 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
836 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
837 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
838 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
842 /* The HW changed the meaning on this bit on gen6 */
843 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
847 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
851 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
852 DRM_DEBUG("sol reset is gen7 only\n");
856 ret
= execlists_move_to_gpu(params
->request
, vmas
);
860 if (engine
== &dev_priv
->engine
[RCS
] &&
861 instp_mode
!= dev_priv
->relative_constants_mode
) {
862 ret
= intel_ring_begin(params
->request
, 4);
866 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
867 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
868 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
869 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
870 intel_logical_ring_advance(ringbuf
);
872 dev_priv
->relative_constants_mode
= instp_mode
;
875 exec_start
= params
->batch_obj_vm_offset
+
876 args
->batch_start_offset
;
878 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
882 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
884 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
889 void intel_execlists_retire_requests(struct intel_engine_cs
*engine
)
891 struct drm_i915_gem_request
*req
, *tmp
;
892 struct list_head retired_list
;
894 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
895 if (list_empty(&engine
->execlist_retired_req_list
))
898 INIT_LIST_HEAD(&retired_list
);
899 spin_lock_bh(&engine
->execlist_lock
);
900 list_replace_init(&engine
->execlist_retired_req_list
, &retired_list
);
901 spin_unlock_bh(&engine
->execlist_lock
);
903 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
904 struct intel_context
*ctx
= req
->ctx
;
905 struct drm_i915_gem_object
*ctx_obj
=
906 ctx
->engine
[engine
->id
].state
;
908 if (ctx_obj
&& (ctx
!= req
->i915
->kernel_context
))
909 intel_lr_context_unpin(ctx
, engine
);
911 list_del(&req
->execlist_link
);
912 i915_gem_request_unreference(req
);
916 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
918 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
921 if (!intel_engine_initialized(engine
))
924 ret
= intel_engine_idle(engine
);
926 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
929 /* TODO: Is this correct with Execlists enabled? */
930 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
931 if (wait_for((I915_READ_MODE(engine
) & MODE_IDLE
) != 0, 1000)) {
932 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
935 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
938 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
940 struct intel_engine_cs
*engine
= req
->engine
;
943 if (!engine
->gpu_caches_dirty
)
946 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
950 engine
->gpu_caches_dirty
= false;
954 static int intel_lr_context_do_pin(struct intel_context
*ctx
,
955 struct intel_engine_cs
*engine
)
957 struct drm_device
*dev
= engine
->dev
;
958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
959 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
960 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[engine
->id
].ringbuf
;
965 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
967 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
968 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
972 vaddr
= i915_gem_object_pin_map(ctx_obj
);
974 ret
= PTR_ERR(vaddr
);
978 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
980 ret
= intel_pin_and_map_ringbuffer_obj(engine
->dev
, ringbuf
);
984 ctx
->engine
[engine
->id
].lrc_vma
= i915_gem_obj_to_ggtt(ctx_obj
);
985 intel_lr_context_descriptor_update(ctx
, engine
);
986 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ringbuf
->vma
->node
.start
;
987 ctx
->engine
[engine
->id
].lrc_reg_state
= lrc_reg_state
;
988 ctx_obj
->dirty
= true;
990 /* Invalidate GuC TLB. */
991 if (i915
.enable_guc_submission
)
992 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
997 i915_gem_object_unpin_map(ctx_obj
);
999 i915_gem_object_ggtt_unpin(ctx_obj
);
1004 static int intel_lr_context_pin(struct intel_context
*ctx
,
1005 struct intel_engine_cs
*engine
)
1009 if (ctx
->engine
[engine
->id
].pin_count
++ == 0) {
1010 ret
= intel_lr_context_do_pin(ctx
, engine
);
1012 goto reset_pin_count
;
1014 i915_gem_context_reference(ctx
);
1019 ctx
->engine
[engine
->id
].pin_count
= 0;
1023 void intel_lr_context_unpin(struct intel_context
*ctx
,
1024 struct intel_engine_cs
*engine
)
1026 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
1028 WARN_ON(!mutex_is_locked(&ctx
->i915
->dev
->struct_mutex
));
1029 if (--ctx
->engine
[engine
->id
].pin_count
== 0) {
1030 i915_gem_object_unpin_map(ctx_obj
);
1031 intel_unpin_ringbuffer_obj(ctx
->engine
[engine
->id
].ringbuf
);
1032 i915_gem_object_ggtt_unpin(ctx_obj
);
1033 ctx
->engine
[engine
->id
].lrc_vma
= NULL
;
1034 ctx
->engine
[engine
->id
].lrc_desc
= 0;
1035 ctx
->engine
[engine
->id
].lrc_reg_state
= NULL
;
1037 i915_gem_context_unreference(ctx
);
1041 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1044 struct intel_engine_cs
*engine
= req
->engine
;
1045 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1046 struct drm_device
*dev
= engine
->dev
;
1047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1048 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1053 engine
->gpu_caches_dirty
= true;
1054 ret
= logical_ring_flush_all_caches(req
);
1058 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
1062 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1063 for (i
= 0; i
< w
->count
; i
++) {
1064 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1065 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1067 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1069 intel_logical_ring_advance(ringbuf
);
1071 engine
->gpu_caches_dirty
= true;
1072 ret
= logical_ring_flush_all_caches(req
);
1079 #define wa_ctx_emit(batch, index, cmd) \
1081 int __index = (index)++; \
1082 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1085 batch[__index] = (cmd); \
1088 #define wa_ctx_emit_reg(batch, index, reg) \
1089 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1092 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1093 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1094 * but there is a slight complication as this is applied in WA batch where the
1095 * values are only initialized once so we cannot take register value at the
1096 * beginning and reuse it further; hence we save its value to memory, upload a
1097 * constant value with bit21 set and then we restore it back with the saved value.
1098 * To simplify the WA, a constant value is formed by using the default value
1099 * of this register. This shouldn't be a problem because we are only modifying
1100 * it for a short period and this batch in non-premptible. We can ofcourse
1101 * use additional instructions that read the actual value of the register
1102 * at that time and set our bit of interest but it makes the WA complicated.
1104 * This WA is also required for Gen9 so extracting as a function avoids
1107 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1108 uint32_t *const batch
,
1111 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1114 * WaDisableLSQCROPERFforOCL:skl
1115 * This WA is implemented in skl_init_clock_gating() but since
1116 * this batch updates GEN8_L3SQCREG4 with default value we need to
1117 * set this bit here to retain the WA during flush.
1119 if (IS_SKL_REVID(engine
->dev
, 0, SKL_REVID_E0
))
1120 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1122 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1123 MI_SRM_LRM_GLOBAL_GTT
));
1124 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1125 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1126 wa_ctx_emit(batch
, index
, 0);
1128 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1129 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1130 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1132 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1133 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1134 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1135 wa_ctx_emit(batch
, index
, 0);
1136 wa_ctx_emit(batch
, index
, 0);
1137 wa_ctx_emit(batch
, index
, 0);
1138 wa_ctx_emit(batch
, index
, 0);
1140 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1141 MI_SRM_LRM_GLOBAL_GTT
));
1142 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1143 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1144 wa_ctx_emit(batch
, index
, 0);
1149 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1151 uint32_t start_alignment
)
1153 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1156 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1158 uint32_t size_alignment
)
1160 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1162 WARN(wa_ctx
->size
% size_alignment
,
1163 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1164 wa_ctx
->size
, size_alignment
);
1169 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1171 * @ring: only applicable for RCS
1172 * @wa_ctx: structure representing wa_ctx
1173 * offset: specifies start of the batch, should be cache-aligned. This is updated
1174 * with the offset value received as input.
1175 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1176 * @batch: page in which WA are loaded
1177 * @offset: This field specifies the start of the batch, it should be
1178 * cache-aligned otherwise it is adjusted accordingly.
1179 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1180 * initialized at the beginning and shared across all contexts but this field
1181 * helps us to have multiple batches at different offsets and select them based
1182 * on a criteria. At the moment this batch always start at the beginning of the page
1183 * and at this point we don't have multiple wa_ctx batch buffers.
1185 * The number of WA applied are not known at the beginning; we use this field
1186 * to return the no of DWORDS written.
1188 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1189 * so it adds NOOPs as padding to make it cacheline aligned.
1190 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1191 * makes a complete batch buffer.
1193 * Return: non-zero if we exceed the PAGE_SIZE limit.
1196 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1197 struct i915_wa_ctx_bb
*wa_ctx
,
1198 uint32_t *const batch
,
1201 uint32_t scratch_addr
;
1202 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1204 /* WaDisableCtxRestoreArbitration:bdw,chv */
1205 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1207 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1208 if (IS_BROADWELL(engine
->dev
)) {
1209 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1215 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1216 /* Actual scratch location is at 128 bytes offset */
1217 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1219 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1220 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1221 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1222 PIPE_CONTROL_CS_STALL
|
1223 PIPE_CONTROL_QW_WRITE
));
1224 wa_ctx_emit(batch
, index
, scratch_addr
);
1225 wa_ctx_emit(batch
, index
, 0);
1226 wa_ctx_emit(batch
, index
, 0);
1227 wa_ctx_emit(batch
, index
, 0);
1229 /* Pad to end of cacheline */
1230 while (index
% CACHELINE_DWORDS
)
1231 wa_ctx_emit(batch
, index
, MI_NOOP
);
1234 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1235 * execution depends on the length specified in terms of cache lines
1236 * in the register CTX_RCS_INDIRECT_CTX
1239 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1243 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1245 * @ring: only applicable for RCS
1246 * @wa_ctx: structure representing wa_ctx
1247 * offset: specifies start of the batch, should be cache-aligned.
1248 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1249 * @batch: page in which WA are loaded
1250 * @offset: This field specifies the start of this batch.
1251 * This batch is started immediately after indirect_ctx batch. Since we ensure
1252 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1254 * The number of DWORDS written are returned using this field.
1256 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1257 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1259 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1260 struct i915_wa_ctx_bb
*wa_ctx
,
1261 uint32_t *const batch
,
1264 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1266 /* WaDisableCtxRestoreArbitration:bdw,chv */
1267 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1269 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1271 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1274 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1275 struct i915_wa_ctx_bb
*wa_ctx
,
1276 uint32_t *const batch
,
1280 struct drm_device
*dev
= engine
->dev
;
1281 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1283 /* WaDisableCtxRestoreArbitration:skl,bxt */
1284 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1285 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1286 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1288 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1289 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1294 /* Pad to end of cacheline */
1295 while (index
% CACHELINE_DWORDS
)
1296 wa_ctx_emit(batch
, index
, MI_NOOP
);
1298 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1301 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1302 struct i915_wa_ctx_bb
*wa_ctx
,
1303 uint32_t *const batch
,
1306 struct drm_device
*dev
= engine
->dev
;
1307 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1309 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1310 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
1311 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1312 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1313 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1314 wa_ctx_emit(batch
, index
,
1315 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1316 wa_ctx_emit(batch
, index
, MI_NOOP
);
1319 /* WaClearTdlStateAckDirtyBits:bxt */
1320 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1321 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1323 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1324 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1326 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1327 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1329 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1330 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1332 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1333 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1334 wa_ctx_emit(batch
, index
, 0x0);
1335 wa_ctx_emit(batch
, index
, MI_NOOP
);
1338 /* WaDisableCtxRestoreArbitration:skl,bxt */
1339 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1340 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1341 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1343 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1345 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1348 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1352 engine
->wa_ctx
.obj
= i915_gem_object_create(engine
->dev
,
1354 if (IS_ERR(engine
->wa_ctx
.obj
)) {
1355 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1356 ret
= PTR_ERR(engine
->wa_ctx
.obj
);
1357 engine
->wa_ctx
.obj
= NULL
;
1361 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1363 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1365 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1372 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1374 if (engine
->wa_ctx
.obj
) {
1375 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1376 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1377 engine
->wa_ctx
.obj
= NULL
;
1381 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1387 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1389 WARN_ON(engine
->id
!= RCS
);
1391 /* update this when WA for higher Gen are added */
1392 if (INTEL_INFO(engine
->dev
)->gen
> 9) {
1393 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1394 INTEL_INFO(engine
->dev
)->gen
);
1398 /* some WA perform writes to scratch page, ensure it is valid */
1399 if (engine
->scratch
.obj
== NULL
) {
1400 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1404 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1406 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1410 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1411 batch
= kmap_atomic(page
);
1414 if (INTEL_INFO(engine
->dev
)->gen
== 8) {
1415 ret
= gen8_init_indirectctx_bb(engine
,
1416 &wa_ctx
->indirect_ctx
,
1422 ret
= gen8_init_perctx_bb(engine
,
1428 } else if (INTEL_INFO(engine
->dev
)->gen
== 9) {
1429 ret
= gen9_init_indirectctx_bb(engine
,
1430 &wa_ctx
->indirect_ctx
,
1436 ret
= gen9_init_perctx_bb(engine
,
1445 kunmap_atomic(batch
);
1447 lrc_destroy_wa_ctx_obj(engine
);
1452 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1454 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
1456 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1457 (u32
)engine
->status_page
.gfx_addr
);
1458 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1461 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1463 struct drm_device
*dev
= engine
->dev
;
1464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 unsigned int next_context_status_buffer_hw
;
1467 lrc_init_hws(engine
);
1469 I915_WRITE_IMR(engine
,
1470 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1471 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1473 I915_WRITE(RING_MODE_GEN7(engine
),
1474 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1475 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1476 POSTING_READ(RING_MODE_GEN7(engine
));
1479 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1480 * zero, we need to read the write pointer from hardware and use its
1481 * value because "this register is power context save restored".
1482 * Effectively, these states have been observed:
1484 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1485 * BDW | CSB regs not reset | CSB regs reset |
1486 * CHT | CSB regs not reset | CSB regs not reset |
1490 next_context_status_buffer_hw
=
1491 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1494 * When the CSB registers are reset (also after power-up / gpu reset),
1495 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1496 * this special case, so the first element read is CSB[0].
1498 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1499 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1501 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1502 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1504 intel_engine_init_hangcheck(engine
);
1506 return intel_mocs_init_engine(engine
);
1509 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1511 struct drm_device
*dev
= engine
->dev
;
1512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1515 ret
= gen8_init_common_ring(engine
);
1519 /* We need to disable the AsyncFlip performance optimisations in order
1520 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1521 * programmed to '1' on all products.
1523 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1525 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1527 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1529 return init_workarounds_ring(engine
);
1532 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1536 ret
= gen8_init_common_ring(engine
);
1540 return init_workarounds_ring(engine
);
1543 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1545 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1546 struct intel_engine_cs
*engine
= req
->engine
;
1547 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1548 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1551 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1555 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1556 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1557 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1559 intel_logical_ring_emit_reg(ringbuf
,
1560 GEN8_RING_PDP_UDW(engine
, i
));
1561 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1562 intel_logical_ring_emit_reg(ringbuf
,
1563 GEN8_RING_PDP_LDW(engine
, i
));
1564 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1567 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1568 intel_logical_ring_advance(ringbuf
);
1573 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1574 u64 offset
, unsigned dispatch_flags
)
1576 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1577 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1580 /* Don't rely in hw updating PDPs, specially in lite-restore.
1581 * Ideally, we should set Force PD Restore in ctx descriptor,
1582 * but we can't. Force Restore would be a second option, but
1583 * it is unsafe in case of lite-restore (because the ctx is
1584 * not idle). PML4 is allocated during ppgtt init so this is
1585 * not needed in 48-bit.*/
1586 if (req
->ctx
->ppgtt
&&
1587 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1588 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1589 !intel_vgpu_active(req
->i915
->dev
)) {
1590 ret
= intel_logical_ring_emit_pdps(req
);
1595 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1598 ret
= intel_ring_begin(req
, 4);
1602 /* FIXME(BDW): Address space and security selectors. */
1603 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1605 (dispatch_flags
& I915_DISPATCH_RS
?
1606 MI_BATCH_RESOURCE_STREAMER
: 0));
1607 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1608 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1609 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1610 intel_logical_ring_advance(ringbuf
);
1615 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*engine
)
1617 struct drm_device
*dev
= engine
->dev
;
1618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1619 unsigned long flags
;
1621 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1624 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1625 if (engine
->irq_refcount
++ == 0) {
1626 I915_WRITE_IMR(engine
,
1627 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1628 POSTING_READ(RING_IMR(engine
->mmio_base
));
1630 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1635 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*engine
)
1637 struct drm_device
*dev
= engine
->dev
;
1638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 unsigned long flags
;
1641 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1642 if (--engine
->irq_refcount
== 0) {
1643 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1644 POSTING_READ(RING_IMR(engine
->mmio_base
));
1646 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1649 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1650 u32 invalidate_domains
,
1653 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1654 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1655 struct drm_device
*dev
= engine
->dev
;
1656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1660 ret
= intel_ring_begin(request
, 4);
1664 cmd
= MI_FLUSH_DW
+ 1;
1666 /* We always require a command barrier so that subsequent
1667 * commands, such as breadcrumb interrupts, are strictly ordered
1668 * wrt the contents of the write cache being flushed to memory
1669 * (and thus being coherent from the CPU).
1671 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1673 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1674 cmd
|= MI_INVALIDATE_TLB
;
1675 if (engine
== &dev_priv
->engine
[VCS
])
1676 cmd
|= MI_INVALIDATE_BSD
;
1679 intel_logical_ring_emit(ringbuf
, cmd
);
1680 intel_logical_ring_emit(ringbuf
,
1681 I915_GEM_HWS_SCRATCH_ADDR
|
1682 MI_FLUSH_DW_USE_GTT
);
1683 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1684 intel_logical_ring_emit(ringbuf
, 0); /* value */
1685 intel_logical_ring_advance(ringbuf
);
1690 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1691 u32 invalidate_domains
,
1694 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1695 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1696 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1697 bool vf_flush_wa
= false;
1701 flags
|= PIPE_CONTROL_CS_STALL
;
1703 if (flush_domains
) {
1704 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1705 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1706 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1707 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1710 if (invalidate_domains
) {
1711 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1712 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1713 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1714 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1715 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1716 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1717 flags
|= PIPE_CONTROL_QW_WRITE
;
1718 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1721 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1724 if (IS_GEN9(engine
->dev
))
1728 ret
= intel_ring_begin(request
, vf_flush_wa
? 12 : 6);
1733 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1734 intel_logical_ring_emit(ringbuf
, 0);
1735 intel_logical_ring_emit(ringbuf
, 0);
1736 intel_logical_ring_emit(ringbuf
, 0);
1737 intel_logical_ring_emit(ringbuf
, 0);
1738 intel_logical_ring_emit(ringbuf
, 0);
1741 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1742 intel_logical_ring_emit(ringbuf
, flags
);
1743 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1744 intel_logical_ring_emit(ringbuf
, 0);
1745 intel_logical_ring_emit(ringbuf
, 0);
1746 intel_logical_ring_emit(ringbuf
, 0);
1747 intel_logical_ring_advance(ringbuf
);
1752 static u32
gen8_get_seqno(struct intel_engine_cs
*engine
)
1754 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1757 static void gen8_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1759 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1762 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1765 * On BXT A steppings there is a HW coherency issue whereby the
1766 * MI_STORE_DATA_IMM storing the completed request's seqno
1767 * occasionally doesn't invalidate the CPU cache. Work around this by
1768 * clflushing the corresponding cacheline whenever the caller wants
1769 * the coherency to be guaranteed. Note that this cacheline is known
1770 * to be clean at this point, since we only write it in
1771 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1772 * this clflush in practice becomes an invalidate operation.
1774 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1777 static void bxt_a_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1779 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1781 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1782 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1786 * Reserve space for 2 NOOPs at the end of each request to be
1787 * used as a workaround for not being allowed to do lite
1788 * restore with HEAD==TAIL (WaIdleLiteRestore).
1790 #define WA_TAIL_DWORDS 2
1792 static inline u32
hws_seqno_address(struct intel_engine_cs
*engine
)
1794 return engine
->status_page
.gfx_addr
+ I915_GEM_HWS_INDEX_ADDR
;
1797 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1799 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1802 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1806 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1807 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1809 intel_logical_ring_emit(ringbuf
,
1810 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1811 intel_logical_ring_emit(ringbuf
,
1812 hws_seqno_address(request
->engine
) |
1813 MI_FLUSH_DW_USE_GTT
);
1814 intel_logical_ring_emit(ringbuf
, 0);
1815 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1816 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1817 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1818 return intel_logical_ring_advance_and_submit(request
);
1821 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1823 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1826 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1830 /* We're using qword write, seqno should be aligned to 8 bytes. */
1831 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1833 /* w/a for post sync ops following a GPGPU operation we
1834 * need a prior CS_STALL, which is emitted by the flush
1835 * following the batch.
1837 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1838 intel_logical_ring_emit(ringbuf
,
1839 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1840 PIPE_CONTROL_CS_STALL
|
1841 PIPE_CONTROL_QW_WRITE
));
1842 intel_logical_ring_emit(ringbuf
, hws_seqno_address(request
->engine
));
1843 intel_logical_ring_emit(ringbuf
, 0);
1844 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1845 /* We're thrashing one dword of HWS. */
1846 intel_logical_ring_emit(ringbuf
, 0);
1847 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1848 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1849 return intel_logical_ring_advance_and_submit(request
);
1852 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1854 struct render_state so
;
1857 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1861 if (so
.rodata
== NULL
)
1864 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1865 I915_DISPATCH_SECURE
);
1869 ret
= req
->engine
->emit_bb_start(req
,
1870 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1871 I915_DISPATCH_SECURE
);
1875 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1878 i915_gem_render_state_fini(&so
);
1882 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1886 ret
= intel_logical_ring_workarounds_emit(req
);
1890 ret
= intel_rcs_context_init_mocs(req
);
1892 * Failing to program the MOCS is non-fatal.The system will not
1893 * run at peak performance. So generate an error and carry on.
1896 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1898 return intel_lr_context_render_state_init(req
);
1902 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1904 * @ring: Engine Command Streamer.
1907 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1909 struct drm_i915_private
*dev_priv
;
1911 if (!intel_engine_initialized(engine
))
1915 * Tasklet cannot be active at this point due intel_mark_active/idle
1916 * so this is just for documentation.
1918 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1919 tasklet_kill(&engine
->irq_tasklet
);
1921 dev_priv
= engine
->dev
->dev_private
;
1923 if (engine
->buffer
) {
1924 intel_logical_ring_stop(engine
);
1925 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1928 if (engine
->cleanup
)
1929 engine
->cleanup(engine
);
1931 i915_cmd_parser_fini_ring(engine
);
1932 i915_gem_batch_pool_fini(&engine
->batch_pool
);
1934 if (engine
->status_page
.obj
) {
1935 i915_gem_object_unpin_map(engine
->status_page
.obj
);
1936 engine
->status_page
.obj
= NULL
;
1939 engine
->idle_lite_restore_wa
= 0;
1940 engine
->disable_lite_restore_wa
= false;
1941 engine
->ctx_desc_template
= 0;
1943 lrc_destroy_wa_ctx_obj(engine
);
1948 logical_ring_default_vfuncs(struct drm_device
*dev
,
1949 struct intel_engine_cs
*engine
)
1951 /* Default vfuncs which can be overriden by each engine. */
1952 engine
->init_hw
= gen8_init_common_ring
;
1953 engine
->emit_request
= gen8_emit_request
;
1954 engine
->emit_flush
= gen8_emit_flush
;
1955 engine
->irq_get
= gen8_logical_ring_get_irq
;
1956 engine
->irq_put
= gen8_logical_ring_put_irq
;
1957 engine
->emit_bb_start
= gen8_emit_bb_start
;
1958 engine
->get_seqno
= gen8_get_seqno
;
1959 engine
->set_seqno
= gen8_set_seqno
;
1960 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1961 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1962 engine
->set_seqno
= bxt_a_set_seqno
;
1967 logical_ring_default_irqs(struct intel_engine_cs
*engine
, unsigned shift
)
1969 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1970 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1974 lrc_setup_hws(struct intel_engine_cs
*engine
,
1975 struct drm_i915_gem_object
*dctx_obj
)
1979 /* The HWSP is part of the default context object in LRC mode. */
1980 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
) +
1981 LRC_PPHWSP_PN
* PAGE_SIZE
;
1982 hws
= i915_gem_object_pin_map(dctx_obj
);
1984 return PTR_ERR(hws
);
1985 engine
->status_page
.page_addr
= hws
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
1986 engine
->status_page
.obj
= dctx_obj
;
1992 logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*engine
)
1994 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1995 struct intel_context
*dctx
= dev_priv
->kernel_context
;
1996 enum forcewake_domains fw_domains
;
1999 /* Intentionally left blank. */
2000 engine
->buffer
= NULL
;
2003 INIT_LIST_HEAD(&engine
->active_list
);
2004 INIT_LIST_HEAD(&engine
->request_list
);
2005 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2006 init_waitqueue_head(&engine
->irq_queue
);
2008 INIT_LIST_HEAD(&engine
->buffers
);
2009 INIT_LIST_HEAD(&engine
->execlist_queue
);
2010 INIT_LIST_HEAD(&engine
->execlist_retired_req_list
);
2011 spin_lock_init(&engine
->execlist_lock
);
2013 tasklet_init(&engine
->irq_tasklet
,
2014 intel_lrc_irq_handler
, (unsigned long)engine
);
2016 logical_ring_init_platform_invariants(engine
);
2018 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
2022 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2023 RING_CONTEXT_STATUS_PTR(engine
),
2024 FW_REG_READ
| FW_REG_WRITE
);
2026 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2027 RING_CONTEXT_STATUS_BUF_BASE(engine
),
2030 engine
->fw_domains
= fw_domains
;
2032 ret
= i915_cmd_parser_init_ring(engine
);
2036 ret
= intel_lr_context_deferred_alloc(dctx
, engine
);
2040 /* As this is the default context, always pin it */
2041 ret
= intel_lr_context_do_pin(dctx
, engine
);
2044 "Failed to pin and map ringbuffer %s: %d\n",
2049 /* And setup the hardware status page. */
2050 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
2052 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
2059 intel_logical_ring_cleanup(engine
);
2063 static int logical_render_ring_init(struct drm_device
*dev
)
2065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2066 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2069 engine
->name
= "render ring";
2071 engine
->exec_id
= I915_EXEC_RENDER
;
2072 engine
->guc_id
= GUC_RENDER_ENGINE
;
2073 engine
->mmio_base
= RENDER_RING_BASE
;
2075 logical_ring_default_irqs(engine
, GEN8_RCS_IRQ_SHIFT
);
2076 if (HAS_L3_DPF(dev
))
2077 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2079 logical_ring_default_vfuncs(dev
, engine
);
2081 /* Override some for render ring. */
2082 if (INTEL_INFO(dev
)->gen
>= 9)
2083 engine
->init_hw
= gen9_init_render_ring
;
2085 engine
->init_hw
= gen8_init_render_ring
;
2086 engine
->init_context
= gen8_init_rcs_context
;
2087 engine
->cleanup
= intel_fini_pipe_control
;
2088 engine
->emit_flush
= gen8_emit_flush_render
;
2089 engine
->emit_request
= gen8_emit_request_render
;
2093 ret
= intel_init_pipe_control(engine
);
2097 ret
= intel_init_workaround_bb(engine
);
2100 * We continue even if we fail to initialize WA batch
2101 * because we only expect rare glitches but nothing
2102 * critical to prevent us from using GPU
2104 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2108 ret
= logical_ring_init(dev
, engine
);
2110 lrc_destroy_wa_ctx_obj(engine
);
2116 static int logical_bsd_ring_init(struct drm_device
*dev
)
2118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2119 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2121 engine
->name
= "bsd ring";
2123 engine
->exec_id
= I915_EXEC_BSD
;
2124 engine
->guc_id
= GUC_VIDEO_ENGINE
;
2125 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2127 logical_ring_default_irqs(engine
, GEN8_VCS1_IRQ_SHIFT
);
2128 logical_ring_default_vfuncs(dev
, engine
);
2130 return logical_ring_init(dev
, engine
);
2133 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2136 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
2138 engine
->name
= "bsd2 ring";
2140 engine
->exec_id
= I915_EXEC_BSD
;
2141 engine
->guc_id
= GUC_VIDEO_ENGINE2
;
2142 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
2144 logical_ring_default_irqs(engine
, GEN8_VCS2_IRQ_SHIFT
);
2145 logical_ring_default_vfuncs(dev
, engine
);
2147 return logical_ring_init(dev
, engine
);
2150 static int logical_blt_ring_init(struct drm_device
*dev
)
2152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2153 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
2155 engine
->name
= "blitter ring";
2157 engine
->exec_id
= I915_EXEC_BLT
;
2158 engine
->guc_id
= GUC_BLITTER_ENGINE
;
2159 engine
->mmio_base
= BLT_RING_BASE
;
2161 logical_ring_default_irqs(engine
, GEN8_BCS_IRQ_SHIFT
);
2162 logical_ring_default_vfuncs(dev
, engine
);
2164 return logical_ring_init(dev
, engine
);
2167 static int logical_vebox_ring_init(struct drm_device
*dev
)
2169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2170 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
2172 engine
->name
= "video enhancement ring";
2174 engine
->exec_id
= I915_EXEC_VEBOX
;
2175 engine
->guc_id
= GUC_VIDEOENHANCE_ENGINE
;
2176 engine
->mmio_base
= VEBOX_RING_BASE
;
2178 logical_ring_default_irqs(engine
, GEN8_VECS_IRQ_SHIFT
);
2179 logical_ring_default_vfuncs(dev
, engine
);
2181 return logical_ring_init(dev
, engine
);
2185 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2188 * This function inits the engines for an Execlists submission style (the equivalent in the
2189 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2190 * those engines that are present in the hardware.
2192 * Return: non-zero if the initialization failed.
2194 int intel_logical_rings_init(struct drm_device
*dev
)
2196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2199 ret
= logical_render_ring_init(dev
);
2204 ret
= logical_bsd_ring_init(dev
);
2206 goto cleanup_render_ring
;
2210 ret
= logical_blt_ring_init(dev
);
2212 goto cleanup_bsd_ring
;
2215 if (HAS_VEBOX(dev
)) {
2216 ret
= logical_vebox_ring_init(dev
);
2218 goto cleanup_blt_ring
;
2221 if (HAS_BSD2(dev
)) {
2222 ret
= logical_bsd2_ring_init(dev
);
2224 goto cleanup_vebox_ring
;
2230 intel_logical_ring_cleanup(&dev_priv
->engine
[VECS
]);
2232 intel_logical_ring_cleanup(&dev_priv
->engine
[BCS
]);
2234 intel_logical_ring_cleanup(&dev_priv
->engine
[VCS
]);
2235 cleanup_render_ring
:
2236 intel_logical_ring_cleanup(&dev_priv
->engine
[RCS
]);
2242 make_rpcs(struct drm_device
*dev
)
2247 * No explicit RPCS request is needed to ensure full
2248 * slice/subslice/EU enablement prior to Gen9.
2250 if (INTEL_INFO(dev
)->gen
< 9)
2254 * Starting in Gen9, render power gating can leave
2255 * slice/subslice/EU in a partially enabled state. We
2256 * must make an explicit request through RPCS for full
2259 if (INTEL_INFO(dev
)->has_slice_pg
) {
2260 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2261 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2262 GEN8_RPCS_S_CNT_SHIFT
;
2263 rpcs
|= GEN8_RPCS_ENABLE
;
2266 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2267 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2268 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2269 GEN8_RPCS_SS_CNT_SHIFT
;
2270 rpcs
|= GEN8_RPCS_ENABLE
;
2273 if (INTEL_INFO(dev
)->has_eu_pg
) {
2274 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2275 GEN8_RPCS_EU_MIN_SHIFT
;
2276 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2277 GEN8_RPCS_EU_MAX_SHIFT
;
2278 rpcs
|= GEN8_RPCS_ENABLE
;
2284 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2286 u32 indirect_ctx_offset
;
2288 switch (INTEL_INFO(engine
->dev
)->gen
) {
2290 MISSING_CASE(INTEL_INFO(engine
->dev
)->gen
);
2293 indirect_ctx_offset
=
2294 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2297 indirect_ctx_offset
=
2298 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2302 return indirect_ctx_offset
;
2306 populate_lr_context(struct intel_context
*ctx
,
2307 struct drm_i915_gem_object
*ctx_obj
,
2308 struct intel_engine_cs
*engine
,
2309 struct intel_ringbuffer
*ringbuf
)
2311 struct drm_device
*dev
= engine
->dev
;
2312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2313 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2319 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2321 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2323 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2327 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2328 if (IS_ERR(vaddr
)) {
2329 ret
= PTR_ERR(vaddr
);
2330 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2333 ctx_obj
->dirty
= true;
2335 /* The second page of the context object contains some fields which must
2336 * be set up prior to the first execution. */
2337 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2339 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2340 * commands followed by (reg, value) pairs. The values we are setting here are
2341 * only for the first context restore: on a subsequent save, the GPU will
2342 * recreate this batchbuffer with new values (including all the missing
2343 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2344 reg_state
[CTX_LRI_HEADER_0
] =
2345 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2346 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2347 RING_CONTEXT_CONTROL(engine
),
2348 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2349 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2350 (HAS_RESOURCE_STREAMER(dev
) ?
2351 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2352 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2354 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2356 /* Ring buffer start address is not known until the buffer is pinned.
2357 * It is written to the context image in execlists_update_context()
2359 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2360 RING_START(engine
->mmio_base
), 0);
2361 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2362 RING_CTL(engine
->mmio_base
),
2363 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2364 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2365 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2366 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2367 RING_BBADDR(engine
->mmio_base
), 0);
2368 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2369 RING_BBSTATE(engine
->mmio_base
),
2371 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2372 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2373 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2374 RING_SBBADDR(engine
->mmio_base
), 0);
2375 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2376 RING_SBBSTATE(engine
->mmio_base
), 0);
2377 if (engine
->id
== RCS
) {
2378 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2379 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2380 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2381 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2382 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2383 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2384 if (engine
->wa_ctx
.obj
) {
2385 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2386 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2388 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2389 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2390 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2392 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2393 intel_lr_indirect_ctx_offset(engine
) << 6;
2395 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2396 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2400 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2401 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2402 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2403 /* PDP values well be assigned later if needed */
2404 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2406 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2408 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2410 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2412 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2414 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2416 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2418 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2421 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2422 /* 64b PPGTT (48bit canonical)
2423 * PDP0_DESCRIPTOR contains the base address to PML4 and
2424 * other PDP Descriptors are ignored.
2426 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2429 * PDP*_DESCRIPTOR contains the base address of space supported.
2430 * With dynamic page allocation, PDPs may not be allocated at
2431 * this point. Point the unallocated PDPs to the scratch page
2433 execlists_update_context_pdps(ppgtt
, reg_state
);
2436 if (engine
->id
== RCS
) {
2437 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2438 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2442 i915_gem_object_unpin_map(ctx_obj
);
2448 * intel_lr_context_free() - free the LRC specific bits of a context
2449 * @ctx: the LR context to free.
2451 * The real context freeing is done in i915_gem_context_free: this only
2452 * takes care of the bits that are LRC related: the per-engine backing
2453 * objects and the logical ringbuffer.
2455 void intel_lr_context_free(struct intel_context
*ctx
)
2459 for (i
= I915_NUM_ENGINES
; --i
>= 0; ) {
2460 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
2461 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2466 if (ctx
== ctx
->i915
->kernel_context
) {
2467 intel_unpin_ringbuffer_obj(ringbuf
);
2468 i915_gem_object_ggtt_unpin(ctx_obj
);
2469 i915_gem_object_unpin_map(ctx_obj
);
2472 WARN_ON(ctx
->engine
[i
].pin_count
);
2473 intel_ringbuffer_free(ringbuf
);
2474 drm_gem_object_unreference(&ctx_obj
->base
);
2479 * intel_lr_context_size() - return the size of the context for an engine
2480 * @ring: which engine to find the context size for
2482 * Each engine may require a different amount of space for a context image,
2483 * so when allocating (or copying) an image, this function can be used to
2484 * find the right size for the specific engine.
2486 * Return: size (in bytes) of an engine-specific context image
2488 * Note: this size includes the HWSP, which is part of the context image
2489 * in LRC mode, but does not include the "shared data page" used with
2490 * GuC submission. The caller should account for this if using the GuC.
2492 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2496 WARN_ON(INTEL_INFO(engine
->dev
)->gen
< 8);
2498 switch (engine
->id
) {
2500 if (INTEL_INFO(engine
->dev
)->gen
>= 9)
2501 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2503 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2509 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2517 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2518 * @ctx: LR context to create.
2519 * @ring: engine to be used with the context.
2521 * This function can be called more than once, with different engines, if we plan
2522 * to use the context with them. The context backing objects and the ringbuffers
2523 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2524 * the creation is a deferred call: it's better to make sure first that we need to use
2525 * a given ring with the context.
2527 * Return: non-zero on error.
2530 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
2531 struct intel_engine_cs
*engine
)
2533 struct drm_device
*dev
= engine
->dev
;
2534 struct drm_i915_gem_object
*ctx_obj
;
2535 uint32_t context_size
;
2536 struct intel_ringbuffer
*ringbuf
;
2539 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2540 WARN_ON(ctx
->engine
[engine
->id
].state
);
2542 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2544 /* One extra page as the sharing data between driver and GuC */
2545 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2547 ctx_obj
= i915_gem_object_create(dev
, context_size
);
2548 if (IS_ERR(ctx_obj
)) {
2549 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2550 return PTR_ERR(ctx_obj
);
2553 ringbuf
= intel_engine_create_ringbuffer(engine
, 4 * PAGE_SIZE
);
2554 if (IS_ERR(ringbuf
)) {
2555 ret
= PTR_ERR(ringbuf
);
2556 goto error_deref_obj
;
2559 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2561 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2565 ctx
->engine
[engine
->id
].ringbuf
= ringbuf
;
2566 ctx
->engine
[engine
->id
].state
= ctx_obj
;
2568 if (ctx
!= ctx
->i915
->kernel_context
&& engine
->init_context
) {
2569 struct drm_i915_gem_request
*req
;
2571 req
= i915_gem_request_alloc(engine
, ctx
);
2574 DRM_ERROR("ring create req: %d\n", ret
);
2578 ret
= engine
->init_context(req
);
2579 i915_add_request_no_flush(req
);
2581 DRM_ERROR("ring init context: %d\n",
2589 intel_ringbuffer_free(ringbuf
);
2591 drm_gem_object_unreference(&ctx_obj
->base
);
2592 ctx
->engine
[engine
->id
].ringbuf
= NULL
;
2593 ctx
->engine
[engine
->id
].state
= NULL
;
2597 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2598 struct intel_context
*ctx
)
2600 struct intel_engine_cs
*engine
;
2602 for_each_engine(engine
, dev_priv
) {
2603 struct drm_i915_gem_object
*ctx_obj
=
2604 ctx
->engine
[engine
->id
].state
;
2605 struct intel_ringbuffer
*ringbuf
=
2606 ctx
->engine
[engine
->id
].ringbuf
;
2608 uint32_t *reg_state
;
2613 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2614 if (WARN_ON(IS_ERR(vaddr
)))
2617 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2618 ctx_obj
->dirty
= true;
2620 reg_state
[CTX_RING_HEAD
+1] = 0;
2621 reg_state
[CTX_RING_TAIL
+1] = 0;
2623 i915_gem_object_unpin_map(ctx_obj
);