2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
193 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
194 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
195 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
199 ADVANCED_CONTEXT
= 0,
204 #define GEN8_CTX_MODE_SHIFT 3
207 FAULT_AND_HALT
, /* Debug only */
209 FAULT_AND_CONTINUE
/* Unsupported */
211 #define GEN8_CTX_ID_SHIFT 32
212 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
214 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
);
217 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
219 * @enable_execlists: value of i915.enable_execlists module parameter.
221 * Only certain platforms support Execlists (the prerequisites being
222 * support for Logical Ring Contexts and Aliasing PPGTT or better).
224 * Return: 1 if Execlists is supported and has to be enabled.
226 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
228 WARN_ON(i915
.enable_ppgtt
== -1);
230 if (INTEL_INFO(dev
)->gen
>= 9)
233 if (enable_execlists
== 0)
236 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
237 i915
.use_mmio_flip
>= 0)
244 * intel_execlists_ctx_id() - get the Execlists Context ID
245 * @ctx_obj: Logical Ring Context backing object.
247 * Do not confuse with ctx->id! Unfortunately we have a name overload
248 * here: the old context ID we pass to userspace as a handler so that
249 * they can refer to a context, and the new context ID we pass to the
250 * ELSP so that the GPU can inform us of the context status via
253 * Return: 20-bits globally unique context ID.
255 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
257 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
259 /* LRCA is required to be 4K aligned so the more significant 20 bits
260 * are globally unique */
264 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs
*ring
,
265 struct drm_i915_gem_object
*ctx_obj
)
267 struct drm_device
*dev
= ring
->dev
;
269 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
271 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
273 desc
= GEN8_CTX_VALID
;
274 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
275 if (IS_GEN8(ctx_obj
->base
.dev
))
276 desc
|= GEN8_CTX_L3LLC_COHERENT
;
277 desc
|= GEN8_CTX_PRIVILEGE
;
279 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
281 /* TODO: WaDisableLiteRestore when we start using semaphore
282 * signalling between Command Streamers */
283 /* desc |= GEN8_CTX_FORCE_RESTORE; */
285 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
287 INTEL_REVID(dev
) <= SKL_REVID_B0
&&
288 (ring
->id
== BCS
|| ring
->id
== VCS
||
289 ring
->id
== VECS
|| ring
->id
== VCS2
))
290 desc
|= GEN8_CTX_FORCE_RESTORE
;
295 static void execlists_elsp_write(struct intel_engine_cs
*ring
,
296 struct drm_i915_gem_object
*ctx_obj0
,
297 struct drm_i915_gem_object
*ctx_obj1
)
299 struct drm_device
*dev
= ring
->dev
;
300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
304 /* XXX: You must always write both descriptors in the order below. */
306 temp
= execlists_ctx_descriptor(ring
, ctx_obj1
);
309 desc
[1] = (u32
)(temp
>> 32);
312 temp
= execlists_ctx_descriptor(ring
, ctx_obj0
);
313 desc
[3] = (u32
)(temp
>> 32);
316 spin_lock(&dev_priv
->uncore
.lock
);
317 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
318 I915_WRITE_FW(RING_ELSP(ring
), desc
[1]);
319 I915_WRITE_FW(RING_ELSP(ring
), desc
[0]);
320 I915_WRITE_FW(RING_ELSP(ring
), desc
[3]);
322 /* The context is automatically loaded after the following */
323 I915_WRITE_FW(RING_ELSP(ring
), desc
[2]);
325 /* ELSP is a wo register, so use another nearby reg for posting instead */
326 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
327 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
328 spin_unlock(&dev_priv
->uncore
.lock
);
331 static int execlists_update_context(struct drm_i915_gem_request
*rq
)
333 struct intel_engine_cs
*ring
= rq
->ring
;
334 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
335 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
336 struct drm_i915_gem_object
*rb_obj
= rq
->ringbuf
->obj
;
341 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj
));
342 WARN_ON(!i915_gem_obj_is_pinned(rb_obj
));
344 page
= i915_gem_object_get_page(ctx_obj
, 1);
345 reg_state
= kmap_atomic(page
);
347 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
348 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(rb_obj
);
350 /* True PPGTT with dynamic page allocation: update PDP registers and
351 * point the unallocated PDPs to the scratch page
354 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
355 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
356 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
357 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
360 kunmap_atomic(reg_state
);
365 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
366 struct drm_i915_gem_request
*rq1
)
368 struct intel_engine_cs
*ring
= rq0
->ring
;
369 struct drm_i915_gem_object
*ctx_obj0
= rq0
->ctx
->engine
[ring
->id
].state
;
370 struct drm_i915_gem_object
*ctx_obj1
= NULL
;
372 execlists_update_context(rq0
);
375 execlists_update_context(rq1
);
376 ctx_obj1
= rq1
->ctx
->engine
[ring
->id
].state
;
379 execlists_elsp_write(ring
, ctx_obj0
, ctx_obj1
);
382 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
384 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
385 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
387 assert_spin_locked(&ring
->execlist_lock
);
390 * If irqs are not active generate a warning as batches that finish
391 * without the irqs may get lost and a GPU Hang may occur.
393 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
395 if (list_empty(&ring
->execlist_queue
))
398 /* Try to read in pairs */
399 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
403 } else if (req0
->ctx
== cursor
->ctx
) {
404 /* Same ctx: ignore first request, as second request
405 * will update tail past first request's workload */
406 cursor
->elsp_submitted
= req0
->elsp_submitted
;
407 list_del(&req0
->execlist_link
);
408 list_add_tail(&req0
->execlist_link
,
409 &ring
->execlist_retired_req_list
);
417 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
419 * WaIdleLiteRestore: make sure we never cause a lite
420 * restore with HEAD==TAIL
422 if (req0
->elsp_submitted
) {
424 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
425 * as we resubmit the request. See gen8_emit_request()
426 * for where we prepare the padding after the end of the
429 struct intel_ringbuffer
*ringbuf
;
431 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
433 req0
->tail
&= ringbuf
->size
- 1;
437 WARN_ON(req1
&& req1
->elsp_submitted
);
439 execlists_submit_requests(req0
, req1
);
441 req0
->elsp_submitted
++;
443 req1
->elsp_submitted
++;
446 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
449 struct drm_i915_gem_request
*head_req
;
451 assert_spin_locked(&ring
->execlist_lock
);
453 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
454 struct drm_i915_gem_request
,
457 if (head_req
!= NULL
) {
458 struct drm_i915_gem_object
*ctx_obj
=
459 head_req
->ctx
->engine
[ring
->id
].state
;
460 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
461 WARN(head_req
->elsp_submitted
== 0,
462 "Never submitted head request\n");
464 if (--head_req
->elsp_submitted
<= 0) {
465 list_del(&head_req
->execlist_link
);
466 list_add_tail(&head_req
->execlist_link
,
467 &ring
->execlist_retired_req_list
);
477 * intel_lrc_irq_handler() - handle Context Switch interrupts
478 * @ring: Engine Command Streamer to handle.
480 * Check the unread Context Status Buffers and manage the submission of new
481 * contexts to the ELSP accordingly.
483 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
485 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
491 u32 submit_contexts
= 0;
493 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
495 read_pointer
= ring
->next_context_status_buffer
;
496 write_pointer
= status_pointer
& 0x07;
497 if (read_pointer
> write_pointer
)
500 spin_lock(&ring
->execlist_lock
);
502 while (read_pointer
< write_pointer
) {
504 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
505 (read_pointer
% 6) * 8);
506 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
507 (read_pointer
% 6) * 8 + 4);
509 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
510 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
511 if (execlists_check_remove_request(ring
, status_id
))
512 WARN(1, "Lite Restored request removed from queue\n");
514 WARN(1, "Preemption without Lite Restore\n");
517 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
518 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
519 if (execlists_check_remove_request(ring
, status_id
))
524 if (submit_contexts
!= 0)
525 execlists_context_unqueue(ring
);
527 spin_unlock(&ring
->execlist_lock
);
529 WARN(submit_contexts
> 2, "More than two context complete events?\n");
530 ring
->next_context_status_buffer
= write_pointer
% 6;
532 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
533 ((u32
)ring
->next_context_status_buffer
& 0x07) << 8);
536 static int execlists_context_queue(struct drm_i915_gem_request
*request
)
538 struct intel_engine_cs
*ring
= request
->ring
;
539 struct drm_i915_gem_request
*cursor
;
540 int num_elements
= 0;
542 if (request
->ctx
!= ring
->default_context
)
543 intel_lr_context_pin(request
);
545 i915_gem_request_reference(request
);
547 request
->tail
= request
->ringbuf
->tail
;
549 spin_lock_irq(&ring
->execlist_lock
);
551 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
552 if (++num_elements
> 2)
555 if (num_elements
> 2) {
556 struct drm_i915_gem_request
*tail_req
;
558 tail_req
= list_last_entry(&ring
->execlist_queue
,
559 struct drm_i915_gem_request
,
562 if (request
->ctx
== tail_req
->ctx
) {
563 WARN(tail_req
->elsp_submitted
!= 0,
564 "More than 2 already-submitted reqs queued\n");
565 list_del(&tail_req
->execlist_link
);
566 list_add_tail(&tail_req
->execlist_link
,
567 &ring
->execlist_retired_req_list
);
571 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
572 if (num_elements
== 0)
573 execlists_context_unqueue(ring
);
575 spin_unlock_irq(&ring
->execlist_lock
);
580 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
582 struct intel_engine_cs
*ring
= req
->ring
;
583 uint32_t flush_domains
;
587 if (ring
->gpu_caches_dirty
)
588 flush_domains
= I915_GEM_GPU_DOMAINS
;
590 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
594 ring
->gpu_caches_dirty
= false;
598 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
599 struct list_head
*vmas
)
601 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
602 struct i915_vma
*vma
;
603 uint32_t flush_domains
= 0;
604 bool flush_chipset
= false;
607 list_for_each_entry(vma
, vmas
, exec_list
) {
608 struct drm_i915_gem_object
*obj
= vma
->obj
;
610 if (obj
->active
& other_rings
) {
611 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
616 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
617 flush_chipset
|= i915_gem_clflush_object(obj
, false);
619 flush_domains
|= obj
->base
.write_domain
;
622 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
625 /* Unconditionally invalidate gpu caches and ensure that we do flush
626 * any residual writes from the previous batch.
628 return logical_ring_invalidate_all_caches(req
);
631 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
635 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
637 if (request
->ctx
!= request
->ring
->default_context
) {
638 ret
= intel_lr_context_pin(request
);
646 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
649 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
650 struct intel_engine_cs
*ring
= req
->ring
;
651 struct drm_i915_gem_request
*target
;
655 if (intel_ring_space(ringbuf
) >= bytes
)
658 /* The whole point of reserving space is to not wait! */
659 WARN_ON(ringbuf
->reserved_in_use
);
661 list_for_each_entry(target
, &ring
->request_list
, list
) {
663 * The request queue is per-engine, so can contain requests
664 * from multiple ringbuffers. Here, we must ignore any that
665 * aren't from the ringbuffer we're considering.
667 if (target
->ringbuf
!= ringbuf
)
670 /* Would completion of this request free enough space? */
671 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
677 if (WARN_ON(&target
->list
== &ring
->request_list
))
680 ret
= i915_wait_request(target
);
684 ringbuf
->space
= space
;
689 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
690 * @request: Request to advance the logical ringbuffer of.
692 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
693 * really happens during submission is that the context and current tail will be placed
694 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
695 * point, the tail *inside* the context is updated and the ELSP written to.
698 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
700 struct intel_engine_cs
*ring
= request
->ring
;
702 intel_logical_ring_advance(request
->ringbuf
);
704 if (intel_ring_stopped(ring
))
707 execlists_context_queue(request
);
710 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
712 uint32_t __iomem
*virt
;
713 int rem
= ringbuf
->size
- ringbuf
->tail
;
715 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
718 iowrite32(MI_NOOP
, virt
++);
721 intel_ring_update_space(ringbuf
);
724 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
726 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
727 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
728 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
729 int ret
, total_bytes
, wait_bytes
= 0;
730 bool need_wrap
= false;
732 if (ringbuf
->reserved_in_use
)
735 total_bytes
= bytes
+ ringbuf
->reserved_size
;
737 if (unlikely(bytes
> remain_usable
)) {
739 * Not enough space for the basic request. So need to flush
740 * out the remainder and then wait for base + reserved.
742 wait_bytes
= remain_actual
+ total_bytes
;
745 if (unlikely(total_bytes
> remain_usable
)) {
747 * The base request will fit but the reserved space
748 * falls off the end. So only need to to wait for the
749 * reserved size after flushing out the remainder.
751 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
753 } else if (total_bytes
> ringbuf
->space
) {
754 /* No wrapping required, just waiting. */
755 wait_bytes
= total_bytes
;
760 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
765 __wrap_ring_buffer(ringbuf
);
772 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
774 * @request: The request to start some new work for
775 * @ctx: Logical ring context whose ringbuffer is being prepared.
776 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
778 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
779 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
780 * and also preallocates a request (every workload submission is still mediated through
781 * requests, same as it did with legacy ringbuffer submission).
783 * Return: non-zero if the ringbuffer is not ready to be written to.
785 static int intel_logical_ring_begin(struct drm_i915_gem_request
*req
,
788 struct drm_i915_private
*dev_priv
;
791 WARN_ON(req
== NULL
);
792 dev_priv
= req
->ring
->dev
->dev_private
;
794 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
795 dev_priv
->mm
.interruptible
);
799 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
803 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
807 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
810 * The first call merely notes the reserve request and is common for
811 * all back ends. The subsequent localised _begin() call actually
812 * ensures that the reservation is available. Without the begin, if
813 * the request creator immediately submitted the request without
814 * adding any commands to it then there might not actually be
815 * sufficient room for the submission commands.
817 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
819 return intel_logical_ring_begin(request
, 0);
823 * execlists_submission() - submit a batchbuffer for execution, Execlists style
826 * @ring: Engine Command Streamer to submit to.
827 * @ctx: Context to employ for this submission.
828 * @args: execbuffer call arguments.
829 * @vmas: list of vmas.
830 * @batch_obj: the batchbuffer to submit.
831 * @exec_start: batchbuffer start virtual address pointer.
832 * @dispatch_flags: translated execbuffer call flags.
834 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
835 * away the submission details of the execbuffer ioctl call.
837 * Return: non-zero if the submission fails.
839 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
840 struct drm_i915_gem_execbuffer2
*args
,
841 struct list_head
*vmas
)
843 struct drm_device
*dev
= params
->dev
;
844 struct intel_engine_cs
*ring
= params
->ring
;
845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
846 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
852 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
853 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
854 switch (instp_mode
) {
855 case I915_EXEC_CONSTANTS_REL_GENERAL
:
856 case I915_EXEC_CONSTANTS_ABSOLUTE
:
857 case I915_EXEC_CONSTANTS_REL_SURFACE
:
858 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
859 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
863 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
864 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
865 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
869 /* The HW changed the meaning on this bit on gen6 */
870 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
874 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
878 if (args
->num_cliprects
!= 0) {
879 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
882 if (args
->DR4
== 0xffffffff) {
883 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
887 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
888 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
893 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
894 DRM_DEBUG("sol reset is gen7 only\n");
898 ret
= execlists_move_to_gpu(params
->request
, vmas
);
902 if (ring
== &dev_priv
->ring
[RCS
] &&
903 instp_mode
!= dev_priv
->relative_constants_mode
) {
904 ret
= intel_logical_ring_begin(params
->request
, 4);
908 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
909 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
910 intel_logical_ring_emit(ringbuf
, INSTPM
);
911 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
912 intel_logical_ring_advance(ringbuf
);
914 dev_priv
->relative_constants_mode
= instp_mode
;
917 exec_start
= params
->batch_obj_vm_offset
+
918 args
->batch_start_offset
;
920 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
924 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
926 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
927 i915_gem_execbuffer_retire_commands(params
);
932 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
934 struct drm_i915_gem_request
*req
, *tmp
;
935 struct list_head retired_list
;
937 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
938 if (list_empty(&ring
->execlist_retired_req_list
))
941 INIT_LIST_HEAD(&retired_list
);
942 spin_lock_irq(&ring
->execlist_lock
);
943 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
944 spin_unlock_irq(&ring
->execlist_lock
);
946 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
947 struct intel_context
*ctx
= req
->ctx
;
948 struct drm_i915_gem_object
*ctx_obj
=
949 ctx
->engine
[ring
->id
].state
;
951 if (ctx_obj
&& (ctx
!= ring
->default_context
))
952 intel_lr_context_unpin(req
);
953 list_del(&req
->execlist_link
);
954 i915_gem_request_unreference(req
);
958 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
960 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
963 if (!intel_ring_initialized(ring
))
966 ret
= intel_ring_idle(ring
);
967 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
968 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
971 /* TODO: Is this correct with Execlists enabled? */
972 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
973 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
974 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
977 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
980 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
982 struct intel_engine_cs
*ring
= req
->ring
;
985 if (!ring
->gpu_caches_dirty
)
988 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
992 ring
->gpu_caches_dirty
= false;
996 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
)
998 struct intel_engine_cs
*ring
= rq
->ring
;
999 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1000 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1003 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1004 if (rq
->ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1005 ret
= i915_gem_obj_ggtt_pin(ctx_obj
,
1006 GEN8_LR_CONTEXT_ALIGN
, 0);
1008 goto reset_pin_count
;
1010 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1018 i915_gem_object_ggtt_unpin(ctx_obj
);
1020 rq
->ctx
->engine
[ring
->id
].pin_count
= 0;
1025 void intel_lr_context_unpin(struct drm_i915_gem_request
*rq
)
1027 struct intel_engine_cs
*ring
= rq
->ring
;
1028 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1029 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1032 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1033 if (--rq
->ctx
->engine
[ring
->id
].pin_count
== 0) {
1034 intel_unpin_ringbuffer_obj(ringbuf
);
1035 i915_gem_object_ggtt_unpin(ctx_obj
);
1040 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1043 struct intel_engine_cs
*ring
= req
->ring
;
1044 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1045 struct drm_device
*dev
= ring
->dev
;
1046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1047 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1049 if (WARN_ON_ONCE(w
->count
== 0))
1052 ring
->gpu_caches_dirty
= true;
1053 ret
= logical_ring_flush_all_caches(req
);
1057 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1061 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1062 for (i
= 0; i
< w
->count
; i
++) {
1063 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1064 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1066 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1068 intel_logical_ring_advance(ringbuf
);
1070 ring
->gpu_caches_dirty
= true;
1071 ret
= logical_ring_flush_all_caches(req
);
1078 #define wa_ctx_emit(batch, cmd) \
1080 if (WARN_ON(index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1083 batch[index++] = (cmd); \
1088 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1089 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1090 * but there is a slight complication as this is applied in WA batch where the
1091 * values are only initialized once so we cannot take register value at the
1092 * beginning and reuse it further; hence we save its value to memory, upload a
1093 * constant value with bit21 set and then we restore it back with the saved value.
1094 * To simplify the WA, a constant value is formed by using the default value
1095 * of this register. This shouldn't be a problem because we are only modifying
1096 * it for a short period and this batch in non-premptible. We can ofcourse
1097 * use additional instructions that read the actual value of the register
1098 * at that time and set our bit of interest but it makes the WA complicated.
1100 * This WA is also required for Gen9 so extracting as a function avoids
1103 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*ring
,
1104 uint32_t *const batch
,
1107 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1109 wa_ctx_emit(batch
, (MI_STORE_REGISTER_MEM_GEN8(1) |
1110 MI_SRM_LRM_GLOBAL_GTT
));
1111 wa_ctx_emit(batch
, GEN8_L3SQCREG4
);
1112 wa_ctx_emit(batch
, ring
->scratch
.gtt_offset
+ 256);
1113 wa_ctx_emit(batch
, 0);
1115 wa_ctx_emit(batch
, MI_LOAD_REGISTER_IMM(1));
1116 wa_ctx_emit(batch
, GEN8_L3SQCREG4
);
1117 wa_ctx_emit(batch
, l3sqc4_flush
);
1119 wa_ctx_emit(batch
, GFX_OP_PIPE_CONTROL(6));
1120 wa_ctx_emit(batch
, (PIPE_CONTROL_CS_STALL
|
1121 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1122 wa_ctx_emit(batch
, 0);
1123 wa_ctx_emit(batch
, 0);
1124 wa_ctx_emit(batch
, 0);
1125 wa_ctx_emit(batch
, 0);
1127 wa_ctx_emit(batch
, (MI_LOAD_REGISTER_MEM_GEN8(1) |
1128 MI_SRM_LRM_GLOBAL_GTT
));
1129 wa_ctx_emit(batch
, GEN8_L3SQCREG4
);
1130 wa_ctx_emit(batch
, ring
->scratch
.gtt_offset
+ 256);
1131 wa_ctx_emit(batch
, 0);
1136 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1138 uint32_t start_alignment
)
1140 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1143 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1145 uint32_t size_alignment
)
1147 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1149 WARN(wa_ctx
->size
% size_alignment
,
1150 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1151 wa_ctx
->size
, size_alignment
);
1156 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1158 * @ring: only applicable for RCS
1159 * @wa_ctx: structure representing wa_ctx
1160 * offset: specifies start of the batch, should be cache-aligned. This is updated
1161 * with the offset value received as input.
1162 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1163 * @batch: page in which WA are loaded
1164 * @offset: This field specifies the start of the batch, it should be
1165 * cache-aligned otherwise it is adjusted accordingly.
1166 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1167 * initialized at the beginning and shared across all contexts but this field
1168 * helps us to have multiple batches at different offsets and select them based
1169 * on a criteria. At the moment this batch always start at the beginning of the page
1170 * and at this point we don't have multiple wa_ctx batch buffers.
1172 * The number of WA applied are not known at the beginning; we use this field
1173 * to return the no of DWORDS written.
1175 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1176 * so it adds NOOPs as padding to make it cacheline aligned.
1177 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1178 * makes a complete batch buffer.
1180 * Return: non-zero if we exceed the PAGE_SIZE limit.
1183 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1184 struct i915_wa_ctx_bb
*wa_ctx
,
1185 uint32_t *const batch
,
1188 uint32_t scratch_addr
;
1189 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1191 /* WaDisableCtxRestoreArbitration:bdw,chv */
1192 wa_ctx_emit(batch
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1194 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1195 if (IS_BROADWELL(ring
->dev
)) {
1196 index
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1201 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1202 /* Actual scratch location is at 128 bytes offset */
1203 scratch_addr
= ring
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1205 wa_ctx_emit(batch
, GFX_OP_PIPE_CONTROL(6));
1206 wa_ctx_emit(batch
, (PIPE_CONTROL_FLUSH_L3
|
1207 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1208 PIPE_CONTROL_CS_STALL
|
1209 PIPE_CONTROL_QW_WRITE
));
1210 wa_ctx_emit(batch
, scratch_addr
);
1211 wa_ctx_emit(batch
, 0);
1212 wa_ctx_emit(batch
, 0);
1213 wa_ctx_emit(batch
, 0);
1215 /* Pad to end of cacheline */
1216 while (index
% CACHELINE_DWORDS
)
1217 wa_ctx_emit(batch
, MI_NOOP
);
1220 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1221 * execution depends on the length specified in terms of cache lines
1222 * in the register CTX_RCS_INDIRECT_CTX
1225 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1229 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1231 * @ring: only applicable for RCS
1232 * @wa_ctx: structure representing wa_ctx
1233 * offset: specifies start of the batch, should be cache-aligned.
1234 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1235 * @batch: page in which WA are loaded
1236 * @offset: This field specifies the start of this batch.
1237 * This batch is started immediately after indirect_ctx batch. Since we ensure
1238 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1240 * The number of DWORDS written are returned using this field.
1242 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1243 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1245 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1246 struct i915_wa_ctx_bb
*wa_ctx
,
1247 uint32_t *const batch
,
1250 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1252 /* WaDisableCtxRestoreArbitration:bdw,chv */
1253 wa_ctx_emit(batch
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1255 wa_ctx_emit(batch
, MI_BATCH_BUFFER_END
);
1257 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1260 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1264 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1265 if (!ring
->wa_ctx
.obj
) {
1266 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1270 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1272 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1274 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1281 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1283 if (ring
->wa_ctx
.obj
) {
1284 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1285 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1286 ring
->wa_ctx
.obj
= NULL
;
1290 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1296 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1298 WARN_ON(ring
->id
!= RCS
);
1300 /* update this when WA for higher Gen are added */
1301 if (WARN(INTEL_INFO(ring
->dev
)->gen
> 8,
1302 "WA batch buffer is not initialized for Gen%d\n",
1303 INTEL_INFO(ring
->dev
)->gen
))
1306 /* some WA perform writes to scratch page, ensure it is valid */
1307 if (ring
->scratch
.obj
== NULL
) {
1308 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1312 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1314 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1318 page
= i915_gem_object_get_page(wa_ctx
->obj
, 0);
1319 batch
= kmap_atomic(page
);
1322 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1323 ret
= gen8_init_indirectctx_bb(ring
,
1324 &wa_ctx
->indirect_ctx
,
1330 ret
= gen8_init_perctx_bb(ring
,
1339 kunmap_atomic(batch
);
1341 lrc_destroy_wa_ctx_obj(ring
);
1346 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1348 struct drm_device
*dev
= ring
->dev
;
1349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1351 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1352 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1354 I915_WRITE(RING_MODE_GEN7(ring
),
1355 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1356 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1357 POSTING_READ(RING_MODE_GEN7(ring
));
1358 ring
->next_context_status_buffer
= 0;
1359 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1361 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1366 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1368 struct drm_device
*dev
= ring
->dev
;
1369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1372 ret
= gen8_init_common_ring(ring
);
1376 /* We need to disable the AsyncFlip performance optimisations in order
1377 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1378 * programmed to '1' on all products.
1380 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1382 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1384 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1386 return init_workarounds_ring(ring
);
1389 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1393 ret
= gen8_init_common_ring(ring
);
1397 return init_workarounds_ring(ring
);
1400 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1402 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1403 struct intel_engine_cs
*ring
= req
->ring
;
1404 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1405 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1408 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1412 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1413 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1414 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1416 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_UDW(ring
, i
));
1417 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1418 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_LDW(ring
, i
));
1419 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1422 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1423 intel_logical_ring_advance(ringbuf
);
1428 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1429 u64 offset
, unsigned dispatch_flags
)
1431 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1432 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1435 /* Don't rely in hw updating PDPs, specially in lite-restore.
1436 * Ideally, we should set Force PD Restore in ctx descriptor,
1437 * but we can't. Force Restore would be a second option, but
1438 * it is unsafe in case of lite-restore (because the ctx is
1440 if (req
->ctx
->ppgtt
&&
1441 (intel_ring_flag(req
->ring
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1442 ret
= intel_logical_ring_emit_pdps(req
);
1446 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(req
->ring
);
1449 ret
= intel_logical_ring_begin(req
, 4);
1453 /* FIXME(BDW): Address space and security selectors. */
1454 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1456 (dispatch_flags
& I915_DISPATCH_RS
?
1457 MI_BATCH_RESOURCE_STREAMER
: 0));
1458 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1459 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1460 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1461 intel_logical_ring_advance(ringbuf
);
1466 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1468 struct drm_device
*dev
= ring
->dev
;
1469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1470 unsigned long flags
;
1472 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1475 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1476 if (ring
->irq_refcount
++ == 0) {
1477 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1478 POSTING_READ(RING_IMR(ring
->mmio_base
));
1480 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1485 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1487 struct drm_device
*dev
= ring
->dev
;
1488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 unsigned long flags
;
1491 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1492 if (--ring
->irq_refcount
== 0) {
1493 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1494 POSTING_READ(RING_IMR(ring
->mmio_base
));
1496 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1499 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1500 u32 invalidate_domains
,
1503 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1504 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1505 struct drm_device
*dev
= ring
->dev
;
1506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 ret
= intel_logical_ring_begin(request
, 4);
1514 cmd
= MI_FLUSH_DW
+ 1;
1516 /* We always require a command barrier so that subsequent
1517 * commands, such as breadcrumb interrupts, are strictly ordered
1518 * wrt the contents of the write cache being flushed to memory
1519 * (and thus being coherent from the CPU).
1521 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1523 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1524 cmd
|= MI_INVALIDATE_TLB
;
1525 if (ring
== &dev_priv
->ring
[VCS
])
1526 cmd
|= MI_INVALIDATE_BSD
;
1529 intel_logical_ring_emit(ringbuf
, cmd
);
1530 intel_logical_ring_emit(ringbuf
,
1531 I915_GEM_HWS_SCRATCH_ADDR
|
1532 MI_FLUSH_DW_USE_GTT
);
1533 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1534 intel_logical_ring_emit(ringbuf
, 0); /* value */
1535 intel_logical_ring_advance(ringbuf
);
1540 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1541 u32 invalidate_domains
,
1544 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1545 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1546 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1551 flags
|= PIPE_CONTROL_CS_STALL
;
1553 if (flush_domains
) {
1554 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1555 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1558 if (invalidate_domains
) {
1559 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1560 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1561 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1562 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1563 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1564 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1565 flags
|= PIPE_CONTROL_QW_WRITE
;
1566 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1570 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1573 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1574 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1576 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1581 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1582 intel_logical_ring_emit(ringbuf
, 0);
1583 intel_logical_ring_emit(ringbuf
, 0);
1584 intel_logical_ring_emit(ringbuf
, 0);
1585 intel_logical_ring_emit(ringbuf
, 0);
1586 intel_logical_ring_emit(ringbuf
, 0);
1589 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1590 intel_logical_ring_emit(ringbuf
, flags
);
1591 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1592 intel_logical_ring_emit(ringbuf
, 0);
1593 intel_logical_ring_emit(ringbuf
, 0);
1594 intel_logical_ring_emit(ringbuf
, 0);
1595 intel_logical_ring_advance(ringbuf
);
1600 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1602 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1605 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1607 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1610 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1612 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1613 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1618 * Reserve space for 2 NOOPs at the end of each request to be
1619 * used as a workaround for not being allowed to do lite
1620 * restore with HEAD==TAIL (WaIdleLiteRestore).
1622 ret
= intel_logical_ring_begin(request
, 8);
1626 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1627 cmd
|= MI_GLOBAL_GTT
;
1629 intel_logical_ring_emit(ringbuf
, cmd
);
1630 intel_logical_ring_emit(ringbuf
,
1631 (ring
->status_page
.gfx_addr
+
1632 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1633 intel_logical_ring_emit(ringbuf
, 0);
1634 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1635 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1636 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1637 intel_logical_ring_advance_and_submit(request
);
1640 * Here we add two extra NOOPs as padding to avoid
1641 * lite restore of a context with HEAD==TAIL.
1643 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1644 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1645 intel_logical_ring_advance(ringbuf
);
1650 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1652 struct render_state so
;
1655 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1659 if (so
.rodata
== NULL
)
1662 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1663 I915_DISPATCH_SECURE
);
1667 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1670 i915_gem_render_state_fini(&so
);
1674 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1678 ret
= intel_logical_ring_workarounds_emit(req
);
1682 return intel_lr_context_render_state_init(req
);
1686 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1688 * @ring: Engine Command Streamer.
1691 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1693 struct drm_i915_private
*dev_priv
;
1695 if (!intel_ring_initialized(ring
))
1698 dev_priv
= ring
->dev
->dev_private
;
1700 intel_logical_ring_stop(ring
);
1701 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1704 ring
->cleanup(ring
);
1706 i915_cmd_parser_fini_ring(ring
);
1707 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1709 if (ring
->status_page
.obj
) {
1710 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1711 ring
->status_page
.obj
= NULL
;
1714 lrc_destroy_wa_ctx_obj(ring
);
1717 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1721 /* Intentionally left blank. */
1722 ring
->buffer
= NULL
;
1725 INIT_LIST_HEAD(&ring
->active_list
);
1726 INIT_LIST_HEAD(&ring
->request_list
);
1727 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1728 init_waitqueue_head(&ring
->irq_queue
);
1730 INIT_LIST_HEAD(&ring
->execlist_queue
);
1731 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1732 spin_lock_init(&ring
->execlist_lock
);
1734 ret
= i915_cmd_parser_init_ring(ring
);
1738 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1743 static int logical_render_ring_init(struct drm_device
*dev
)
1745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1746 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1749 ring
->name
= "render ring";
1751 ring
->mmio_base
= RENDER_RING_BASE
;
1752 ring
->irq_enable_mask
=
1753 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1754 ring
->irq_keep_mask
=
1755 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1756 if (HAS_L3_DPF(dev
))
1757 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1759 if (INTEL_INFO(dev
)->gen
>= 9)
1760 ring
->init_hw
= gen9_init_render_ring
;
1762 ring
->init_hw
= gen8_init_render_ring
;
1763 ring
->init_context
= gen8_init_rcs_context
;
1764 ring
->cleanup
= intel_fini_pipe_control
;
1765 ring
->get_seqno
= gen8_get_seqno
;
1766 ring
->set_seqno
= gen8_set_seqno
;
1767 ring
->emit_request
= gen8_emit_request
;
1768 ring
->emit_flush
= gen8_emit_flush_render
;
1769 ring
->irq_get
= gen8_logical_ring_get_irq
;
1770 ring
->irq_put
= gen8_logical_ring_put_irq
;
1771 ring
->emit_bb_start
= gen8_emit_bb_start
;
1775 ret
= intel_init_pipe_control(ring
);
1779 ret
= intel_init_workaround_bb(ring
);
1782 * We continue even if we fail to initialize WA batch
1783 * because we only expect rare glitches but nothing
1784 * critical to prevent us from using GPU
1786 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1790 ret
= logical_ring_init(dev
, ring
);
1792 lrc_destroy_wa_ctx_obj(ring
);
1798 static int logical_bsd_ring_init(struct drm_device
*dev
)
1800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1801 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1803 ring
->name
= "bsd ring";
1805 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1806 ring
->irq_enable_mask
=
1807 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1808 ring
->irq_keep_mask
=
1809 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1811 ring
->init_hw
= gen8_init_common_ring
;
1812 ring
->get_seqno
= gen8_get_seqno
;
1813 ring
->set_seqno
= gen8_set_seqno
;
1814 ring
->emit_request
= gen8_emit_request
;
1815 ring
->emit_flush
= gen8_emit_flush
;
1816 ring
->irq_get
= gen8_logical_ring_get_irq
;
1817 ring
->irq_put
= gen8_logical_ring_put_irq
;
1818 ring
->emit_bb_start
= gen8_emit_bb_start
;
1820 return logical_ring_init(dev
, ring
);
1823 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1826 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1828 ring
->name
= "bds2 ring";
1830 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1831 ring
->irq_enable_mask
=
1832 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1833 ring
->irq_keep_mask
=
1834 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1836 ring
->init_hw
= gen8_init_common_ring
;
1837 ring
->get_seqno
= gen8_get_seqno
;
1838 ring
->set_seqno
= gen8_set_seqno
;
1839 ring
->emit_request
= gen8_emit_request
;
1840 ring
->emit_flush
= gen8_emit_flush
;
1841 ring
->irq_get
= gen8_logical_ring_get_irq
;
1842 ring
->irq_put
= gen8_logical_ring_put_irq
;
1843 ring
->emit_bb_start
= gen8_emit_bb_start
;
1845 return logical_ring_init(dev
, ring
);
1848 static int logical_blt_ring_init(struct drm_device
*dev
)
1850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1851 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1853 ring
->name
= "blitter ring";
1855 ring
->mmio_base
= BLT_RING_BASE
;
1856 ring
->irq_enable_mask
=
1857 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1858 ring
->irq_keep_mask
=
1859 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1861 ring
->init_hw
= gen8_init_common_ring
;
1862 ring
->get_seqno
= gen8_get_seqno
;
1863 ring
->set_seqno
= gen8_set_seqno
;
1864 ring
->emit_request
= gen8_emit_request
;
1865 ring
->emit_flush
= gen8_emit_flush
;
1866 ring
->irq_get
= gen8_logical_ring_get_irq
;
1867 ring
->irq_put
= gen8_logical_ring_put_irq
;
1868 ring
->emit_bb_start
= gen8_emit_bb_start
;
1870 return logical_ring_init(dev
, ring
);
1873 static int logical_vebox_ring_init(struct drm_device
*dev
)
1875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1876 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1878 ring
->name
= "video enhancement ring";
1880 ring
->mmio_base
= VEBOX_RING_BASE
;
1881 ring
->irq_enable_mask
=
1882 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1883 ring
->irq_keep_mask
=
1884 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1886 ring
->init_hw
= gen8_init_common_ring
;
1887 ring
->get_seqno
= gen8_get_seqno
;
1888 ring
->set_seqno
= gen8_set_seqno
;
1889 ring
->emit_request
= gen8_emit_request
;
1890 ring
->emit_flush
= gen8_emit_flush
;
1891 ring
->irq_get
= gen8_logical_ring_get_irq
;
1892 ring
->irq_put
= gen8_logical_ring_put_irq
;
1893 ring
->emit_bb_start
= gen8_emit_bb_start
;
1895 return logical_ring_init(dev
, ring
);
1899 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1902 * This function inits the engines for an Execlists submission style (the equivalent in the
1903 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1904 * those engines that are present in the hardware.
1906 * Return: non-zero if the initialization failed.
1908 int intel_logical_rings_init(struct drm_device
*dev
)
1910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1913 ret
= logical_render_ring_init(dev
);
1918 ret
= logical_bsd_ring_init(dev
);
1920 goto cleanup_render_ring
;
1924 ret
= logical_blt_ring_init(dev
);
1926 goto cleanup_bsd_ring
;
1929 if (HAS_VEBOX(dev
)) {
1930 ret
= logical_vebox_ring_init(dev
);
1932 goto cleanup_blt_ring
;
1935 if (HAS_BSD2(dev
)) {
1936 ret
= logical_bsd2_ring_init(dev
);
1938 goto cleanup_vebox_ring
;
1941 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
1943 goto cleanup_bsd2_ring
;
1948 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
1950 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
1952 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
1954 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
1955 cleanup_render_ring
:
1956 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
1962 make_rpcs(struct drm_device
*dev
)
1967 * No explicit RPCS request is needed to ensure full
1968 * slice/subslice/EU enablement prior to Gen9.
1970 if (INTEL_INFO(dev
)->gen
< 9)
1974 * Starting in Gen9, render power gating can leave
1975 * slice/subslice/EU in a partially enabled state. We
1976 * must make an explicit request through RPCS for full
1979 if (INTEL_INFO(dev
)->has_slice_pg
) {
1980 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1981 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
1982 GEN8_RPCS_S_CNT_SHIFT
;
1983 rpcs
|= GEN8_RPCS_ENABLE
;
1986 if (INTEL_INFO(dev
)->has_subslice_pg
) {
1987 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1988 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
1989 GEN8_RPCS_SS_CNT_SHIFT
;
1990 rpcs
|= GEN8_RPCS_ENABLE
;
1993 if (INTEL_INFO(dev
)->has_eu_pg
) {
1994 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
1995 GEN8_RPCS_EU_MIN_SHIFT
;
1996 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
1997 GEN8_RPCS_EU_MAX_SHIFT
;
1998 rpcs
|= GEN8_RPCS_ENABLE
;
2005 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2006 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
2008 struct drm_device
*dev
= ring
->dev
;
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2012 uint32_t *reg_state
;
2016 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2018 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2020 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2024 ret
= i915_gem_object_get_pages(ctx_obj
);
2026 DRM_DEBUG_DRIVER("Could not get object pages\n");
2030 i915_gem_object_pin_pages(ctx_obj
);
2032 /* The second page of the context object contains some fields which must
2033 * be set up prior to the first execution. */
2034 page
= i915_gem_object_get_page(ctx_obj
, 1);
2035 reg_state
= kmap_atomic(page
);
2037 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2038 * commands followed by (reg, value) pairs. The values we are setting here are
2039 * only for the first context restore: on a subsequent save, the GPU will
2040 * recreate this batchbuffer with new values (including all the missing
2041 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2042 if (ring
->id
== RCS
)
2043 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
2045 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
2046 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
2047 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
2048 reg_state
[CTX_CONTEXT_CONTROL
+1] =
2049 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2050 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2051 CTX_CTRL_RS_CTX_ENABLE
);
2052 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
2053 reg_state
[CTX_RING_HEAD
+1] = 0;
2054 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
2055 reg_state
[CTX_RING_TAIL
+1] = 0;
2056 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
2057 /* Ring buffer start address is not known until the buffer is pinned.
2058 * It is written to the context image in execlists_update_context()
2060 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
2061 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
2062 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
2063 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
2064 reg_state
[CTX_BB_HEAD_U
+1] = 0;
2065 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
2066 reg_state
[CTX_BB_HEAD_L
+1] = 0;
2067 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
2068 reg_state
[CTX_BB_STATE
+1] = (1<<5);
2069 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
2070 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
2071 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
2072 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
2073 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
2074 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
2075 if (ring
->id
== RCS
) {
2076 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
2077 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
2078 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
2079 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
2080 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
2081 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
2082 if (ring
->wa_ctx
.obj
) {
2083 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2084 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2086 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2087 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2088 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2090 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2091 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2093 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2094 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2098 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
2099 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
2100 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
2101 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
2102 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
2103 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
2104 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
2105 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
2106 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
2107 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
2108 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
2109 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
2111 /* With dynamic page allocation, PDPs may not be allocated at this point,
2112 * Point the unallocated PDPs to the scratch page
2114 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2115 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2116 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2117 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2118 if (ring
->id
== RCS
) {
2119 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2120 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
2121 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
2124 kunmap_atomic(reg_state
);
2127 set_page_dirty(page
);
2128 i915_gem_object_unpin_pages(ctx_obj
);
2134 * intel_lr_context_free() - free the LRC specific bits of a context
2135 * @ctx: the LR context to free.
2137 * The real context freeing is done in i915_gem_context_free: this only
2138 * takes care of the bits that are LRC related: the per-engine backing
2139 * objects and the logical ringbuffer.
2141 void intel_lr_context_free(struct intel_context
*ctx
)
2145 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2146 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2149 struct intel_ringbuffer
*ringbuf
=
2150 ctx
->engine
[i
].ringbuf
;
2151 struct intel_engine_cs
*ring
= ringbuf
->ring
;
2153 if (ctx
== ring
->default_context
) {
2154 intel_unpin_ringbuffer_obj(ringbuf
);
2155 i915_gem_object_ggtt_unpin(ctx_obj
);
2157 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
2158 intel_destroy_ringbuffer_obj(ringbuf
);
2160 drm_gem_object_unreference(&ctx_obj
->base
);
2165 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
2169 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2173 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2174 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2176 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2182 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2189 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2190 struct drm_i915_gem_object
*default_ctx_obj
)
2192 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2194 /* The status page is offset 0 from the default context object
2196 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
);
2197 ring
->status_page
.page_addr
=
2198 kmap(sg_page(default_ctx_obj
->pages
->sgl
));
2199 ring
->status_page
.obj
= default_ctx_obj
;
2201 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2202 (u32
)ring
->status_page
.gfx_addr
);
2203 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2207 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2208 * @ctx: LR context to create.
2209 * @ring: engine to be used with the context.
2211 * This function can be called more than once, with different engines, if we plan
2212 * to use the context with them. The context backing objects and the ringbuffers
2213 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2214 * the creation is a deferred call: it's better to make sure first that we need to use
2215 * a given ring with the context.
2217 * Return: non-zero on error.
2219 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
2220 struct intel_engine_cs
*ring
)
2222 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
2223 struct drm_device
*dev
= ring
->dev
;
2224 struct drm_i915_gem_object
*ctx_obj
;
2225 uint32_t context_size
;
2226 struct intel_ringbuffer
*ringbuf
;
2229 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2230 WARN_ON(ctx
->engine
[ring
->id
].state
);
2232 context_size
= round_up(get_lr_context_size(ring
), 4096);
2234 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2236 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2240 if (is_global_default_ctx
) {
2241 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
2243 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2245 drm_gem_object_unreference(&ctx_obj
->base
);
2250 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2252 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2255 goto error_unpin_ctx
;
2258 ringbuf
->ring
= ring
;
2260 ringbuf
->size
= 32 * PAGE_SIZE
;
2261 ringbuf
->effective_size
= ringbuf
->size
;
2264 ringbuf
->last_retired_head
= -1;
2265 intel_ring_update_space(ringbuf
);
2267 if (ringbuf
->obj
== NULL
) {
2268 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
2271 "Failed to allocate ringbuffer obj %s: %d\n",
2273 goto error_free_rbuf
;
2276 if (is_global_default_ctx
) {
2277 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2280 "Failed to pin and map ringbuffer %s: %d\n",
2282 goto error_destroy_rbuf
;
2288 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2290 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2294 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2295 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2297 if (ctx
== ring
->default_context
)
2298 lrc_setup_hardware_status_page(ring
, ctx_obj
);
2299 else if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
2300 if (ring
->init_context
) {
2301 struct drm_i915_gem_request
*req
;
2303 ret
= i915_gem_request_alloc(ring
, ctx
, &req
);
2307 ret
= ring
->init_context(req
);
2309 DRM_ERROR("ring init context: %d\n", ret
);
2310 i915_gem_request_cancel(req
);
2311 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2312 ctx
->engine
[ring
->id
].state
= NULL
;
2316 i915_add_request_no_flush(req
);
2319 ctx
->rcs_initialized
= true;
2325 if (is_global_default_ctx
)
2326 intel_unpin_ringbuffer_obj(ringbuf
);
2328 intel_destroy_ringbuffer_obj(ringbuf
);
2332 if (is_global_default_ctx
)
2333 i915_gem_object_ggtt_unpin(ctx_obj
);
2334 drm_gem_object_unreference(&ctx_obj
->base
);
2338 void intel_lr_context_reset(struct drm_device
*dev
,
2339 struct intel_context
*ctx
)
2341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2342 struct intel_engine_cs
*ring
;
2345 for_each_ring(ring
, dev_priv
, i
) {
2346 struct drm_i915_gem_object
*ctx_obj
=
2347 ctx
->engine
[ring
->id
].state
;
2348 struct intel_ringbuffer
*ringbuf
=
2349 ctx
->engine
[ring
->id
].ringbuf
;
2350 uint32_t *reg_state
;
2356 if (i915_gem_object_get_pages(ctx_obj
)) {
2357 WARN(1, "Failed get_pages for context obj\n");
2360 page
= i915_gem_object_get_page(ctx_obj
, 1);
2361 reg_state
= kmap_atomic(page
);
2363 reg_state
[CTX_RING_HEAD
+1] = 0;
2364 reg_state
[CTX_RING_TAIL
+1] = 0;
2366 kunmap_atomic(reg_state
);