2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
194 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
195 (reg_state)[(pos)+1] = (val); \
198 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
199 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
200 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
201 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
204 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
205 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
206 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
210 ADVANCED_CONTEXT
= 0,
215 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
216 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
217 LEGACY_64B_CONTEXT :\
221 FAULT_AND_HALT
, /* Debug only */
223 FAULT_AND_CONTINUE
/* Unsupported */
225 #define GEN8_CTX_ID_SHIFT 32
226 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
);
229 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
230 struct drm_i915_gem_object
*default_ctx_obj
);
234 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
236 * @enable_execlists: value of i915.enable_execlists module parameter.
238 * Only certain platforms support Execlists (the prerequisites being
239 * support for Logical Ring Contexts and Aliasing PPGTT or better).
241 * Return: 1 if Execlists is supported and has to be enabled.
243 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
245 WARN_ON(i915
.enable_ppgtt
== -1);
247 /* On platforms with execlist available, vGPU will only
248 * support execlist mode, no ring buffer mode.
250 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
253 if (INTEL_INFO(dev
)->gen
>= 9)
256 if (enable_execlists
== 0)
259 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
260 i915
.use_mmio_flip
>= 0)
267 logical_ring_init_platform_invariants(struct intel_engine_cs
*ring
)
269 struct drm_device
*dev
= ring
->dev
;
271 ring
->disable_lite_restore_wa
= (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
272 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) &&
273 (ring
->id
== VCS
|| ring
->id
== VCS2
);
275 ring
->ctx_desc_template
= GEN8_CTX_VALID
;
276 ring
->ctx_desc_template
|= GEN8_CTX_ADDRESSING_MODE(dev
) <<
277 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
279 ring
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
280 ring
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
282 /* TODO: WaDisableLiteRestore when we start using semaphore
283 * signalling between Command Streamers */
284 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
286 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
287 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
288 if (ring
->disable_lite_restore_wa
)
289 ring
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
293 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
294 * descriptor for a pinned context
296 * @ctx: Context to work on
297 * @ring: Engine the descriptor will be used with
299 * The context descriptor encodes various attributes of a context,
300 * including its GTT address and some flags. Because it's fairly
301 * expensive to calculate, we'll just do it once and cache the result,
302 * which remains valid until the context is unpinned.
304 * This is what a descriptor looks like, from LSB to MSB:
305 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
306 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
307 * bits 32-51: ctx ID, a globally unique tag (the LRCA again!)
308 * bits 52-63: reserved, may encode the engine ID (for GuC)
311 intel_lr_context_descriptor_update(struct intel_context
*ctx
,
312 struct intel_engine_cs
*ring
)
316 lrca
= ctx
->engine
[ring
->id
].lrc_vma
->node
.start
+
317 LRC_PPHWSP_PN
* PAGE_SIZE
;
319 desc
= ring
->ctx_desc_template
; /* bits 0-11 */
320 desc
|= lrca
; /* bits 12-31 */
321 desc
|= (lrca
>> PAGE_SHIFT
) << GEN8_CTX_ID_SHIFT
; /* bits 32-51 */
323 ctx
->engine
[ring
->id
].lrc_desc
= desc
;
326 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
327 struct intel_engine_cs
*ring
)
329 return ctx
->engine
[ring
->id
].lrc_desc
;
333 * intel_execlists_ctx_id() - get the Execlists Context ID
334 * @ctx: Context to get the ID for
335 * @ring: Engine to get the ID for
337 * Do not confuse with ctx->id! Unfortunately we have a name overload
338 * here: the old context ID we pass to userspace as a handler so that
339 * they can refer to a context, and the new context ID we pass to the
340 * ELSP so that the GPU can inform us of the context status via
343 * The context ID is a portion of the context descriptor, so we can
344 * just extract the required part from the cached descriptor.
346 * Return: 20-bits globally unique context ID.
348 u32
intel_execlists_ctx_id(struct intel_context
*ctx
,
349 struct intel_engine_cs
*ring
)
351 return intel_lr_context_descriptor(ctx
, ring
) >> GEN8_CTX_ID_SHIFT
;
354 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
355 struct drm_i915_gem_request
*rq1
)
358 struct intel_engine_cs
*ring
= rq0
->ring
;
359 struct drm_device
*dev
= ring
->dev
;
360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
364 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->ring
);
365 rq1
->elsp_submitted
++;
370 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->ring
);
371 rq0
->elsp_submitted
++;
373 /* You must always write both descriptors in the order below. */
374 spin_lock(&dev_priv
->uncore
.lock
);
375 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
376 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[1]));
377 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[1]));
379 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[0]));
380 /* The context is automatically loaded after the following */
381 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[0]));
383 /* ELSP is a wo register, use another nearby reg for posting */
384 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring
));
385 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
386 spin_unlock(&dev_priv
->uncore
.lock
);
389 static int execlists_update_context(struct drm_i915_gem_request
*rq
)
391 struct intel_engine_cs
*ring
= rq
->ring
;
392 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
393 uint32_t *reg_state
= rq
->ctx
->engine
[ring
->id
].lrc_reg_state
;
395 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
396 reg_state
[CTX_RING_BUFFER_START
+1] = rq
->ringbuf
->vma
->node
.start
;
398 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
399 /* True 32b PPGTT with dynamic page allocation: update PDP
400 * registers and point the unallocated PDPs to scratch page.
401 * PML4 is allocated during ppgtt init, so this is not needed
404 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
405 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
406 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
407 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
413 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
414 struct drm_i915_gem_request
*rq1
)
416 execlists_update_context(rq0
);
419 execlists_update_context(rq1
);
421 execlists_elsp_write(rq0
, rq1
);
424 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
426 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
427 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
429 assert_spin_locked(&ring
->execlist_lock
);
432 * If irqs are not active generate a warning as batches that finish
433 * without the irqs may get lost and a GPU Hang may occur.
435 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
437 if (list_empty(&ring
->execlist_queue
))
440 /* Try to read in pairs */
441 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
445 } else if (req0
->ctx
== cursor
->ctx
) {
446 /* Same ctx: ignore first request, as second request
447 * will update tail past first request's workload */
448 cursor
->elsp_submitted
= req0
->elsp_submitted
;
449 list_move_tail(&req0
->execlist_link
,
450 &ring
->execlist_retired_req_list
);
458 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
460 * WaIdleLiteRestore: make sure we never cause a lite
461 * restore with HEAD==TAIL
463 if (req0
->elsp_submitted
) {
465 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
466 * as we resubmit the request. See gen8_emit_request()
467 * for where we prepare the padding after the end of the
470 struct intel_ringbuffer
*ringbuf
;
472 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
474 req0
->tail
&= ringbuf
->size
- 1;
478 WARN_ON(req1
&& req1
->elsp_submitted
);
480 execlists_submit_requests(req0
, req1
);
483 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
486 struct drm_i915_gem_request
*head_req
;
488 assert_spin_locked(&ring
->execlist_lock
);
490 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
491 struct drm_i915_gem_request
,
494 if (head_req
!= NULL
) {
495 if (intel_execlists_ctx_id(head_req
->ctx
, ring
) == request_id
) {
496 WARN(head_req
->elsp_submitted
== 0,
497 "Never submitted head request\n");
499 if (--head_req
->elsp_submitted
<= 0) {
500 list_move_tail(&head_req
->execlist_link
,
501 &ring
->execlist_retired_req_list
);
510 static void get_context_status(struct intel_engine_cs
*ring
,
512 u32
*status
, u32
*context_id
)
514 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
516 if (WARN_ON(read_pointer
>= GEN8_CSB_ENTRIES
))
519 *status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring
, read_pointer
));
520 *context_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring
, read_pointer
));
524 * intel_lrc_irq_handler() - handle Context Switch interrupts
525 * @ring: Engine Command Streamer to handle.
527 * Check the unread Context Status Buffers and manage the submission of new
528 * contexts to the ELSP accordingly.
530 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
532 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
538 u32 submit_contexts
= 0;
540 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
542 read_pointer
= ring
->next_context_status_buffer
;
543 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
544 if (read_pointer
> write_pointer
)
545 write_pointer
+= GEN8_CSB_ENTRIES
;
547 spin_lock(&ring
->execlist_lock
);
549 while (read_pointer
< write_pointer
) {
551 get_context_status(ring
, ++read_pointer
% GEN8_CSB_ENTRIES
,
552 &status
, &status_id
);
554 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
557 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
558 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
559 if (execlists_check_remove_request(ring
, status_id
))
560 WARN(1, "Lite Restored request removed from queue\n");
562 WARN(1, "Preemption without Lite Restore\n");
565 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
566 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
567 if (execlists_check_remove_request(ring
, status_id
))
572 if (ring
->disable_lite_restore_wa
) {
573 /* Prevent a ctx to preempt itself */
574 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) &&
575 (submit_contexts
!= 0))
576 execlists_context_unqueue(ring
);
577 } else if (submit_contexts
!= 0) {
578 execlists_context_unqueue(ring
);
581 spin_unlock(&ring
->execlist_lock
);
583 if (unlikely(submit_contexts
> 2))
584 DRM_ERROR("More than two context complete events?\n");
586 ring
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
588 /* Update the read pointer to the old write pointer. Manual ringbuffer
589 * management ftw </sarcasm> */
590 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
591 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
592 ring
->next_context_status_buffer
<< 8));
595 static int execlists_context_queue(struct drm_i915_gem_request
*request
)
597 struct intel_engine_cs
*ring
= request
->ring
;
598 struct drm_i915_gem_request
*cursor
;
599 int num_elements
= 0;
601 if (request
->ctx
!= request
->i915
->kernel_context
)
602 intel_lr_context_pin(request
);
604 i915_gem_request_reference(request
);
606 spin_lock_irq(&ring
->execlist_lock
);
608 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
609 if (++num_elements
> 2)
612 if (num_elements
> 2) {
613 struct drm_i915_gem_request
*tail_req
;
615 tail_req
= list_last_entry(&ring
->execlist_queue
,
616 struct drm_i915_gem_request
,
619 if (request
->ctx
== tail_req
->ctx
) {
620 WARN(tail_req
->elsp_submitted
!= 0,
621 "More than 2 already-submitted reqs queued\n");
622 list_move_tail(&tail_req
->execlist_link
,
623 &ring
->execlist_retired_req_list
);
627 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
628 if (num_elements
== 0)
629 execlists_context_unqueue(ring
);
631 spin_unlock_irq(&ring
->execlist_lock
);
636 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
638 struct intel_engine_cs
*ring
= req
->ring
;
639 uint32_t flush_domains
;
643 if (ring
->gpu_caches_dirty
)
644 flush_domains
= I915_GEM_GPU_DOMAINS
;
646 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
650 ring
->gpu_caches_dirty
= false;
654 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
655 struct list_head
*vmas
)
657 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
658 struct i915_vma
*vma
;
659 uint32_t flush_domains
= 0;
660 bool flush_chipset
= false;
663 list_for_each_entry(vma
, vmas
, exec_list
) {
664 struct drm_i915_gem_object
*obj
= vma
->obj
;
666 if (obj
->active
& other_rings
) {
667 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
672 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
673 flush_chipset
|= i915_gem_clflush_object(obj
, false);
675 flush_domains
|= obj
->base
.write_domain
;
678 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
681 /* Unconditionally invalidate gpu caches and ensure that we do flush
682 * any residual writes from the previous batch.
684 return logical_ring_invalidate_all_caches(req
);
687 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
691 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
693 if (i915
.enable_guc_submission
) {
695 * Check that the GuC has space for the request before
696 * going any further, as the i915_add_request() call
697 * later on mustn't fail ...
699 struct intel_guc
*guc
= &request
->i915
->guc
;
701 ret
= i915_guc_wq_check_space(guc
->execbuf_client
);
706 if (request
->ctx
!= request
->i915
->kernel_context
)
707 ret
= intel_lr_context_pin(request
);
712 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
715 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
716 struct intel_engine_cs
*ring
= req
->ring
;
717 struct drm_i915_gem_request
*target
;
721 if (intel_ring_space(ringbuf
) >= bytes
)
724 /* The whole point of reserving space is to not wait! */
725 WARN_ON(ringbuf
->reserved_in_use
);
727 list_for_each_entry(target
, &ring
->request_list
, list
) {
729 * The request queue is per-engine, so can contain requests
730 * from multiple ringbuffers. Here, we must ignore any that
731 * aren't from the ringbuffer we're considering.
733 if (target
->ringbuf
!= ringbuf
)
736 /* Would completion of this request free enough space? */
737 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
743 if (WARN_ON(&target
->list
== &ring
->request_list
))
746 ret
= i915_wait_request(target
);
750 ringbuf
->space
= space
;
755 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
756 * @request: Request to advance the logical ringbuffer of.
758 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
759 * really happens during submission is that the context and current tail will be placed
760 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
761 * point, the tail *inside* the context is updated and the ELSP written to.
764 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
766 struct intel_engine_cs
*ring
= request
->ring
;
767 struct drm_i915_private
*dev_priv
= request
->i915
;
769 intel_logical_ring_advance(request
->ringbuf
);
771 request
->tail
= request
->ringbuf
->tail
;
773 if (intel_ring_stopped(ring
))
776 if (dev_priv
->guc
.execbuf_client
)
777 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
779 execlists_context_queue(request
);
782 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
784 uint32_t __iomem
*virt
;
785 int rem
= ringbuf
->size
- ringbuf
->tail
;
787 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
790 iowrite32(MI_NOOP
, virt
++);
793 intel_ring_update_space(ringbuf
);
796 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
798 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
799 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
800 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
801 int ret
, total_bytes
, wait_bytes
= 0;
802 bool need_wrap
= false;
804 if (ringbuf
->reserved_in_use
)
807 total_bytes
= bytes
+ ringbuf
->reserved_size
;
809 if (unlikely(bytes
> remain_usable
)) {
811 * Not enough space for the basic request. So need to flush
812 * out the remainder and then wait for base + reserved.
814 wait_bytes
= remain_actual
+ total_bytes
;
817 if (unlikely(total_bytes
> remain_usable
)) {
819 * The base request will fit but the reserved space
820 * falls off the end. So only need to to wait for the
821 * reserved size after flushing out the remainder.
823 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
825 } else if (total_bytes
> ringbuf
->space
) {
826 /* No wrapping required, just waiting. */
827 wait_bytes
= total_bytes
;
832 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
837 __wrap_ring_buffer(ringbuf
);
844 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
846 * @req: The request to start some new work for
847 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
849 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
850 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
851 * and also preallocates a request (every workload submission is still mediated through
852 * requests, same as it did with legacy ringbuffer submission).
854 * Return: non-zero if the ringbuffer is not ready to be written to.
856 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
858 struct drm_i915_private
*dev_priv
;
861 WARN_ON(req
== NULL
);
862 dev_priv
= req
->ring
->dev
->dev_private
;
864 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
865 dev_priv
->mm
.interruptible
);
869 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
873 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
877 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
880 * The first call merely notes the reserve request and is common for
881 * all back ends. The subsequent localised _begin() call actually
882 * ensures that the reservation is available. Without the begin, if
883 * the request creator immediately submitted the request without
884 * adding any commands to it then there might not actually be
885 * sufficient room for the submission commands.
887 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
889 return intel_logical_ring_begin(request
, 0);
893 * execlists_submission() - submit a batchbuffer for execution, Execlists style
896 * @ring: Engine Command Streamer to submit to.
897 * @ctx: Context to employ for this submission.
898 * @args: execbuffer call arguments.
899 * @vmas: list of vmas.
900 * @batch_obj: the batchbuffer to submit.
901 * @exec_start: batchbuffer start virtual address pointer.
902 * @dispatch_flags: translated execbuffer call flags.
904 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
905 * away the submission details of the execbuffer ioctl call.
907 * Return: non-zero if the submission fails.
909 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
910 struct drm_i915_gem_execbuffer2
*args
,
911 struct list_head
*vmas
)
913 struct drm_device
*dev
= params
->dev
;
914 struct intel_engine_cs
*ring
= params
->ring
;
915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
916 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
922 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
923 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
924 switch (instp_mode
) {
925 case I915_EXEC_CONSTANTS_REL_GENERAL
:
926 case I915_EXEC_CONSTANTS_ABSOLUTE
:
927 case I915_EXEC_CONSTANTS_REL_SURFACE
:
928 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
929 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
933 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
934 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
935 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
939 /* The HW changed the meaning on this bit on gen6 */
940 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
944 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
948 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
949 DRM_DEBUG("sol reset is gen7 only\n");
953 ret
= execlists_move_to_gpu(params
->request
, vmas
);
957 if (ring
== &dev_priv
->ring
[RCS
] &&
958 instp_mode
!= dev_priv
->relative_constants_mode
) {
959 ret
= intel_logical_ring_begin(params
->request
, 4);
963 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
964 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
965 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
966 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
967 intel_logical_ring_advance(ringbuf
);
969 dev_priv
->relative_constants_mode
= instp_mode
;
972 exec_start
= params
->batch_obj_vm_offset
+
973 args
->batch_start_offset
;
975 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
979 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
981 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
982 i915_gem_execbuffer_retire_commands(params
);
987 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
989 struct drm_i915_gem_request
*req
, *tmp
;
990 struct list_head retired_list
;
992 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
993 if (list_empty(&ring
->execlist_retired_req_list
))
996 INIT_LIST_HEAD(&retired_list
);
997 spin_lock_irq(&ring
->execlist_lock
);
998 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
999 spin_unlock_irq(&ring
->execlist_lock
);
1001 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
1002 struct intel_context
*ctx
= req
->ctx
;
1003 struct drm_i915_gem_object
*ctx_obj
=
1004 ctx
->engine
[ring
->id
].state
;
1006 if (ctx_obj
&& (ctx
!= req
->i915
->kernel_context
))
1007 intel_lr_context_unpin(req
);
1008 list_del(&req
->execlist_link
);
1009 i915_gem_request_unreference(req
);
1013 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
1015 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1018 if (!intel_ring_initialized(ring
))
1021 ret
= intel_ring_idle(ring
);
1022 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
1023 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1026 /* TODO: Is this correct with Execlists enabled? */
1027 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
1028 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
1029 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
1032 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
1035 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
1037 struct intel_engine_cs
*ring
= req
->ring
;
1040 if (!ring
->gpu_caches_dirty
)
1043 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
1047 ring
->gpu_caches_dirty
= false;
1051 static int intel_lr_context_do_pin(struct intel_engine_cs
*ring
,
1052 struct intel_context
*ctx
)
1054 struct drm_device
*dev
= ring
->dev
;
1055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1056 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
1057 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1058 struct page
*lrc_state_page
;
1061 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1063 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
1064 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
1068 lrc_state_page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
1069 if (WARN_ON(!lrc_state_page
)) {
1074 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1078 ctx
->engine
[ring
->id
].lrc_vma
= i915_gem_obj_to_ggtt(ctx_obj
);
1079 intel_lr_context_descriptor_update(ctx
, ring
);
1080 ctx
->engine
[ring
->id
].lrc_reg_state
= kmap(lrc_state_page
);
1081 ctx_obj
->dirty
= true;
1083 /* Invalidate GuC TLB. */
1084 if (i915
.enable_guc_submission
)
1085 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1090 i915_gem_object_ggtt_unpin(ctx_obj
);
1095 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
)
1098 struct intel_engine_cs
*ring
= rq
->ring
;
1100 if (rq
->ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1101 ret
= intel_lr_context_do_pin(ring
, rq
->ctx
);
1103 goto reset_pin_count
;
1108 rq
->ctx
->engine
[ring
->id
].pin_count
= 0;
1112 void intel_lr_context_unpin(struct drm_i915_gem_request
*rq
)
1114 struct intel_engine_cs
*ring
= rq
->ring
;
1115 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1116 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1118 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1123 if (--rq
->ctx
->engine
[ring
->id
].pin_count
== 0) {
1124 kunmap(kmap_to_page(rq
->ctx
->engine
[ring
->id
].lrc_reg_state
));
1125 intel_unpin_ringbuffer_obj(ringbuf
);
1126 i915_gem_object_ggtt_unpin(ctx_obj
);
1127 rq
->ctx
->engine
[ring
->id
].lrc_vma
= NULL
;
1128 rq
->ctx
->engine
[ring
->id
].lrc_desc
= 0;
1129 rq
->ctx
->engine
[ring
->id
].lrc_reg_state
= NULL
;
1133 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1136 struct intel_engine_cs
*ring
= req
->ring
;
1137 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1138 struct drm_device
*dev
= ring
->dev
;
1139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1140 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1145 ring
->gpu_caches_dirty
= true;
1146 ret
= logical_ring_flush_all_caches(req
);
1150 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1154 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1155 for (i
= 0; i
< w
->count
; i
++) {
1156 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1157 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1159 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1161 intel_logical_ring_advance(ringbuf
);
1163 ring
->gpu_caches_dirty
= true;
1164 ret
= logical_ring_flush_all_caches(req
);
1171 #define wa_ctx_emit(batch, index, cmd) \
1173 int __index = (index)++; \
1174 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1177 batch[__index] = (cmd); \
1180 #define wa_ctx_emit_reg(batch, index, reg) \
1181 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1184 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1185 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1186 * but there is a slight complication as this is applied in WA batch where the
1187 * values are only initialized once so we cannot take register value at the
1188 * beginning and reuse it further; hence we save its value to memory, upload a
1189 * constant value with bit21 set and then we restore it back with the saved value.
1190 * To simplify the WA, a constant value is formed by using the default value
1191 * of this register. This shouldn't be a problem because we are only modifying
1192 * it for a short period and this batch in non-premptible. We can ofcourse
1193 * use additional instructions that read the actual value of the register
1194 * at that time and set our bit of interest but it makes the WA complicated.
1196 * This WA is also required for Gen9 so extracting as a function avoids
1199 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*ring
,
1200 uint32_t *const batch
,
1203 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1206 * WaDisableLSQCROPERFforOCL:skl
1207 * This WA is implemented in skl_init_clock_gating() but since
1208 * this batch updates GEN8_L3SQCREG4 with default value we need to
1209 * set this bit here to retain the WA during flush.
1211 if (IS_SKL_REVID(ring
->dev
, 0, SKL_REVID_E0
))
1212 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1214 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1215 MI_SRM_LRM_GLOBAL_GTT
));
1216 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1217 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1218 wa_ctx_emit(batch
, index
, 0);
1220 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1221 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1222 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1224 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1225 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1226 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1227 wa_ctx_emit(batch
, index
, 0);
1228 wa_ctx_emit(batch
, index
, 0);
1229 wa_ctx_emit(batch
, index
, 0);
1230 wa_ctx_emit(batch
, index
, 0);
1232 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1233 MI_SRM_LRM_GLOBAL_GTT
));
1234 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1235 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1236 wa_ctx_emit(batch
, index
, 0);
1241 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1243 uint32_t start_alignment
)
1245 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1248 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1250 uint32_t size_alignment
)
1252 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1254 WARN(wa_ctx
->size
% size_alignment
,
1255 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1256 wa_ctx
->size
, size_alignment
);
1261 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1263 * @ring: only applicable for RCS
1264 * @wa_ctx: structure representing wa_ctx
1265 * offset: specifies start of the batch, should be cache-aligned. This is updated
1266 * with the offset value received as input.
1267 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1268 * @batch: page in which WA are loaded
1269 * @offset: This field specifies the start of the batch, it should be
1270 * cache-aligned otherwise it is adjusted accordingly.
1271 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1272 * initialized at the beginning and shared across all contexts but this field
1273 * helps us to have multiple batches at different offsets and select them based
1274 * on a criteria. At the moment this batch always start at the beginning of the page
1275 * and at this point we don't have multiple wa_ctx batch buffers.
1277 * The number of WA applied are not known at the beginning; we use this field
1278 * to return the no of DWORDS written.
1280 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1281 * so it adds NOOPs as padding to make it cacheline aligned.
1282 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1283 * makes a complete batch buffer.
1285 * Return: non-zero if we exceed the PAGE_SIZE limit.
1288 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1289 struct i915_wa_ctx_bb
*wa_ctx
,
1290 uint32_t *const batch
,
1293 uint32_t scratch_addr
;
1294 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1296 /* WaDisableCtxRestoreArbitration:bdw,chv */
1297 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1299 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1300 if (IS_BROADWELL(ring
->dev
)) {
1301 int rc
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1307 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1308 /* Actual scratch location is at 128 bytes offset */
1309 scratch_addr
= ring
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1311 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1312 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1313 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1314 PIPE_CONTROL_CS_STALL
|
1315 PIPE_CONTROL_QW_WRITE
));
1316 wa_ctx_emit(batch
, index
, scratch_addr
);
1317 wa_ctx_emit(batch
, index
, 0);
1318 wa_ctx_emit(batch
, index
, 0);
1319 wa_ctx_emit(batch
, index
, 0);
1321 /* Pad to end of cacheline */
1322 while (index
% CACHELINE_DWORDS
)
1323 wa_ctx_emit(batch
, index
, MI_NOOP
);
1326 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1327 * execution depends on the length specified in terms of cache lines
1328 * in the register CTX_RCS_INDIRECT_CTX
1331 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1335 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1337 * @ring: only applicable for RCS
1338 * @wa_ctx: structure representing wa_ctx
1339 * offset: specifies start of the batch, should be cache-aligned.
1340 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1341 * @batch: page in which WA are loaded
1342 * @offset: This field specifies the start of this batch.
1343 * This batch is started immediately after indirect_ctx batch. Since we ensure
1344 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1346 * The number of DWORDS written are returned using this field.
1348 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1349 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1351 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1352 struct i915_wa_ctx_bb
*wa_ctx
,
1353 uint32_t *const batch
,
1356 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1358 /* WaDisableCtxRestoreArbitration:bdw,chv */
1359 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1361 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1363 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1366 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1367 struct i915_wa_ctx_bb
*wa_ctx
,
1368 uint32_t *const batch
,
1372 struct drm_device
*dev
= ring
->dev
;
1373 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1375 /* WaDisableCtxRestoreArbitration:skl,bxt */
1376 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1377 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1378 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1380 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1381 ret
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1386 /* Pad to end of cacheline */
1387 while (index
% CACHELINE_DWORDS
)
1388 wa_ctx_emit(batch
, index
, MI_NOOP
);
1390 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1393 static int gen9_init_perctx_bb(struct intel_engine_cs
*ring
,
1394 struct i915_wa_ctx_bb
*wa_ctx
,
1395 uint32_t *const batch
,
1398 struct drm_device
*dev
= ring
->dev
;
1399 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1401 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1402 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
1403 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1404 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1405 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1406 wa_ctx_emit(batch
, index
,
1407 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1408 wa_ctx_emit(batch
, index
, MI_NOOP
);
1411 /* WaDisableCtxRestoreArbitration:skl,bxt */
1412 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1413 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1414 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1416 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1418 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1421 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1425 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1426 if (!ring
->wa_ctx
.obj
) {
1427 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1431 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1433 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1435 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1442 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1444 if (ring
->wa_ctx
.obj
) {
1445 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1446 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1447 ring
->wa_ctx
.obj
= NULL
;
1451 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1457 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1459 WARN_ON(ring
->id
!= RCS
);
1461 /* update this when WA for higher Gen are added */
1462 if (INTEL_INFO(ring
->dev
)->gen
> 9) {
1463 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1464 INTEL_INFO(ring
->dev
)->gen
);
1468 /* some WA perform writes to scratch page, ensure it is valid */
1469 if (ring
->scratch
.obj
== NULL
) {
1470 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1474 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1476 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1480 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1481 batch
= kmap_atomic(page
);
1484 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1485 ret
= gen8_init_indirectctx_bb(ring
,
1486 &wa_ctx
->indirect_ctx
,
1492 ret
= gen8_init_perctx_bb(ring
,
1498 } else if (INTEL_INFO(ring
->dev
)->gen
== 9) {
1499 ret
= gen9_init_indirectctx_bb(ring
,
1500 &wa_ctx
->indirect_ctx
,
1506 ret
= gen9_init_perctx_bb(ring
,
1515 kunmap_atomic(batch
);
1517 lrc_destroy_wa_ctx_obj(ring
);
1522 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1524 struct drm_device
*dev
= ring
->dev
;
1525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1526 u8 next_context_status_buffer_hw
;
1528 lrc_setup_hardware_status_page(ring
,
1529 dev_priv
->kernel_context
->engine
[ring
->id
].state
);
1531 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1532 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1534 I915_WRITE(RING_MODE_GEN7(ring
),
1535 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1536 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1537 POSTING_READ(RING_MODE_GEN7(ring
));
1540 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1541 * zero, we need to read the write pointer from hardware and use its
1542 * value because "this register is power context save restored".
1543 * Effectively, these states have been observed:
1545 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1546 * BDW | CSB regs not reset | CSB regs reset |
1547 * CHT | CSB regs not reset | CSB regs not reset |
1551 next_context_status_buffer_hw
=
1552 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(ring
)));
1555 * When the CSB registers are reset (also after power-up / gpu reset),
1556 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1557 * this special case, so the first element read is CSB[0].
1559 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1560 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1562 ring
->next_context_status_buffer
= next_context_status_buffer_hw
;
1563 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1565 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1570 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1572 struct drm_device
*dev
= ring
->dev
;
1573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1576 ret
= gen8_init_common_ring(ring
);
1580 /* We need to disable the AsyncFlip performance optimisations in order
1581 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1582 * programmed to '1' on all products.
1584 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1586 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1588 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1590 return init_workarounds_ring(ring
);
1593 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1597 ret
= gen8_init_common_ring(ring
);
1601 return init_workarounds_ring(ring
);
1604 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1606 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1607 struct intel_engine_cs
*ring
= req
->ring
;
1608 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1609 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1612 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1616 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1617 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1618 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1620 intel_logical_ring_emit_reg(ringbuf
, GEN8_RING_PDP_UDW(ring
, i
));
1621 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1622 intel_logical_ring_emit_reg(ringbuf
, GEN8_RING_PDP_LDW(ring
, i
));
1623 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1626 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1627 intel_logical_ring_advance(ringbuf
);
1632 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1633 u64 offset
, unsigned dispatch_flags
)
1635 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1636 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1639 /* Don't rely in hw updating PDPs, specially in lite-restore.
1640 * Ideally, we should set Force PD Restore in ctx descriptor,
1641 * but we can't. Force Restore would be a second option, but
1642 * it is unsafe in case of lite-restore (because the ctx is
1643 * not idle). PML4 is allocated during ppgtt init so this is
1644 * not needed in 48-bit.*/
1645 if (req
->ctx
->ppgtt
&&
1646 (intel_ring_flag(req
->ring
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1647 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1648 !intel_vgpu_active(req
->i915
->dev
)) {
1649 ret
= intel_logical_ring_emit_pdps(req
);
1654 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(req
->ring
);
1657 ret
= intel_logical_ring_begin(req
, 4);
1661 /* FIXME(BDW): Address space and security selectors. */
1662 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1664 (dispatch_flags
& I915_DISPATCH_RS
?
1665 MI_BATCH_RESOURCE_STREAMER
: 0));
1666 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1667 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1668 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1669 intel_logical_ring_advance(ringbuf
);
1674 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1676 struct drm_device
*dev
= ring
->dev
;
1677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1678 unsigned long flags
;
1680 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1683 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1684 if (ring
->irq_refcount
++ == 0) {
1685 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1686 POSTING_READ(RING_IMR(ring
->mmio_base
));
1688 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1693 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1695 struct drm_device
*dev
= ring
->dev
;
1696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1697 unsigned long flags
;
1699 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1700 if (--ring
->irq_refcount
== 0) {
1701 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1702 POSTING_READ(RING_IMR(ring
->mmio_base
));
1704 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1707 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1708 u32 invalidate_domains
,
1711 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1712 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1713 struct drm_device
*dev
= ring
->dev
;
1714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1718 ret
= intel_logical_ring_begin(request
, 4);
1722 cmd
= MI_FLUSH_DW
+ 1;
1724 /* We always require a command barrier so that subsequent
1725 * commands, such as breadcrumb interrupts, are strictly ordered
1726 * wrt the contents of the write cache being flushed to memory
1727 * (and thus being coherent from the CPU).
1729 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1731 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1732 cmd
|= MI_INVALIDATE_TLB
;
1733 if (ring
== &dev_priv
->ring
[VCS
])
1734 cmd
|= MI_INVALIDATE_BSD
;
1737 intel_logical_ring_emit(ringbuf
, cmd
);
1738 intel_logical_ring_emit(ringbuf
,
1739 I915_GEM_HWS_SCRATCH_ADDR
|
1740 MI_FLUSH_DW_USE_GTT
);
1741 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1742 intel_logical_ring_emit(ringbuf
, 0); /* value */
1743 intel_logical_ring_advance(ringbuf
);
1748 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1749 u32 invalidate_domains
,
1752 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1753 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1754 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1755 bool vf_flush_wa
= false;
1759 flags
|= PIPE_CONTROL_CS_STALL
;
1761 if (flush_domains
) {
1762 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1763 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1764 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1765 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1768 if (invalidate_domains
) {
1769 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1770 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1771 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1772 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1773 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1774 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1775 flags
|= PIPE_CONTROL_QW_WRITE
;
1776 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1779 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1782 if (IS_GEN9(ring
->dev
))
1786 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1791 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1792 intel_logical_ring_emit(ringbuf
, 0);
1793 intel_logical_ring_emit(ringbuf
, 0);
1794 intel_logical_ring_emit(ringbuf
, 0);
1795 intel_logical_ring_emit(ringbuf
, 0);
1796 intel_logical_ring_emit(ringbuf
, 0);
1799 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1800 intel_logical_ring_emit(ringbuf
, flags
);
1801 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1802 intel_logical_ring_emit(ringbuf
, 0);
1803 intel_logical_ring_emit(ringbuf
, 0);
1804 intel_logical_ring_emit(ringbuf
, 0);
1805 intel_logical_ring_advance(ringbuf
);
1810 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1812 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1815 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1817 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1820 static u32
bxt_a_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1824 * On BXT A steppings there is a HW coherency issue whereby the
1825 * MI_STORE_DATA_IMM storing the completed request's seqno
1826 * occasionally doesn't invalidate the CPU cache. Work around this by
1827 * clflushing the corresponding cacheline whenever the caller wants
1828 * the coherency to be guaranteed. Note that this cacheline is known
1829 * to be clean at this point, since we only write it in
1830 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1831 * this clflush in practice becomes an invalidate operation.
1834 if (!lazy_coherency
)
1835 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1837 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1840 static void bxt_a_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1842 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1844 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1845 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1848 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1850 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1851 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1856 * Reserve space for 2 NOOPs at the end of each request to be
1857 * used as a workaround for not being allowed to do lite
1858 * restore with HEAD==TAIL (WaIdleLiteRestore).
1860 ret
= intel_logical_ring_begin(request
, 8);
1864 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1865 cmd
|= MI_GLOBAL_GTT
;
1867 intel_logical_ring_emit(ringbuf
, cmd
);
1868 intel_logical_ring_emit(ringbuf
,
1869 (ring
->status_page
.gfx_addr
+
1870 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1871 intel_logical_ring_emit(ringbuf
, 0);
1872 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1873 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1874 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1875 intel_logical_ring_advance_and_submit(request
);
1878 * Here we add two extra NOOPs as padding to avoid
1879 * lite restore of a context with HEAD==TAIL.
1881 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1882 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1883 intel_logical_ring_advance(ringbuf
);
1888 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1890 struct render_state so
;
1893 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1897 if (so
.rodata
== NULL
)
1900 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1901 I915_DISPATCH_SECURE
);
1905 ret
= req
->ring
->emit_bb_start(req
,
1906 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1907 I915_DISPATCH_SECURE
);
1911 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1914 i915_gem_render_state_fini(&so
);
1918 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1922 ret
= intel_logical_ring_workarounds_emit(req
);
1926 ret
= intel_rcs_context_init_mocs(req
);
1928 * Failing to program the MOCS is non-fatal.The system will not
1929 * run at peak performance. So generate an error and carry on.
1932 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1934 return intel_lr_context_render_state_init(req
);
1938 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1940 * @ring: Engine Command Streamer.
1943 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1945 struct drm_i915_private
*dev_priv
;
1947 if (!intel_ring_initialized(ring
))
1950 dev_priv
= ring
->dev
->dev_private
;
1953 intel_logical_ring_stop(ring
);
1954 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1958 ring
->cleanup(ring
);
1960 i915_cmd_parser_fini_ring(ring
);
1961 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1963 if (ring
->status_page
.obj
) {
1964 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1965 ring
->status_page
.obj
= NULL
;
1968 ring
->disable_lite_restore_wa
= false;
1969 ring
->ctx_desc_template
= 0;
1971 lrc_destroy_wa_ctx_obj(ring
);
1976 logical_ring_default_vfuncs(struct drm_device
*dev
,
1977 struct intel_engine_cs
*ring
)
1979 /* Default vfuncs which can be overriden by each engine. */
1980 ring
->init_hw
= gen8_init_common_ring
;
1981 ring
->emit_request
= gen8_emit_request
;
1982 ring
->emit_flush
= gen8_emit_flush
;
1983 ring
->irq_get
= gen8_logical_ring_get_irq
;
1984 ring
->irq_put
= gen8_logical_ring_put_irq
;
1985 ring
->emit_bb_start
= gen8_emit_bb_start
;
1986 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1987 ring
->get_seqno
= bxt_a_get_seqno
;
1988 ring
->set_seqno
= bxt_a_set_seqno
;
1990 ring
->get_seqno
= gen8_get_seqno
;
1991 ring
->set_seqno
= gen8_set_seqno
;
1996 logical_ring_default_irqs(struct intel_engine_cs
*ring
, unsigned shift
)
1998 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1999 ring
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
2003 logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
2005 struct intel_context
*dctx
= to_i915(dev
)->kernel_context
;
2008 /* Intentionally left blank. */
2009 ring
->buffer
= NULL
;
2012 INIT_LIST_HEAD(&ring
->active_list
);
2013 INIT_LIST_HEAD(&ring
->request_list
);
2014 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
2015 init_waitqueue_head(&ring
->irq_queue
);
2017 INIT_LIST_HEAD(&ring
->buffers
);
2018 INIT_LIST_HEAD(&ring
->execlist_queue
);
2019 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
2020 spin_lock_init(&ring
->execlist_lock
);
2022 logical_ring_init_platform_invariants(ring
);
2024 ret
= i915_cmd_parser_init_ring(ring
);
2028 ret
= intel_lr_context_deferred_alloc(dctx
, ring
);
2032 /* As this is the default context, always pin it */
2033 ret
= intel_lr_context_do_pin(ring
, dctx
);
2036 "Failed to pin and map ringbuffer %s: %d\n",
2044 intel_logical_ring_cleanup(ring
);
2048 static int logical_render_ring_init(struct drm_device
*dev
)
2050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2051 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2054 ring
->name
= "render ring";
2056 ring
->mmio_base
= RENDER_RING_BASE
;
2058 logical_ring_default_irqs(ring
, GEN8_RCS_IRQ_SHIFT
);
2059 if (HAS_L3_DPF(dev
))
2060 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2062 logical_ring_default_vfuncs(dev
, ring
);
2064 /* Override some for render ring. */
2065 if (INTEL_INFO(dev
)->gen
>= 9)
2066 ring
->init_hw
= gen9_init_render_ring
;
2068 ring
->init_hw
= gen8_init_render_ring
;
2069 ring
->init_context
= gen8_init_rcs_context
;
2070 ring
->cleanup
= intel_fini_pipe_control
;
2071 ring
->emit_flush
= gen8_emit_flush_render
;
2075 ret
= intel_init_pipe_control(ring
);
2079 ret
= intel_init_workaround_bb(ring
);
2082 * We continue even if we fail to initialize WA batch
2083 * because we only expect rare glitches but nothing
2084 * critical to prevent us from using GPU
2086 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2090 ret
= logical_ring_init(dev
, ring
);
2092 lrc_destroy_wa_ctx_obj(ring
);
2098 static int logical_bsd_ring_init(struct drm_device
*dev
)
2100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2101 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2103 ring
->name
= "bsd ring";
2105 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2107 logical_ring_default_irqs(ring
, GEN8_VCS1_IRQ_SHIFT
);
2108 logical_ring_default_vfuncs(dev
, ring
);
2110 return logical_ring_init(dev
, ring
);
2113 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2116 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2118 ring
->name
= "bsd2 ring";
2120 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2122 logical_ring_default_irqs(ring
, GEN8_VCS2_IRQ_SHIFT
);
2123 logical_ring_default_vfuncs(dev
, ring
);
2125 return logical_ring_init(dev
, ring
);
2128 static int logical_blt_ring_init(struct drm_device
*dev
)
2130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2131 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2133 ring
->name
= "blitter ring";
2135 ring
->mmio_base
= BLT_RING_BASE
;
2137 logical_ring_default_irqs(ring
, GEN8_BCS_IRQ_SHIFT
);
2138 logical_ring_default_vfuncs(dev
, ring
);
2140 return logical_ring_init(dev
, ring
);
2143 static int logical_vebox_ring_init(struct drm_device
*dev
)
2145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2146 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2148 ring
->name
= "video enhancement ring";
2150 ring
->mmio_base
= VEBOX_RING_BASE
;
2152 logical_ring_default_irqs(ring
, GEN8_VECS_IRQ_SHIFT
);
2153 logical_ring_default_vfuncs(dev
, ring
);
2155 return logical_ring_init(dev
, ring
);
2159 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2162 * This function inits the engines for an Execlists submission style (the equivalent in the
2163 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2164 * those engines that are present in the hardware.
2166 * Return: non-zero if the initialization failed.
2168 int intel_logical_rings_init(struct drm_device
*dev
)
2170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2173 ret
= logical_render_ring_init(dev
);
2178 ret
= logical_bsd_ring_init(dev
);
2180 goto cleanup_render_ring
;
2184 ret
= logical_blt_ring_init(dev
);
2186 goto cleanup_bsd_ring
;
2189 if (HAS_VEBOX(dev
)) {
2190 ret
= logical_vebox_ring_init(dev
);
2192 goto cleanup_blt_ring
;
2195 if (HAS_BSD2(dev
)) {
2196 ret
= logical_bsd2_ring_init(dev
);
2198 goto cleanup_vebox_ring
;
2204 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
2206 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
2208 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
2209 cleanup_render_ring
:
2210 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
2216 make_rpcs(struct drm_device
*dev
)
2221 * No explicit RPCS request is needed to ensure full
2222 * slice/subslice/EU enablement prior to Gen9.
2224 if (INTEL_INFO(dev
)->gen
< 9)
2228 * Starting in Gen9, render power gating can leave
2229 * slice/subslice/EU in a partially enabled state. We
2230 * must make an explicit request through RPCS for full
2233 if (INTEL_INFO(dev
)->has_slice_pg
) {
2234 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2235 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2236 GEN8_RPCS_S_CNT_SHIFT
;
2237 rpcs
|= GEN8_RPCS_ENABLE
;
2240 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2241 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2242 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2243 GEN8_RPCS_SS_CNT_SHIFT
;
2244 rpcs
|= GEN8_RPCS_ENABLE
;
2247 if (INTEL_INFO(dev
)->has_eu_pg
) {
2248 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2249 GEN8_RPCS_EU_MIN_SHIFT
;
2250 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2251 GEN8_RPCS_EU_MAX_SHIFT
;
2252 rpcs
|= GEN8_RPCS_ENABLE
;
2259 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2260 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
2262 struct drm_device
*dev
= ring
->dev
;
2263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2264 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2266 uint32_t *reg_state
;
2270 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2272 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2274 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2278 ret
= i915_gem_object_get_pages(ctx_obj
);
2280 DRM_DEBUG_DRIVER("Could not get object pages\n");
2284 i915_gem_object_pin_pages(ctx_obj
);
2286 /* The second page of the context object contains some fields which must
2287 * be set up prior to the first execution. */
2288 page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
2289 reg_state
= kmap_atomic(page
);
2291 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2292 * commands followed by (reg, value) pairs. The values we are setting here are
2293 * only for the first context restore: on a subsequent save, the GPU will
2294 * recreate this batchbuffer with new values (including all the missing
2295 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2296 reg_state
[CTX_LRI_HEADER_0
] =
2297 MI_LOAD_REGISTER_IMM(ring
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2298 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
, RING_CONTEXT_CONTROL(ring
),
2299 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2300 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2301 CTX_CTRL_RS_CTX_ENABLE
));
2302 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(ring
->mmio_base
), 0);
2303 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(ring
->mmio_base
), 0);
2304 /* Ring buffer start address is not known until the buffer is pinned.
2305 * It is written to the context image in execlists_update_context()
2307 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
, RING_START(ring
->mmio_base
), 0);
2308 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
, RING_CTL(ring
->mmio_base
),
2309 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2310 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
, RING_BBADDR_UDW(ring
->mmio_base
), 0);
2311 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
, RING_BBADDR(ring
->mmio_base
), 0);
2312 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
, RING_BBSTATE(ring
->mmio_base
),
2314 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
, RING_SBBADDR_UDW(ring
->mmio_base
), 0);
2315 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
, RING_SBBADDR(ring
->mmio_base
), 0);
2316 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
, RING_SBBSTATE(ring
->mmio_base
), 0);
2317 if (ring
->id
== RCS
) {
2318 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
, RING_BB_PER_CTX_PTR(ring
->mmio_base
), 0);
2319 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
, RING_INDIRECT_CTX(ring
->mmio_base
), 0);
2320 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
, RING_INDIRECT_CTX_OFFSET(ring
->mmio_base
), 0);
2321 if (ring
->wa_ctx
.obj
) {
2322 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2323 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2325 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2326 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2327 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2329 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2330 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2332 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2333 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2337 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2338 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
, RING_CTX_TIMESTAMP(ring
->mmio_base
), 0);
2339 /* PDP values well be assigned later if needed */
2340 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(ring
, 3), 0);
2341 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(ring
, 3), 0);
2342 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(ring
, 2), 0);
2343 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(ring
, 2), 0);
2344 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(ring
, 1), 0);
2345 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(ring
, 1), 0);
2346 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(ring
, 0), 0);
2347 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(ring
, 0), 0);
2349 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2350 /* 64b PPGTT (48bit canonical)
2351 * PDP0_DESCRIPTOR contains the base address to PML4 and
2352 * other PDP Descriptors are ignored.
2354 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2357 * PDP*_DESCRIPTOR contains the base address of space supported.
2358 * With dynamic page allocation, PDPs may not be allocated at
2359 * this point. Point the unallocated PDPs to the scratch page
2361 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2362 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2363 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2364 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2367 if (ring
->id
== RCS
) {
2368 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2369 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2373 kunmap_atomic(reg_state
);
2374 i915_gem_object_unpin_pages(ctx_obj
);
2380 * intel_lr_context_free() - free the LRC specific bits of a context
2381 * @ctx: the LR context to free.
2383 * The real context freeing is done in i915_gem_context_free: this only
2384 * takes care of the bits that are LRC related: the per-engine backing
2385 * objects and the logical ringbuffer.
2387 void intel_lr_context_free(struct intel_context
*ctx
)
2391 for (i
= I915_NUM_RINGS
; --i
>= 0; ) {
2392 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
2393 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2398 if (ctx
== ctx
->i915
->kernel_context
) {
2399 intel_unpin_ringbuffer_obj(ringbuf
);
2400 i915_gem_object_ggtt_unpin(ctx_obj
);
2403 WARN_ON(ctx
->engine
[i
].pin_count
);
2404 intel_ringbuffer_free(ringbuf
);
2405 drm_gem_object_unreference(&ctx_obj
->base
);
2410 * intel_lr_context_size() - return the size of the context for an engine
2411 * @ring: which engine to find the context size for
2413 * Each engine may require a different amount of space for a context image,
2414 * so when allocating (or copying) an image, this function can be used to
2415 * find the right size for the specific engine.
2417 * Return: size (in bytes) of an engine-specific context image
2419 * Note: this size includes the HWSP, which is part of the context image
2420 * in LRC mode, but does not include the "shared data page" used with
2421 * GuC submission. The caller should account for this if using the GuC.
2423 uint32_t intel_lr_context_size(struct intel_engine_cs
*ring
)
2427 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2431 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2432 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2434 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2440 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2447 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2448 struct drm_i915_gem_object
*default_ctx_obj
)
2450 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2453 /* The HWSP is part of the default context object in LRC mode. */
2454 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
)
2455 + LRC_PPHWSP_PN
* PAGE_SIZE
;
2456 page
= i915_gem_object_get_page(default_ctx_obj
, LRC_PPHWSP_PN
);
2457 ring
->status_page
.page_addr
= kmap(page
);
2458 ring
->status_page
.obj
= default_ctx_obj
;
2460 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2461 (u32
)ring
->status_page
.gfx_addr
);
2462 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2466 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2467 * @ctx: LR context to create.
2468 * @ring: engine to be used with the context.
2470 * This function can be called more than once, with different engines, if we plan
2471 * to use the context with them. The context backing objects and the ringbuffers
2472 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2473 * the creation is a deferred call: it's better to make sure first that we need to use
2474 * a given ring with the context.
2476 * Return: non-zero on error.
2479 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
2480 struct intel_engine_cs
*ring
)
2482 struct drm_device
*dev
= ring
->dev
;
2483 struct drm_i915_gem_object
*ctx_obj
;
2484 uint32_t context_size
;
2485 struct intel_ringbuffer
*ringbuf
;
2488 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2489 WARN_ON(ctx
->engine
[ring
->id
].state
);
2491 context_size
= round_up(intel_lr_context_size(ring
), 4096);
2493 /* One extra page as the sharing data between driver and GuC */
2494 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2496 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2498 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2502 ringbuf
= intel_engine_create_ringbuffer(ring
, 4 * PAGE_SIZE
);
2503 if (IS_ERR(ringbuf
)) {
2504 ret
= PTR_ERR(ringbuf
);
2505 goto error_deref_obj
;
2508 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2510 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2514 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2515 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2517 if (ctx
!= ctx
->i915
->kernel_context
&& ring
->init_context
) {
2518 struct drm_i915_gem_request
*req
;
2520 req
= i915_gem_request_alloc(ring
, ctx
);
2523 DRM_ERROR("ring create req: %d\n", ret
);
2527 ret
= ring
->init_context(req
);
2529 DRM_ERROR("ring init context: %d\n",
2531 i915_gem_request_cancel(req
);
2534 i915_add_request_no_flush(req
);
2539 intel_ringbuffer_free(ringbuf
);
2541 drm_gem_object_unreference(&ctx_obj
->base
);
2542 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2543 ctx
->engine
[ring
->id
].state
= NULL
;
2547 void intel_lr_context_reset(struct drm_device
*dev
,
2548 struct intel_context
*ctx
)
2550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2551 struct intel_engine_cs
*ring
;
2554 for_each_ring(ring
, dev_priv
, i
) {
2555 struct drm_i915_gem_object
*ctx_obj
=
2556 ctx
->engine
[ring
->id
].state
;
2557 struct intel_ringbuffer
*ringbuf
=
2558 ctx
->engine
[ring
->id
].ringbuf
;
2559 uint32_t *reg_state
;
2565 if (i915_gem_object_get_pages(ctx_obj
)) {
2566 WARN(1, "Failed get_pages for context obj\n");
2569 page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
2570 reg_state
= kmap_atomic(page
);
2572 reg_state
[CTX_RING_HEAD
+1] = 0;
2573 reg_state
[CTX_RING_TAIL
+1] = 0;
2575 kunmap_atomic(reg_state
);