2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
193 const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
194 ppgtt->pdp.page_directory[n]->daddr : \
195 ppgtt->scratch_pd->daddr; \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
201 ADVANCED_CONTEXT
= 0,
206 #define GEN8_CTX_MODE_SHIFT 3
209 FAULT_AND_HALT
, /* Debug only */
211 FAULT_AND_CONTINUE
/* Unsupported */
213 #define GEN8_CTX_ID_SHIFT 32
215 static int intel_lr_context_pin(struct intel_engine_cs
*ring
,
216 struct intel_context
*ctx
);
219 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
221 * @enable_execlists: value of i915.enable_execlists module parameter.
223 * Only certain platforms support Execlists (the prerequisites being
224 * support for Logical Ring Contexts and Aliasing PPGTT or better).
226 * Return: 1 if Execlists is supported and has to be enabled.
228 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
230 WARN_ON(i915
.enable_ppgtt
== -1);
232 if (INTEL_INFO(dev
)->gen
>= 9)
235 if (enable_execlists
== 0)
238 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
239 i915
.use_mmio_flip
>= 0)
246 * intel_execlists_ctx_id() - get the Execlists Context ID
247 * @ctx_obj: Logical Ring Context backing object.
249 * Do not confuse with ctx->id! Unfortunately we have a name overload
250 * here: the old context ID we pass to userspace as a handler so that
251 * they can refer to a context, and the new context ID we pass to the
252 * ELSP so that the GPU can inform us of the context status via
255 * Return: 20-bits globally unique context ID.
257 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
259 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
261 /* LRCA is required to be 4K aligned so the more significant 20 bits
262 * are globally unique */
266 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs
*ring
,
267 struct drm_i915_gem_object
*ctx_obj
)
269 struct drm_device
*dev
= ring
->dev
;
271 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
273 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
275 desc
= GEN8_CTX_VALID
;
276 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
277 if (IS_GEN8(ctx_obj
->base
.dev
))
278 desc
|= GEN8_CTX_L3LLC_COHERENT
;
279 desc
|= GEN8_CTX_PRIVILEGE
;
281 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
283 /* TODO: WaDisableLiteRestore when we start using semaphore
284 * signalling between Command Streamers */
285 /* desc |= GEN8_CTX_FORCE_RESTORE; */
287 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 INTEL_REVID(dev
) <= SKL_REVID_B0
&&
290 (ring
->id
== BCS
|| ring
->id
== VCS
||
291 ring
->id
== VECS
|| ring
->id
== VCS2
))
292 desc
|= GEN8_CTX_FORCE_RESTORE
;
297 static void execlists_elsp_write(struct intel_engine_cs
*ring
,
298 struct drm_i915_gem_object
*ctx_obj0
,
299 struct drm_i915_gem_object
*ctx_obj1
)
301 struct drm_device
*dev
= ring
->dev
;
302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 /* XXX: You must always write both descriptors in the order below. */
308 temp
= execlists_ctx_descriptor(ring
, ctx_obj1
);
311 desc
[1] = (u32
)(temp
>> 32);
314 temp
= execlists_ctx_descriptor(ring
, ctx_obj0
);
315 desc
[3] = (u32
)(temp
>> 32);
318 spin_lock(&dev_priv
->uncore
.lock
);
319 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
320 I915_WRITE_FW(RING_ELSP(ring
), desc
[1]);
321 I915_WRITE_FW(RING_ELSP(ring
), desc
[0]);
322 I915_WRITE_FW(RING_ELSP(ring
), desc
[3]);
324 /* The context is automatically loaded after the following */
325 I915_WRITE_FW(RING_ELSP(ring
), desc
[2]);
327 /* ELSP is a wo register, so use another nearby reg for posting instead */
328 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
329 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
330 spin_unlock(&dev_priv
->uncore
.lock
);
333 static int execlists_update_context(struct drm_i915_gem_object
*ctx_obj
,
334 struct drm_i915_gem_object
*ring_obj
,
335 struct i915_hw_ppgtt
*ppgtt
,
341 page
= i915_gem_object_get_page(ctx_obj
, 1);
342 reg_state
= kmap_atomic(page
);
344 reg_state
[CTX_RING_TAIL
+1] = tail
;
345 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(ring_obj
);
347 /* True PPGTT with dynamic page allocation: update PDP registers and
348 * point the unallocated PDPs to the scratch page
351 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
352 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
353 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
354 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
357 kunmap_atomic(reg_state
);
362 static void execlists_submit_contexts(struct intel_engine_cs
*ring
,
363 struct intel_context
*to0
, u32 tail0
,
364 struct intel_context
*to1
, u32 tail1
)
366 struct drm_i915_gem_object
*ctx_obj0
= to0
->engine
[ring
->id
].state
;
367 struct intel_ringbuffer
*ringbuf0
= to0
->engine
[ring
->id
].ringbuf
;
368 struct drm_i915_gem_object
*ctx_obj1
= NULL
;
369 struct intel_ringbuffer
*ringbuf1
= NULL
;
372 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0
));
373 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0
->obj
));
375 execlists_update_context(ctx_obj0
, ringbuf0
->obj
, to0
->ppgtt
, tail0
);
378 ringbuf1
= to1
->engine
[ring
->id
].ringbuf
;
379 ctx_obj1
= to1
->engine
[ring
->id
].state
;
381 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1
));
382 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1
->obj
));
384 execlists_update_context(ctx_obj1
, ringbuf1
->obj
, to1
->ppgtt
, tail1
);
387 execlists_elsp_write(ring
, ctx_obj0
, ctx_obj1
);
390 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
392 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
393 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
395 assert_spin_locked(&ring
->execlist_lock
);
397 if (list_empty(&ring
->execlist_queue
))
400 /* Try to read in pairs */
401 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
405 } else if (req0
->ctx
== cursor
->ctx
) {
406 /* Same ctx: ignore first request, as second request
407 * will update tail past first request's workload */
408 cursor
->elsp_submitted
= req0
->elsp_submitted
;
409 list_del(&req0
->execlist_link
);
410 list_add_tail(&req0
->execlist_link
,
411 &ring
->execlist_retired_req_list
);
419 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
421 * WaIdleLiteRestore: make sure we never cause a lite
422 * restore with HEAD==TAIL
424 if (req0
&& req0
->elsp_submitted
) {
426 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
427 * as we resubmit the request. See gen8_emit_request()
428 * for where we prepare the padding after the end of the
431 struct intel_ringbuffer
*ringbuf
;
433 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
435 req0
->tail
&= ringbuf
->size
- 1;
439 WARN_ON(req1
&& req1
->elsp_submitted
);
441 execlists_submit_contexts(ring
, req0
->ctx
, req0
->tail
,
442 req1
? req1
->ctx
: NULL
,
443 req1
? req1
->tail
: 0);
445 req0
->elsp_submitted
++;
447 req1
->elsp_submitted
++;
450 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
453 struct drm_i915_gem_request
*head_req
;
455 assert_spin_locked(&ring
->execlist_lock
);
457 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
458 struct drm_i915_gem_request
,
461 if (head_req
!= NULL
) {
462 struct drm_i915_gem_object
*ctx_obj
=
463 head_req
->ctx
->engine
[ring
->id
].state
;
464 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
465 WARN(head_req
->elsp_submitted
== 0,
466 "Never submitted head request\n");
468 if (--head_req
->elsp_submitted
<= 0) {
469 list_del(&head_req
->execlist_link
);
470 list_add_tail(&head_req
->execlist_link
,
471 &ring
->execlist_retired_req_list
);
481 * intel_lrc_irq_handler() - handle Context Switch interrupts
482 * @ring: Engine Command Streamer to handle.
484 * Check the unread Context Status Buffers and manage the submission of new
485 * contexts to the ELSP accordingly.
487 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
489 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
495 u32 submit_contexts
= 0;
497 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
499 read_pointer
= ring
->next_context_status_buffer
;
500 write_pointer
= status_pointer
& 0x07;
501 if (read_pointer
> write_pointer
)
504 spin_lock(&ring
->execlist_lock
);
506 while (read_pointer
< write_pointer
) {
508 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
509 (read_pointer
% 6) * 8);
510 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
511 (read_pointer
% 6) * 8 + 4);
513 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
514 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
515 if (execlists_check_remove_request(ring
, status_id
))
516 WARN(1, "Lite Restored request removed from queue\n");
518 WARN(1, "Preemption without Lite Restore\n");
521 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
522 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
523 if (execlists_check_remove_request(ring
, status_id
))
528 if (submit_contexts
!= 0)
529 execlists_context_unqueue(ring
);
531 spin_unlock(&ring
->execlist_lock
);
533 WARN(submit_contexts
> 2, "More than two context complete events?\n");
534 ring
->next_context_status_buffer
= write_pointer
% 6;
536 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
537 ((u32
)ring
->next_context_status_buffer
& 0x07) << 8);
540 static int execlists_context_queue(struct intel_engine_cs
*ring
,
541 struct intel_context
*to
,
543 struct drm_i915_gem_request
*request
)
545 struct drm_i915_gem_request
*cursor
;
546 int num_elements
= 0;
548 if (to
!= ring
->default_context
)
549 intel_lr_context_pin(ring
, to
);
553 * If there isn't a request associated with this submission,
554 * create one as a temporary holder.
556 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
559 request
->ring
= ring
;
561 kref_init(&request
->ref
);
562 i915_gem_context_reference(request
->ctx
);
564 i915_gem_request_reference(request
);
565 WARN_ON(to
!= request
->ctx
);
567 request
->tail
= tail
;
569 spin_lock_irq(&ring
->execlist_lock
);
571 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
572 if (++num_elements
> 2)
575 if (num_elements
> 2) {
576 struct drm_i915_gem_request
*tail_req
;
578 tail_req
= list_last_entry(&ring
->execlist_queue
,
579 struct drm_i915_gem_request
,
582 if (to
== tail_req
->ctx
) {
583 WARN(tail_req
->elsp_submitted
!= 0,
584 "More than 2 already-submitted reqs queued\n");
585 list_del(&tail_req
->execlist_link
);
586 list_add_tail(&tail_req
->execlist_link
,
587 &ring
->execlist_retired_req_list
);
591 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
592 if (num_elements
== 0)
593 execlists_context_unqueue(ring
);
595 spin_unlock_irq(&ring
->execlist_lock
);
600 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer
*ringbuf
,
601 struct intel_context
*ctx
)
603 struct intel_engine_cs
*ring
= ringbuf
->ring
;
604 uint32_t flush_domains
;
608 if (ring
->gpu_caches_dirty
)
609 flush_domains
= I915_GEM_GPU_DOMAINS
;
611 ret
= ring
->emit_flush(ringbuf
, ctx
,
612 I915_GEM_GPU_DOMAINS
, flush_domains
);
616 ring
->gpu_caches_dirty
= false;
620 static int execlists_move_to_gpu(struct intel_ringbuffer
*ringbuf
,
621 struct intel_context
*ctx
,
622 struct list_head
*vmas
)
624 struct intel_engine_cs
*ring
= ringbuf
->ring
;
625 struct i915_vma
*vma
;
626 uint32_t flush_domains
= 0;
627 bool flush_chipset
= false;
630 list_for_each_entry(vma
, vmas
, exec_list
) {
631 struct drm_i915_gem_object
*obj
= vma
->obj
;
633 ret
= i915_gem_object_sync(obj
, ring
);
637 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
638 flush_chipset
|= i915_gem_clflush_object(obj
, false);
640 flush_domains
|= obj
->base
.write_domain
;
643 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
646 /* Unconditionally invalidate gpu caches and ensure that we do flush
647 * any residual writes from the previous batch.
649 return logical_ring_invalidate_all_caches(ringbuf
, ctx
);
652 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
,
653 struct intel_context
*ctx
)
657 if (ctx
!= request
->ring
->default_context
) {
658 ret
= intel_lr_context_pin(request
->ring
, ctx
);
663 request
->ringbuf
= ctx
->engine
[request
->ring
->id
].ringbuf
;
665 i915_gem_context_reference(request
->ctx
);
670 static int logical_ring_wait_for_space(struct intel_ringbuffer
*ringbuf
,
671 struct intel_context
*ctx
,
674 struct intel_engine_cs
*ring
= ringbuf
->ring
;
675 struct drm_i915_gem_request
*request
;
678 if (intel_ring_space(ringbuf
) >= bytes
)
681 list_for_each_entry(request
, &ring
->request_list
, list
) {
683 * The request queue is per-engine, so can contain requests
684 * from multiple ringbuffers. Here, we must ignore any that
685 * aren't from the ringbuffer we're considering.
687 struct intel_context
*ctx
= request
->ctx
;
688 if (ctx
->engine
[ring
->id
].ringbuf
!= ringbuf
)
691 /* Would completion of this request free enough space? */
692 new_space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
694 if (new_space
>= bytes
)
698 if (WARN_ON(&request
->list
== &ring
->request_list
))
701 ret
= i915_wait_request(request
);
705 i915_gem_retire_requests_ring(ring
);
707 WARN_ON(intel_ring_space(ringbuf
) < new_space
);
709 return intel_ring_space(ringbuf
) >= bytes
? 0 : -ENOSPC
;
713 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
714 * @ringbuf: Logical Ringbuffer to advance.
716 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
717 * really happens during submission is that the context and current tail will be placed
718 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
719 * point, the tail *inside* the context is updated and the ELSP written to.
722 intel_logical_ring_advance_and_submit(struct intel_ringbuffer
*ringbuf
,
723 struct intel_context
*ctx
,
724 struct drm_i915_gem_request
*request
)
726 struct intel_engine_cs
*ring
= ringbuf
->ring
;
728 intel_logical_ring_advance(ringbuf
);
730 if (intel_ring_stopped(ring
))
733 execlists_context_queue(ring
, ctx
, ringbuf
->tail
, request
);
736 static int logical_ring_wrap_buffer(struct intel_ringbuffer
*ringbuf
,
737 struct intel_context
*ctx
)
739 uint32_t __iomem
*virt
;
740 int rem
= ringbuf
->size
- ringbuf
->tail
;
742 if (ringbuf
->space
< rem
) {
743 int ret
= logical_ring_wait_for_space(ringbuf
, ctx
, rem
);
749 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
752 iowrite32(MI_NOOP
, virt
++);
755 intel_ring_update_space(ringbuf
);
760 static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf
,
761 struct intel_context
*ctx
, int bytes
)
765 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
766 ret
= logical_ring_wrap_buffer(ringbuf
, ctx
);
771 if (unlikely(ringbuf
->space
< bytes
)) {
772 ret
= logical_ring_wait_for_space(ringbuf
, ctx
, bytes
);
781 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
783 * @ringbuf: Logical ringbuffer.
784 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
786 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
787 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
788 * and also preallocates a request (every workload submission is still mediated through
789 * requests, same as it did with legacy ringbuffer submission).
791 * Return: non-zero if the ringbuffer is not ready to be written to.
793 static int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf
,
794 struct intel_context
*ctx
, int num_dwords
)
796 struct intel_engine_cs
*ring
= ringbuf
->ring
;
797 struct drm_device
*dev
= ring
->dev
;
798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
801 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
802 dev_priv
->mm
.interruptible
);
806 ret
= logical_ring_prepare(ringbuf
, ctx
, num_dwords
* sizeof(uint32_t));
810 /* Preallocate the olr before touching the ring */
811 ret
= i915_gem_request_alloc(ring
, ctx
);
815 ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
820 * execlists_submission() - submit a batchbuffer for execution, Execlists style
823 * @ring: Engine Command Streamer to submit to.
824 * @ctx: Context to employ for this submission.
825 * @args: execbuffer call arguments.
826 * @vmas: list of vmas.
827 * @batch_obj: the batchbuffer to submit.
828 * @exec_start: batchbuffer start virtual address pointer.
829 * @dispatch_flags: translated execbuffer call flags.
831 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
832 * away the submission details of the execbuffer ioctl call.
834 * Return: non-zero if the submission fails.
836 int intel_execlists_submission(struct drm_device
*dev
, struct drm_file
*file
,
837 struct intel_engine_cs
*ring
,
838 struct intel_context
*ctx
,
839 struct drm_i915_gem_execbuffer2
*args
,
840 struct list_head
*vmas
,
841 struct drm_i915_gem_object
*batch_obj
,
842 u64 exec_start
, u32 dispatch_flags
)
844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
845 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
850 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
851 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
852 switch (instp_mode
) {
853 case I915_EXEC_CONSTANTS_REL_GENERAL
:
854 case I915_EXEC_CONSTANTS_ABSOLUTE
:
855 case I915_EXEC_CONSTANTS_REL_SURFACE
:
856 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
857 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
861 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
862 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
863 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
867 /* The HW changed the meaning on this bit on gen6 */
868 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
872 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
876 if (args
->num_cliprects
!= 0) {
877 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
880 if (args
->DR4
== 0xffffffff) {
881 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
885 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
886 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
891 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
892 DRM_DEBUG("sol reset is gen7 only\n");
896 ret
= execlists_move_to_gpu(ringbuf
, ctx
, vmas
);
900 if (ring
== &dev_priv
->ring
[RCS
] &&
901 instp_mode
!= dev_priv
->relative_constants_mode
) {
902 ret
= intel_logical_ring_begin(ringbuf
, ctx
, 4);
906 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
907 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
908 intel_logical_ring_emit(ringbuf
, INSTPM
);
909 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
910 intel_logical_ring_advance(ringbuf
);
912 dev_priv
->relative_constants_mode
= instp_mode
;
915 ret
= ring
->emit_bb_start(ringbuf
, ctx
, exec_start
, dispatch_flags
);
919 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring
), dispatch_flags
);
921 i915_gem_execbuffer_move_to_active(vmas
, ring
);
922 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
927 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
929 struct drm_i915_gem_request
*req
, *tmp
;
930 struct list_head retired_list
;
932 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
933 if (list_empty(&ring
->execlist_retired_req_list
))
936 INIT_LIST_HEAD(&retired_list
);
937 spin_lock_irq(&ring
->execlist_lock
);
938 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
939 spin_unlock_irq(&ring
->execlist_lock
);
941 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
942 struct intel_context
*ctx
= req
->ctx
;
943 struct drm_i915_gem_object
*ctx_obj
=
944 ctx
->engine
[ring
->id
].state
;
946 if (ctx_obj
&& (ctx
!= ring
->default_context
))
947 intel_lr_context_unpin(ring
, ctx
);
948 list_del(&req
->execlist_link
);
949 i915_gem_request_unreference(req
);
953 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
955 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
958 if (!intel_ring_initialized(ring
))
961 ret
= intel_ring_idle(ring
);
962 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
963 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
966 /* TODO: Is this correct with Execlists enabled? */
967 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
968 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
969 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
972 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
975 int logical_ring_flush_all_caches(struct intel_ringbuffer
*ringbuf
,
976 struct intel_context
*ctx
)
978 struct intel_engine_cs
*ring
= ringbuf
->ring
;
981 if (!ring
->gpu_caches_dirty
)
984 ret
= ring
->emit_flush(ringbuf
, ctx
, 0, I915_GEM_GPU_DOMAINS
);
988 ring
->gpu_caches_dirty
= false;
992 static int intel_lr_context_pin(struct intel_engine_cs
*ring
,
993 struct intel_context
*ctx
)
995 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
996 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
999 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1000 if (ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1001 ret
= i915_gem_obj_ggtt_pin(ctx_obj
,
1002 GEN8_LR_CONTEXT_ALIGN
, 0);
1004 goto reset_pin_count
;
1006 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1014 i915_gem_object_ggtt_unpin(ctx_obj
);
1016 ctx
->engine
[ring
->id
].pin_count
= 0;
1021 void intel_lr_context_unpin(struct intel_engine_cs
*ring
,
1022 struct intel_context
*ctx
)
1024 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
1025 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1028 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1029 if (--ctx
->engine
[ring
->id
].pin_count
== 0) {
1030 intel_unpin_ringbuffer_obj(ringbuf
);
1031 i915_gem_object_ggtt_unpin(ctx_obj
);
1036 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs
*ring
,
1037 struct intel_context
*ctx
)
1040 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1041 struct drm_device
*dev
= ring
->dev
;
1042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1043 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1045 if (WARN_ON_ONCE(w
->count
== 0))
1048 ring
->gpu_caches_dirty
= true;
1049 ret
= logical_ring_flush_all_caches(ringbuf
, ctx
);
1053 ret
= intel_logical_ring_begin(ringbuf
, ctx
, w
->count
* 2 + 2);
1057 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1058 for (i
= 0; i
< w
->count
; i
++) {
1059 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1060 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1062 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1064 intel_logical_ring_advance(ringbuf
);
1066 ring
->gpu_caches_dirty
= true;
1067 ret
= logical_ring_flush_all_caches(ringbuf
, ctx
);
1074 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1076 struct drm_device
*dev
= ring
->dev
;
1077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1079 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1080 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1082 I915_WRITE(RING_MODE_GEN7(ring
),
1083 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1084 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1085 POSTING_READ(RING_MODE_GEN7(ring
));
1086 ring
->next_context_status_buffer
= 0;
1087 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1089 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1094 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1096 struct drm_device
*dev
= ring
->dev
;
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1100 ret
= gen8_init_common_ring(ring
);
1104 /* We need to disable the AsyncFlip performance optimisations in order
1105 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1106 * programmed to '1' on all products.
1108 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1110 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1112 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1114 return init_workarounds_ring(ring
);
1117 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1121 ret
= gen8_init_common_ring(ring
);
1125 return init_workarounds_ring(ring
);
1128 static int gen8_emit_bb_start(struct intel_ringbuffer
*ringbuf
,
1129 struct intel_context
*ctx
,
1130 u64 offset
, unsigned dispatch_flags
)
1132 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1135 ret
= intel_logical_ring_begin(ringbuf
, ctx
, 4);
1139 /* FIXME(BDW): Address space and security selectors. */
1140 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
1141 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1142 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1143 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1144 intel_logical_ring_advance(ringbuf
);
1149 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1151 struct drm_device
*dev
= ring
->dev
;
1152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1153 unsigned long flags
;
1155 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1158 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1159 if (ring
->irq_refcount
++ == 0) {
1160 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1161 POSTING_READ(RING_IMR(ring
->mmio_base
));
1163 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1168 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1170 struct drm_device
*dev
= ring
->dev
;
1171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1172 unsigned long flags
;
1174 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1175 if (--ring
->irq_refcount
== 0) {
1176 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1177 POSTING_READ(RING_IMR(ring
->mmio_base
));
1179 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1182 static int gen8_emit_flush(struct intel_ringbuffer
*ringbuf
,
1183 struct intel_context
*ctx
,
1184 u32 invalidate_domains
,
1187 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1188 struct drm_device
*dev
= ring
->dev
;
1189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1193 ret
= intel_logical_ring_begin(ringbuf
, ctx
, 4);
1197 cmd
= MI_FLUSH_DW
+ 1;
1199 /* We always require a command barrier so that subsequent
1200 * commands, such as breadcrumb interrupts, are strictly ordered
1201 * wrt the contents of the write cache being flushed to memory
1202 * (and thus being coherent from the CPU).
1204 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1206 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1207 cmd
|= MI_INVALIDATE_TLB
;
1208 if (ring
== &dev_priv
->ring
[VCS
])
1209 cmd
|= MI_INVALIDATE_BSD
;
1212 intel_logical_ring_emit(ringbuf
, cmd
);
1213 intel_logical_ring_emit(ringbuf
,
1214 I915_GEM_HWS_SCRATCH_ADDR
|
1215 MI_FLUSH_DW_USE_GTT
);
1216 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1217 intel_logical_ring_emit(ringbuf
, 0); /* value */
1218 intel_logical_ring_advance(ringbuf
);
1223 static int gen8_emit_flush_render(struct intel_ringbuffer
*ringbuf
,
1224 struct intel_context
*ctx
,
1225 u32 invalidate_domains
,
1228 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1229 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1234 flags
|= PIPE_CONTROL_CS_STALL
;
1236 if (flush_domains
) {
1237 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1238 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1241 if (invalidate_domains
) {
1242 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1243 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1244 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1245 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1246 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1247 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1248 flags
|= PIPE_CONTROL_QW_WRITE
;
1249 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1253 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1256 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1257 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1259 ret
= intel_logical_ring_begin(ringbuf
, ctx
, vf_flush_wa
? 12 : 6);
1264 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1265 intel_logical_ring_emit(ringbuf
, 0);
1266 intel_logical_ring_emit(ringbuf
, 0);
1267 intel_logical_ring_emit(ringbuf
, 0);
1268 intel_logical_ring_emit(ringbuf
, 0);
1269 intel_logical_ring_emit(ringbuf
, 0);
1272 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1273 intel_logical_ring_emit(ringbuf
, flags
);
1274 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1275 intel_logical_ring_emit(ringbuf
, 0);
1276 intel_logical_ring_emit(ringbuf
, 0);
1277 intel_logical_ring_emit(ringbuf
, 0);
1278 intel_logical_ring_advance(ringbuf
);
1283 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1285 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1288 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1290 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1293 static int gen8_emit_request(struct intel_ringbuffer
*ringbuf
,
1294 struct drm_i915_gem_request
*request
)
1296 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1301 * Reserve space for 2 NOOPs at the end of each request to be
1302 * used as a workaround for not being allowed to do lite
1303 * restore with HEAD==TAIL (WaIdleLiteRestore).
1305 ret
= intel_logical_ring_begin(ringbuf
, request
->ctx
, 8);
1309 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1310 cmd
|= MI_GLOBAL_GTT
;
1312 intel_logical_ring_emit(ringbuf
, cmd
);
1313 intel_logical_ring_emit(ringbuf
,
1314 (ring
->status_page
.gfx_addr
+
1315 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1316 intel_logical_ring_emit(ringbuf
, 0);
1317 intel_logical_ring_emit(ringbuf
,
1318 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1319 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1320 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1321 intel_logical_ring_advance_and_submit(ringbuf
, request
->ctx
, request
);
1324 * Here we add two extra NOOPs as padding to avoid
1325 * lite restore of a context with HEAD==TAIL.
1327 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1328 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1329 intel_logical_ring_advance(ringbuf
);
1334 static int intel_lr_context_render_state_init(struct intel_engine_cs
*ring
,
1335 struct intel_context
*ctx
)
1337 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1338 struct render_state so
;
1339 struct drm_i915_file_private
*file_priv
= ctx
->file_priv
;
1340 struct drm_file
*file
= file_priv
? file_priv
->file
: NULL
;
1343 ret
= i915_gem_render_state_prepare(ring
, &so
);
1347 if (so
.rodata
== NULL
)
1350 ret
= ring
->emit_bb_start(ringbuf
,
1353 I915_DISPATCH_SECURE
);
1357 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), ring
);
1359 ret
= __i915_add_request(ring
, file
, so
.obj
);
1360 /* intel_logical_ring_add_request moves object to inactive if it
1363 i915_gem_render_state_fini(&so
);
1367 static int gen8_init_rcs_context(struct intel_engine_cs
*ring
,
1368 struct intel_context
*ctx
)
1372 ret
= intel_logical_ring_workarounds_emit(ring
, ctx
);
1376 return intel_lr_context_render_state_init(ring
, ctx
);
1380 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1382 * @ring: Engine Command Streamer.
1385 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1387 struct drm_i915_private
*dev_priv
;
1389 if (!intel_ring_initialized(ring
))
1392 dev_priv
= ring
->dev
->dev_private
;
1394 intel_logical_ring_stop(ring
);
1395 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1396 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
1399 ring
->cleanup(ring
);
1401 i915_cmd_parser_fini_ring(ring
);
1402 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1404 if (ring
->status_page
.obj
) {
1405 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1406 ring
->status_page
.obj
= NULL
;
1410 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1414 /* Intentionally left blank. */
1415 ring
->buffer
= NULL
;
1418 INIT_LIST_HEAD(&ring
->active_list
);
1419 INIT_LIST_HEAD(&ring
->request_list
);
1420 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1421 init_waitqueue_head(&ring
->irq_queue
);
1423 INIT_LIST_HEAD(&ring
->execlist_queue
);
1424 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1425 spin_lock_init(&ring
->execlist_lock
);
1427 ret
= i915_cmd_parser_init_ring(ring
);
1431 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1436 static int logical_render_ring_init(struct drm_device
*dev
)
1438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1439 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1442 ring
->name
= "render ring";
1444 ring
->mmio_base
= RENDER_RING_BASE
;
1445 ring
->irq_enable_mask
=
1446 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1447 ring
->irq_keep_mask
=
1448 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1449 if (HAS_L3_DPF(dev
))
1450 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1452 if (INTEL_INFO(dev
)->gen
>= 9)
1453 ring
->init_hw
= gen9_init_render_ring
;
1455 ring
->init_hw
= gen8_init_render_ring
;
1456 ring
->init_context
= gen8_init_rcs_context
;
1457 ring
->cleanup
= intel_fini_pipe_control
;
1458 ring
->get_seqno
= gen8_get_seqno
;
1459 ring
->set_seqno
= gen8_set_seqno
;
1460 ring
->emit_request
= gen8_emit_request
;
1461 ring
->emit_flush
= gen8_emit_flush_render
;
1462 ring
->irq_get
= gen8_logical_ring_get_irq
;
1463 ring
->irq_put
= gen8_logical_ring_put_irq
;
1464 ring
->emit_bb_start
= gen8_emit_bb_start
;
1467 ret
= logical_ring_init(dev
, ring
);
1471 return intel_init_pipe_control(ring
);
1474 static int logical_bsd_ring_init(struct drm_device
*dev
)
1476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1477 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1479 ring
->name
= "bsd ring";
1481 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1482 ring
->irq_enable_mask
=
1483 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1484 ring
->irq_keep_mask
=
1485 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1487 ring
->init_hw
= gen8_init_common_ring
;
1488 ring
->get_seqno
= gen8_get_seqno
;
1489 ring
->set_seqno
= gen8_set_seqno
;
1490 ring
->emit_request
= gen8_emit_request
;
1491 ring
->emit_flush
= gen8_emit_flush
;
1492 ring
->irq_get
= gen8_logical_ring_get_irq
;
1493 ring
->irq_put
= gen8_logical_ring_put_irq
;
1494 ring
->emit_bb_start
= gen8_emit_bb_start
;
1496 return logical_ring_init(dev
, ring
);
1499 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1502 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1504 ring
->name
= "bds2 ring";
1506 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1507 ring
->irq_enable_mask
=
1508 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1509 ring
->irq_keep_mask
=
1510 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1512 ring
->init_hw
= gen8_init_common_ring
;
1513 ring
->get_seqno
= gen8_get_seqno
;
1514 ring
->set_seqno
= gen8_set_seqno
;
1515 ring
->emit_request
= gen8_emit_request
;
1516 ring
->emit_flush
= gen8_emit_flush
;
1517 ring
->irq_get
= gen8_logical_ring_get_irq
;
1518 ring
->irq_put
= gen8_logical_ring_put_irq
;
1519 ring
->emit_bb_start
= gen8_emit_bb_start
;
1521 return logical_ring_init(dev
, ring
);
1524 static int logical_blt_ring_init(struct drm_device
*dev
)
1526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1527 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1529 ring
->name
= "blitter ring";
1531 ring
->mmio_base
= BLT_RING_BASE
;
1532 ring
->irq_enable_mask
=
1533 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1534 ring
->irq_keep_mask
=
1535 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1537 ring
->init_hw
= gen8_init_common_ring
;
1538 ring
->get_seqno
= gen8_get_seqno
;
1539 ring
->set_seqno
= gen8_set_seqno
;
1540 ring
->emit_request
= gen8_emit_request
;
1541 ring
->emit_flush
= gen8_emit_flush
;
1542 ring
->irq_get
= gen8_logical_ring_get_irq
;
1543 ring
->irq_put
= gen8_logical_ring_put_irq
;
1544 ring
->emit_bb_start
= gen8_emit_bb_start
;
1546 return logical_ring_init(dev
, ring
);
1549 static int logical_vebox_ring_init(struct drm_device
*dev
)
1551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1552 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1554 ring
->name
= "video enhancement ring";
1556 ring
->mmio_base
= VEBOX_RING_BASE
;
1557 ring
->irq_enable_mask
=
1558 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1559 ring
->irq_keep_mask
=
1560 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1562 ring
->init_hw
= gen8_init_common_ring
;
1563 ring
->get_seqno
= gen8_get_seqno
;
1564 ring
->set_seqno
= gen8_set_seqno
;
1565 ring
->emit_request
= gen8_emit_request
;
1566 ring
->emit_flush
= gen8_emit_flush
;
1567 ring
->irq_get
= gen8_logical_ring_get_irq
;
1568 ring
->irq_put
= gen8_logical_ring_put_irq
;
1569 ring
->emit_bb_start
= gen8_emit_bb_start
;
1571 return logical_ring_init(dev
, ring
);
1575 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1578 * This function inits the engines for an Execlists submission style (the equivalent in the
1579 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1580 * those engines that are present in the hardware.
1582 * Return: non-zero if the initialization failed.
1584 int intel_logical_rings_init(struct drm_device
*dev
)
1586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1589 ret
= logical_render_ring_init(dev
);
1594 ret
= logical_bsd_ring_init(dev
);
1596 goto cleanup_render_ring
;
1600 ret
= logical_blt_ring_init(dev
);
1602 goto cleanup_bsd_ring
;
1605 if (HAS_VEBOX(dev
)) {
1606 ret
= logical_vebox_ring_init(dev
);
1608 goto cleanup_blt_ring
;
1611 if (HAS_BSD2(dev
)) {
1612 ret
= logical_bsd2_ring_init(dev
);
1614 goto cleanup_vebox_ring
;
1617 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
1619 goto cleanup_bsd2_ring
;
1624 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
1626 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
1628 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
1630 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
1631 cleanup_render_ring
:
1632 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
1638 make_rpcs(struct drm_device
*dev
)
1643 * No explicit RPCS request is needed to ensure full
1644 * slice/subslice/EU enablement prior to Gen9.
1646 if (INTEL_INFO(dev
)->gen
< 9)
1650 * Starting in Gen9, render power gating can leave
1651 * slice/subslice/EU in a partially enabled state. We
1652 * must make an explicit request through RPCS for full
1655 if (INTEL_INFO(dev
)->has_slice_pg
) {
1656 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1657 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
1658 GEN8_RPCS_S_CNT_SHIFT
;
1659 rpcs
|= GEN8_RPCS_ENABLE
;
1662 if (INTEL_INFO(dev
)->has_subslice_pg
) {
1663 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1664 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
1665 GEN8_RPCS_SS_CNT_SHIFT
;
1666 rpcs
|= GEN8_RPCS_ENABLE
;
1669 if (INTEL_INFO(dev
)->has_eu_pg
) {
1670 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
1671 GEN8_RPCS_EU_MIN_SHIFT
;
1672 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
1673 GEN8_RPCS_EU_MAX_SHIFT
;
1674 rpcs
|= GEN8_RPCS_ENABLE
;
1681 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
1682 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
1684 struct drm_device
*dev
= ring
->dev
;
1685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1686 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1688 uint32_t *reg_state
;
1692 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1694 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1696 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1700 ret
= i915_gem_object_get_pages(ctx_obj
);
1702 DRM_DEBUG_DRIVER("Could not get object pages\n");
1706 i915_gem_object_pin_pages(ctx_obj
);
1708 /* The second page of the context object contains some fields which must
1709 * be set up prior to the first execution. */
1710 page
= i915_gem_object_get_page(ctx_obj
, 1);
1711 reg_state
= kmap_atomic(page
);
1713 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1714 * commands followed by (reg, value) pairs. The values we are setting here are
1715 * only for the first context restore: on a subsequent save, the GPU will
1716 * recreate this batchbuffer with new values (including all the missing
1717 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1718 if (ring
->id
== RCS
)
1719 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
1721 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
1722 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
1723 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
1724 reg_state
[CTX_CONTEXT_CONTROL
+1] =
1725 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
1726 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
);
1727 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
1728 reg_state
[CTX_RING_HEAD
+1] = 0;
1729 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
1730 reg_state
[CTX_RING_TAIL
+1] = 0;
1731 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
1732 /* Ring buffer start address is not known until the buffer is pinned.
1733 * It is written to the context image in execlists_update_context()
1735 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
1736 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
1737 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
1738 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
1739 reg_state
[CTX_BB_HEAD_U
+1] = 0;
1740 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
1741 reg_state
[CTX_BB_HEAD_L
+1] = 0;
1742 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
1743 reg_state
[CTX_BB_STATE
+1] = (1<<5);
1744 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
1745 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
1746 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
1747 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
1748 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
1749 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
1750 if (ring
->id
== RCS
) {
1751 /* TODO: according to BSpec, the register state context
1752 * for CHV does not have these. OTOH, these registers do
1753 * exist in CHV. I'm waiting for a clarification */
1754 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
1755 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
1756 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
1757 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
1758 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
1759 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
1761 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
1762 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
1763 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
1764 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
1765 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
1766 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
1767 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
1768 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
1769 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
1770 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
1771 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
1772 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
1774 /* With dynamic page allocation, PDPs may not be allocated at this point,
1775 * Point the unallocated PDPs to the scratch page
1777 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
1778 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
1779 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
1780 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
1781 if (ring
->id
== RCS
) {
1782 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
1783 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
1784 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
1787 kunmap_atomic(reg_state
);
1790 set_page_dirty(page
);
1791 i915_gem_object_unpin_pages(ctx_obj
);
1797 * intel_lr_context_free() - free the LRC specific bits of a context
1798 * @ctx: the LR context to free.
1800 * The real context freeing is done in i915_gem_context_free: this only
1801 * takes care of the bits that are LRC related: the per-engine backing
1802 * objects and the logical ringbuffer.
1804 void intel_lr_context_free(struct intel_context
*ctx
)
1808 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1809 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
1812 struct intel_ringbuffer
*ringbuf
=
1813 ctx
->engine
[i
].ringbuf
;
1814 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1816 if (ctx
== ring
->default_context
) {
1817 intel_unpin_ringbuffer_obj(ringbuf
);
1818 i915_gem_object_ggtt_unpin(ctx_obj
);
1820 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
1821 intel_destroy_ringbuffer_obj(ringbuf
);
1823 drm_gem_object_unreference(&ctx_obj
->base
);
1828 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
1832 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
1836 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
1837 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
1839 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
1845 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
1852 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
1853 struct drm_i915_gem_object
*default_ctx_obj
)
1855 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1857 /* The status page is offset 0 from the default context object
1859 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
);
1860 ring
->status_page
.page_addr
=
1861 kmap(sg_page(default_ctx_obj
->pages
->sgl
));
1862 ring
->status_page
.obj
= default_ctx_obj
;
1864 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1865 (u32
)ring
->status_page
.gfx_addr
);
1866 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1870 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1871 * @ctx: LR context to create.
1872 * @ring: engine to be used with the context.
1874 * This function can be called more than once, with different engines, if we plan
1875 * to use the context with them. The context backing objects and the ringbuffers
1876 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1877 * the creation is a deferred call: it's better to make sure first that we need to use
1878 * a given ring with the context.
1880 * Return: non-zero on error.
1882 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
1883 struct intel_engine_cs
*ring
)
1885 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
1886 struct drm_device
*dev
= ring
->dev
;
1887 struct drm_i915_gem_object
*ctx_obj
;
1888 uint32_t context_size
;
1889 struct intel_ringbuffer
*ringbuf
;
1892 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
1893 WARN_ON(ctx
->engine
[ring
->id
].state
);
1895 context_size
= round_up(get_lr_context_size(ring
), 4096);
1897 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
1898 if (IS_ERR(ctx_obj
)) {
1899 ret
= PTR_ERR(ctx_obj
);
1900 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret
);
1904 if (is_global_default_ctx
) {
1905 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
1907 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1909 drm_gem_object_unreference(&ctx_obj
->base
);
1914 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1916 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1919 goto error_unpin_ctx
;
1922 ringbuf
->ring
= ring
;
1924 ringbuf
->size
= 32 * PAGE_SIZE
;
1925 ringbuf
->effective_size
= ringbuf
->size
;
1928 ringbuf
->last_retired_head
= -1;
1929 intel_ring_update_space(ringbuf
);
1931 if (ringbuf
->obj
== NULL
) {
1932 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1935 "Failed to allocate ringbuffer obj %s: %d\n",
1937 goto error_free_rbuf
;
1940 if (is_global_default_ctx
) {
1941 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
1944 "Failed to pin and map ringbuffer %s: %d\n",
1946 goto error_destroy_rbuf
;
1952 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
1954 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
1958 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
1959 ctx
->engine
[ring
->id
].state
= ctx_obj
;
1961 if (ctx
== ring
->default_context
)
1962 lrc_setup_hardware_status_page(ring
, ctx_obj
);
1963 else if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
1964 if (ring
->init_context
) {
1965 ret
= ring
->init_context(ring
, ctx
);
1967 DRM_ERROR("ring init context: %d\n", ret
);
1968 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
1969 ctx
->engine
[ring
->id
].state
= NULL
;
1974 ctx
->rcs_initialized
= true;
1980 if (is_global_default_ctx
)
1981 intel_unpin_ringbuffer_obj(ringbuf
);
1983 intel_destroy_ringbuffer_obj(ringbuf
);
1987 if (is_global_default_ctx
)
1988 i915_gem_object_ggtt_unpin(ctx_obj
);
1989 drm_gem_object_unreference(&ctx_obj
->base
);
1993 void intel_lr_context_reset(struct drm_device
*dev
,
1994 struct intel_context
*ctx
)
1996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1997 struct intel_engine_cs
*ring
;
2000 for_each_ring(ring
, dev_priv
, i
) {
2001 struct drm_i915_gem_object
*ctx_obj
=
2002 ctx
->engine
[ring
->id
].state
;
2003 struct intel_ringbuffer
*ringbuf
=
2004 ctx
->engine
[ring
->id
].ringbuf
;
2005 uint32_t *reg_state
;
2011 if (i915_gem_object_get_pages(ctx_obj
)) {
2012 WARN(1, "Failed get_pages for context obj\n");
2015 page
= i915_gem_object_get_page(ctx_obj
, 1);
2016 reg_state
= kmap_atomic(page
);
2018 reg_state
[CTX_RING_HEAD
+1] = 0;
2019 reg_state
[CTX_RING_TAIL
+1] = 0;
2021 kunmap_atomic(reg_state
);