drm/i915: Trivial sparse fixes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
30 #include <acpi/button.h>
31 #include <linux/dmi.h>
32 #include <linux/i2c.h>
33 #include <linux/slab.h>
34 #include "drmP.h"
35 #include "drm.h"
36 #include "drm_crtc.h"
37 #include "drm_edid.h"
38 #include "intel_drv.h"
39 #include "i915_drm.h"
40 #include "i915_drv.h"
41 #include <linux/acpi.h>
42
43 /* Private structure for the integrated LVDS support */
44 struct intel_lvds {
45 struct intel_encoder base;
46
47 struct edid *edid;
48
49 int fitting_mode;
50 u32 pfit_control;
51 u32 pfit_pgm_ratios;
52 bool pfit_dirty;
53
54 struct drm_display_mode *fixed_mode;
55 };
56
57 static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder)
58 {
59 return container_of(encoder, struct intel_lvds, base.base);
60 }
61
62 static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector)
63 {
64 return container_of(intel_attached_encoder(connector),
65 struct intel_lvds, base);
66 }
67
68 /**
69 * Sets the power state for the panel.
70 */
71 static void intel_lvds_enable(struct intel_lvds *intel_lvds)
72 {
73 struct drm_device *dev = intel_lvds->base.base.dev;
74 struct drm_i915_private *dev_priv = dev->dev_private;
75 u32 ctl_reg, lvds_reg;
76
77 if (HAS_PCH_SPLIT(dev)) {
78 ctl_reg = PCH_PP_CONTROL;
79 lvds_reg = PCH_LVDS;
80 } else {
81 ctl_reg = PP_CONTROL;
82 lvds_reg = LVDS;
83 }
84
85 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
86
87 if (intel_lvds->pfit_dirty) {
88 /*
89 * Enable automatic panel scaling so that non-native modes
90 * fill the screen. The panel fitter should only be
91 * adjusted whilst the pipe is disabled, according to
92 * register description and PRM.
93 */
94 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
95 intel_lvds->pfit_control,
96 intel_lvds->pfit_pgm_ratios);
97 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) {
98 DRM_ERROR("timed out waiting for panel to power off\n");
99 } else {
100 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
101 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
102 intel_lvds->pfit_dirty = false;
103 }
104 }
105
106 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
107 POSTING_READ(lvds_reg);
108
109 intel_panel_enable_backlight(dev);
110 }
111
112 static void intel_lvds_disable(struct intel_lvds *intel_lvds)
113 {
114 struct drm_device *dev = intel_lvds->base.base.dev;
115 struct drm_i915_private *dev_priv = dev->dev_private;
116 u32 ctl_reg, lvds_reg;
117
118 if (HAS_PCH_SPLIT(dev)) {
119 ctl_reg = PCH_PP_CONTROL;
120 lvds_reg = PCH_LVDS;
121 } else {
122 ctl_reg = PP_CONTROL;
123 lvds_reg = LVDS;
124 }
125
126 intel_panel_disable_backlight(dev);
127
128 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
129
130 if (intel_lvds->pfit_control) {
131 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000))
132 DRM_ERROR("timed out waiting for panel to power off\n");
133
134 I915_WRITE(PFIT_CONTROL, 0);
135 intel_lvds->pfit_dirty = true;
136 }
137
138 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
139 POSTING_READ(lvds_reg);
140 }
141
142 static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
143 {
144 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
145
146 if (mode == DRM_MODE_DPMS_ON)
147 intel_lvds_enable(intel_lvds);
148 else
149 intel_lvds_disable(intel_lvds);
150
151 /* XXX: We never power down the LVDS pairs. */
152 }
153
154 static int intel_lvds_mode_valid(struct drm_connector *connector,
155 struct drm_display_mode *mode)
156 {
157 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
158 struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode;
159
160 if (mode->hdisplay > fixed_mode->hdisplay)
161 return MODE_PANEL;
162 if (mode->vdisplay > fixed_mode->vdisplay)
163 return MODE_PANEL;
164
165 return MODE_OK;
166 }
167
168 static void
169 centre_horizontally(struct drm_display_mode *mode,
170 int width)
171 {
172 u32 border, sync_pos, blank_width, sync_width;
173
174 /* keep the hsync and hblank widths constant */
175 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
176 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
177 sync_pos = (blank_width - sync_width + 1) / 2;
178
179 border = (mode->hdisplay - width + 1) / 2;
180 border += border & 1; /* make the border even */
181
182 mode->crtc_hdisplay = width;
183 mode->crtc_hblank_start = width + border;
184 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
185
186 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
187 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
188 }
189
190 static void
191 centre_vertically(struct drm_display_mode *mode,
192 int height)
193 {
194 u32 border, sync_pos, blank_width, sync_width;
195
196 /* keep the vsync and vblank widths constant */
197 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
198 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
199 sync_pos = (blank_width - sync_width + 1) / 2;
200
201 border = (mode->vdisplay - height + 1) / 2;
202
203 mode->crtc_vdisplay = height;
204 mode->crtc_vblank_start = height + border;
205 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
206
207 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
208 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
209 }
210
211 static inline u32 panel_fitter_scaling(u32 source, u32 target)
212 {
213 /*
214 * Floating point operation is not supported. So the FACTOR
215 * is defined, which can avoid the floating point computation
216 * when calculating the panel ratio.
217 */
218 #define ACCURACY 12
219 #define FACTOR (1 << ACCURACY)
220 u32 ratio = source * FACTOR / target;
221 return (FACTOR * ratio + FACTOR/2) / FACTOR;
222 }
223
224 static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
225 struct drm_display_mode *mode,
226 struct drm_display_mode *adjusted_mode)
227 {
228 struct drm_device *dev = encoder->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
231 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
232 struct drm_encoder *tmp_encoder;
233 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
234
235 /* Should never happen!! */
236 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
237 DRM_ERROR("Can't support LVDS on pipe A\n");
238 return false;
239 }
240
241 /* Should never happen!! */
242 list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) {
243 if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) {
244 DRM_ERROR("Can't enable LVDS and another "
245 "encoder on the same pipe\n");
246 return false;
247 }
248 }
249
250 /*
251 * We have timings from the BIOS for the panel, put them in
252 * to the adjusted mode. The CRTC will be set up for this mode,
253 * with the panel scaling set up to source from the H/VDisplay
254 * of the original mode.
255 */
256 intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode);
257
258 if (HAS_PCH_SPLIT(dev)) {
259 intel_pch_panel_fitting(dev, intel_lvds->fitting_mode,
260 mode, adjusted_mode);
261 return true;
262 }
263
264 /* Make sure pre-965s set dither correctly */
265 if (INTEL_INFO(dev)->gen < 4) {
266 if (dev_priv->lvds_dither)
267 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
268 }
269
270 /* Native modes don't need fitting */
271 if (adjusted_mode->hdisplay == mode->hdisplay &&
272 adjusted_mode->vdisplay == mode->vdisplay)
273 goto out;
274
275 /* 965+ wants fuzzy fitting */
276 if (INTEL_INFO(dev)->gen >= 4)
277 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
278 PFIT_FILTER_FUZZY);
279
280 /*
281 * Enable automatic panel scaling for non-native modes so that they fill
282 * the screen. Should be enabled before the pipe is enabled, according
283 * to register description and PRM.
284 * Change the value here to see the borders for debugging
285 */
286 I915_WRITE(BCLRPAT_A, 0);
287 I915_WRITE(BCLRPAT_B, 0);
288
289 switch (intel_lvds->fitting_mode) {
290 case DRM_MODE_SCALE_CENTER:
291 /*
292 * For centered modes, we have to calculate border widths &
293 * heights and modify the values programmed into the CRTC.
294 */
295 centre_horizontally(adjusted_mode, mode->hdisplay);
296 centre_vertically(adjusted_mode, mode->vdisplay);
297 border = LVDS_BORDER_ENABLE;
298 break;
299
300 case DRM_MODE_SCALE_ASPECT:
301 /* Scale but preserve the aspect ratio */
302 if (INTEL_INFO(dev)->gen >= 4) {
303 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
304 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
305
306 /* 965+ is easy, it does everything in hw */
307 if (scaled_width > scaled_height)
308 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
309 else if (scaled_width < scaled_height)
310 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
311 else if (adjusted_mode->hdisplay != mode->hdisplay)
312 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
313 } else {
314 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
315 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
316 /*
317 * For earlier chips we have to calculate the scaling
318 * ratio by hand and program it into the
319 * PFIT_PGM_RATIO register
320 */
321 if (scaled_width > scaled_height) { /* pillar */
322 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
323
324 border = LVDS_BORDER_ENABLE;
325 if (mode->vdisplay != adjusted_mode->vdisplay) {
326 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
327 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
328 bits << PFIT_VERT_SCALE_SHIFT);
329 pfit_control |= (PFIT_ENABLE |
330 VERT_INTERP_BILINEAR |
331 HORIZ_INTERP_BILINEAR);
332 }
333 } else if (scaled_width < scaled_height) { /* letter */
334 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
335
336 border = LVDS_BORDER_ENABLE;
337 if (mode->hdisplay != adjusted_mode->hdisplay) {
338 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
339 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
340 bits << PFIT_VERT_SCALE_SHIFT);
341 pfit_control |= (PFIT_ENABLE |
342 VERT_INTERP_BILINEAR |
343 HORIZ_INTERP_BILINEAR);
344 }
345 } else
346 /* Aspects match, Let hw scale both directions */
347 pfit_control |= (PFIT_ENABLE |
348 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
349 VERT_INTERP_BILINEAR |
350 HORIZ_INTERP_BILINEAR);
351 }
352 break;
353
354 case DRM_MODE_SCALE_FULLSCREEN:
355 /*
356 * Full scaling, even if it changes the aspect ratio.
357 * Fortunately this is all done for us in hw.
358 */
359 if (mode->vdisplay != adjusted_mode->vdisplay ||
360 mode->hdisplay != adjusted_mode->hdisplay) {
361 pfit_control |= PFIT_ENABLE;
362 if (INTEL_INFO(dev)->gen >= 4)
363 pfit_control |= PFIT_SCALING_AUTO;
364 else
365 pfit_control |= (VERT_AUTO_SCALE |
366 VERT_INTERP_BILINEAR |
367 HORIZ_AUTO_SCALE |
368 HORIZ_INTERP_BILINEAR);
369 }
370 break;
371
372 default:
373 break;
374 }
375
376 out:
377 if ((pfit_control & PFIT_ENABLE) == 0) {
378 pfit_control = 0;
379 pfit_pgm_ratios = 0;
380 }
381 if (pfit_control != intel_lvds->pfit_control ||
382 pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) {
383 intel_lvds->pfit_control = pfit_control;
384 intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios;
385 intel_lvds->pfit_dirty = true;
386 }
387 dev_priv->lvds_border_bits = border;
388
389 /*
390 * XXX: It would be nice to support lower refresh rates on the
391 * panels to reduce power consumption, and perhaps match the
392 * user's requested refresh rate.
393 */
394
395 return true;
396 }
397
398 static void intel_lvds_prepare(struct drm_encoder *encoder)
399 {
400 struct drm_device *dev = encoder->dev;
401 struct drm_i915_private *dev_priv = dev->dev_private;
402 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
403
404 /* We try to do the minimum that is necessary in order to unlock
405 * the registers for mode setting.
406 *
407 * On Ironlake, this is quite simple as we just set the unlock key
408 * and ignore all subtleties. (This may cause some issues...)
409 *
410 * Prior to Ironlake, we must disable the pipe if we want to adjust
411 * the panel fitter. However at all other times we can just reset
412 * the registers regardless.
413 */
414
415 if (HAS_PCH_SPLIT(dev)) {
416 I915_WRITE(PCH_PP_CONTROL,
417 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
418 } else if (intel_lvds->pfit_dirty) {
419 I915_WRITE(PP_CONTROL,
420 (I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS)
421 & ~POWER_TARGET_ON);
422 } else {
423 I915_WRITE(PP_CONTROL,
424 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
425 }
426 }
427
428 static void intel_lvds_commit(struct drm_encoder *encoder)
429 {
430 struct drm_device *dev = encoder->dev;
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
433
434 /* Undo any unlocking done in prepare to prevent accidental
435 * adjustment of the registers.
436 */
437 if (HAS_PCH_SPLIT(dev)) {
438 u32 val = I915_READ(PCH_PP_CONTROL);
439 if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)
440 I915_WRITE(PCH_PP_CONTROL, val & 0x3);
441 } else {
442 u32 val = I915_READ(PP_CONTROL);
443 if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)
444 I915_WRITE(PP_CONTROL, val & 0x3);
445 }
446
447 /* Always do a full power on as we do not know what state
448 * we were left in.
449 */
450 intel_lvds_enable(intel_lvds);
451 }
452
453 static void intel_lvds_mode_set(struct drm_encoder *encoder,
454 struct drm_display_mode *mode,
455 struct drm_display_mode *adjusted_mode)
456 {
457 /*
458 * The LVDS pin pair will already have been turned on in the
459 * intel_crtc_mode_set since it has a large impact on the DPLL
460 * settings.
461 */
462 }
463
464 /**
465 * Detect the LVDS connection.
466 *
467 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
468 * connected and closed means disconnected. We also send hotplug events as
469 * needed, using lid status notification from the input layer.
470 */
471 static enum drm_connector_status
472 intel_lvds_detect(struct drm_connector *connector, bool force)
473 {
474 struct drm_device *dev = connector->dev;
475 struct drm_i915_private *dev_priv = dev->dev_private;
476 enum drm_connector_status status = connector_status_connected;
477
478 /* Assume that the BIOS does not lie through the OpRegion... */
479 if (dev_priv->opregion.lid_state)
480 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
481 connector_status_connected :
482 connector_status_disconnected;
483
484 /* ACPI lid methods were generally unreliable in this generation, so
485 * don't even bother.
486 */
487 if (IS_GEN2(dev) || IS_GEN3(dev))
488 return connector_status_connected;
489
490 return status;
491 }
492
493 /**
494 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
495 */
496 static int intel_lvds_get_modes(struct drm_connector *connector)
497 {
498 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
499 struct drm_device *dev = connector->dev;
500 struct drm_display_mode *mode;
501
502 if (intel_lvds->edid)
503 return drm_add_edid_modes(connector, intel_lvds->edid);
504
505 mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode);
506 if (mode == NULL)
507 return 0;
508
509 drm_mode_probed_add(connector, mode);
510 return 1;
511 }
512
513 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
514 {
515 DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident);
516 return 1;
517 }
518
519 /* The GPU hangs up on these systems if modeset is performed on LID open */
520 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
521 {
522 .callback = intel_no_modeset_on_lid_dmi_callback,
523 .ident = "Toshiba Tecra A11",
524 .matches = {
525 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
526 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
527 },
528 },
529
530 { } /* terminating entry */
531 };
532
533 /*
534 * Lid events. Note the use of 'modeset_on_lid':
535 * - we set it on lid close, and reset it on open
536 * - we use it as a "only once" bit (ie we ignore
537 * duplicate events where it was already properly
538 * set/reset)
539 * - the suspend/resume paths will also set it to
540 * zero, since they restore the mode ("lid open").
541 */
542 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
543 void *unused)
544 {
545 struct drm_i915_private *dev_priv =
546 container_of(nb, struct drm_i915_private, lid_notifier);
547 struct drm_device *dev = dev_priv->dev;
548 struct drm_connector *connector = dev_priv->int_lvds_connector;
549
550 /*
551 * check and update the status of LVDS connector after receiving
552 * the LID nofication event.
553 */
554 if (connector)
555 connector->status = connector->funcs->detect(connector,
556 false);
557
558 /* Don't force modeset on machines where it causes a GPU lockup */
559 if (dmi_check_system(intel_no_modeset_on_lid))
560 return NOTIFY_OK;
561 if (!acpi_lid_open()) {
562 dev_priv->modeset_on_lid = 1;
563 return NOTIFY_OK;
564 }
565
566 if (!dev_priv->modeset_on_lid)
567 return NOTIFY_OK;
568
569 dev_priv->modeset_on_lid = 0;
570
571 mutex_lock(&dev->mode_config.mutex);
572 drm_helper_resume_force_mode(dev);
573 mutex_unlock(&dev->mode_config.mutex);
574
575 return NOTIFY_OK;
576 }
577
578 /**
579 * intel_lvds_destroy - unregister and free LVDS structures
580 * @connector: connector to free
581 *
582 * Unregister the DDC bus for this connector then free the driver private
583 * structure.
584 */
585 static void intel_lvds_destroy(struct drm_connector *connector)
586 {
587 struct drm_device *dev = connector->dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
589
590 if (dev_priv->lid_notifier.notifier_call)
591 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
592 drm_sysfs_connector_remove(connector);
593 drm_connector_cleanup(connector);
594 kfree(connector);
595 }
596
597 static int intel_lvds_set_property(struct drm_connector *connector,
598 struct drm_property *property,
599 uint64_t value)
600 {
601 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
602 struct drm_device *dev = connector->dev;
603
604 if (property == dev->mode_config.scaling_mode_property) {
605 struct drm_crtc *crtc = intel_lvds->base.base.crtc;
606
607 if (value == DRM_MODE_SCALE_NONE) {
608 DRM_DEBUG_KMS("no scaling not supported\n");
609 return -EINVAL;
610 }
611
612 if (intel_lvds->fitting_mode == value) {
613 /* the LVDS scaling property is not changed */
614 return 0;
615 }
616 intel_lvds->fitting_mode = value;
617 if (crtc && crtc->enabled) {
618 /*
619 * If the CRTC is enabled, the display will be changed
620 * according to the new panel fitting mode.
621 */
622 drm_crtc_helper_set_mode(crtc, &crtc->mode,
623 crtc->x, crtc->y, crtc->fb);
624 }
625 }
626
627 return 0;
628 }
629
630 static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
631 .dpms = intel_lvds_dpms,
632 .mode_fixup = intel_lvds_mode_fixup,
633 .prepare = intel_lvds_prepare,
634 .mode_set = intel_lvds_mode_set,
635 .commit = intel_lvds_commit,
636 };
637
638 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
639 .get_modes = intel_lvds_get_modes,
640 .mode_valid = intel_lvds_mode_valid,
641 .best_encoder = intel_best_encoder,
642 };
643
644 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
645 .dpms = drm_helper_connector_dpms,
646 .detect = intel_lvds_detect,
647 .fill_modes = drm_helper_probe_single_connector_modes,
648 .set_property = intel_lvds_set_property,
649 .destroy = intel_lvds_destroy,
650 };
651
652 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
653 .destroy = intel_encoder_destroy,
654 };
655
656 static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
657 {
658 DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident);
659 return 1;
660 }
661
662 /* These systems claim to have LVDS, but really don't */
663 static const struct dmi_system_id intel_no_lvds[] = {
664 {
665 .callback = intel_no_lvds_dmi_callback,
666 .ident = "Apple Mac Mini (Core series)",
667 .matches = {
668 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
669 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
670 },
671 },
672 {
673 .callback = intel_no_lvds_dmi_callback,
674 .ident = "Apple Mac Mini (Core 2 series)",
675 .matches = {
676 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
677 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
678 },
679 },
680 {
681 .callback = intel_no_lvds_dmi_callback,
682 .ident = "MSI IM-945GSE-A",
683 .matches = {
684 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
685 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
686 },
687 },
688 {
689 .callback = intel_no_lvds_dmi_callback,
690 .ident = "Dell Studio Hybrid",
691 .matches = {
692 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
693 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
694 },
695 },
696 {
697 .callback = intel_no_lvds_dmi_callback,
698 .ident = "AOpen Mini PC",
699 .matches = {
700 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
701 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
702 },
703 },
704 {
705 .callback = intel_no_lvds_dmi_callback,
706 .ident = "AOpen Mini PC MP915",
707 .matches = {
708 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
709 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
710 },
711 },
712 {
713 .callback = intel_no_lvds_dmi_callback,
714 .ident = "AOpen i915GMm-HFS",
715 .matches = {
716 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
717 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
718 },
719 },
720 {
721 .callback = intel_no_lvds_dmi_callback,
722 .ident = "Aopen i945GTt-VFA",
723 .matches = {
724 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
725 },
726 },
727 {
728 .callback = intel_no_lvds_dmi_callback,
729 .ident = "Clientron U800",
730 .matches = {
731 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
732 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
733 },
734 },
735
736 { } /* terminating entry */
737 };
738
739 /**
740 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
741 * @dev: drm device
742 * @connector: LVDS connector
743 *
744 * Find the reduced downclock for LVDS in EDID.
745 */
746 static void intel_find_lvds_downclock(struct drm_device *dev,
747 struct drm_display_mode *fixed_mode,
748 struct drm_connector *connector)
749 {
750 struct drm_i915_private *dev_priv = dev->dev_private;
751 struct drm_display_mode *scan;
752 int temp_downclock;
753
754 temp_downclock = fixed_mode->clock;
755 list_for_each_entry(scan, &connector->probed_modes, head) {
756 /*
757 * If one mode has the same resolution with the fixed_panel
758 * mode while they have the different refresh rate, it means
759 * that the reduced downclock is found for the LVDS. In such
760 * case we can set the different FPx0/1 to dynamically select
761 * between low and high frequency.
762 */
763 if (scan->hdisplay == fixed_mode->hdisplay &&
764 scan->hsync_start == fixed_mode->hsync_start &&
765 scan->hsync_end == fixed_mode->hsync_end &&
766 scan->htotal == fixed_mode->htotal &&
767 scan->vdisplay == fixed_mode->vdisplay &&
768 scan->vsync_start == fixed_mode->vsync_start &&
769 scan->vsync_end == fixed_mode->vsync_end &&
770 scan->vtotal == fixed_mode->vtotal) {
771 if (scan->clock < temp_downclock) {
772 /*
773 * The downclock is already found. But we
774 * expect to find the lower downclock.
775 */
776 temp_downclock = scan->clock;
777 }
778 }
779 }
780 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
781 /* We found the downclock for LVDS. */
782 dev_priv->lvds_downclock_avail = 1;
783 dev_priv->lvds_downclock = temp_downclock;
784 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
785 "Normal clock %dKhz, downclock %dKhz\n",
786 fixed_mode->clock, temp_downclock);
787 }
788 }
789
790 /*
791 * Enumerate the child dev array parsed from VBT to check whether
792 * the LVDS is present.
793 * If it is present, return 1.
794 * If it is not present, return false.
795 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
796 */
797 static bool lvds_is_present_in_vbt(struct drm_device *dev,
798 u8 *i2c_pin)
799 {
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 int i;
802
803 if (!dev_priv->child_dev_num)
804 return true;
805
806 for (i = 0; i < dev_priv->child_dev_num; i++) {
807 struct child_device_config *child = dev_priv->child_dev + i;
808
809 /* If the device type is not LFP, continue.
810 * We have to check both the new identifiers as well as the
811 * old for compatibility with some BIOSes.
812 */
813 if (child->device_type != DEVICE_TYPE_INT_LFP &&
814 child->device_type != DEVICE_TYPE_LFP)
815 continue;
816
817 if (child->i2c_pin)
818 *i2c_pin = child->i2c_pin;
819
820 /* However, we cannot trust the BIOS writers to populate
821 * the VBT correctly. Since LVDS requires additional
822 * information from AIM blocks, a non-zero addin offset is
823 * a good indicator that the LVDS is actually present.
824 */
825 if (child->addin_offset)
826 return true;
827
828 /* But even then some BIOS writers perform some black magic
829 * and instantiate the device without reference to any
830 * additional data. Trust that if the VBT was written into
831 * the OpRegion then they have validated the LVDS's existence.
832 */
833 if (dev_priv->opregion.vbt)
834 return true;
835 }
836
837 return false;
838 }
839
840 static bool intel_lvds_ddc_probe(struct drm_device *dev, u8 pin)
841 {
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 u8 buf = 0;
844 struct i2c_msg msgs[] = {
845 {
846 .addr = 0xA0,
847 .flags = 0,
848 .len = 1,
849 .buf = &buf,
850 },
851 };
852 struct i2c_adapter *i2c = &dev_priv->gmbus[pin].adapter;
853 /* XXX this only appears to work when using GMBUS */
854 if (intel_gmbus_is_forced_bit(i2c))
855 return true;
856 return i2c_transfer(i2c, msgs, 1) == 1;
857 }
858
859 /**
860 * intel_lvds_init - setup LVDS connectors on this device
861 * @dev: drm device
862 *
863 * Create the connector, register the LVDS DDC bus, and try to figure out what
864 * modes we can display on the LVDS panel (if present).
865 */
866 bool intel_lvds_init(struct drm_device *dev)
867 {
868 struct drm_i915_private *dev_priv = dev->dev_private;
869 struct intel_lvds *intel_lvds;
870 struct intel_encoder *intel_encoder;
871 struct intel_connector *intel_connector;
872 struct drm_connector *connector;
873 struct drm_encoder *encoder;
874 struct drm_display_mode *scan; /* *modes, *bios_mode; */
875 struct drm_crtc *crtc;
876 u32 lvds;
877 int pipe;
878 u8 pin;
879
880 /* Skip init on machines we know falsely report LVDS */
881 if (dmi_check_system(intel_no_lvds))
882 return false;
883
884 pin = GMBUS_PORT_PANEL;
885 if (!lvds_is_present_in_vbt(dev, &pin)) {
886 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
887 return false;
888 }
889
890 if (HAS_PCH_SPLIT(dev)) {
891 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
892 return false;
893 if (dev_priv->edp.support) {
894 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
895 return false;
896 }
897 }
898
899 if (!intel_lvds_ddc_probe(dev, pin)) {
900 DRM_DEBUG_KMS("LVDS did not respond to DDC probe\n");
901 return false;
902 }
903
904 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);
905 if (!intel_lvds) {
906 return false;
907 }
908
909 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
910 if (!intel_connector) {
911 kfree(intel_lvds);
912 return false;
913 }
914
915 if (!HAS_PCH_SPLIT(dev)) {
916 intel_lvds->pfit_control = I915_READ(PFIT_CONTROL);
917 }
918
919 intel_encoder = &intel_lvds->base;
920 encoder = &intel_encoder->base;
921 connector = &intel_connector->base;
922 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
923 DRM_MODE_CONNECTOR_LVDS);
924
925 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
926 DRM_MODE_ENCODER_LVDS);
927
928 intel_connector_attach_encoder(intel_connector, intel_encoder);
929 intel_encoder->type = INTEL_OUTPUT_LVDS;
930
931 intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
932 intel_encoder->crtc_mask = (1 << 1);
933 if (INTEL_INFO(dev)->gen >= 5)
934 intel_encoder->crtc_mask |= (1 << 0);
935 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
936 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
937 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
938 connector->interlace_allowed = false;
939 connector->doublescan_allowed = false;
940
941 /* create the scaling mode property */
942 drm_mode_create_scaling_mode_property(dev);
943 /*
944 * the initial panel fitting mode will be FULL_SCREEN.
945 */
946
947 drm_connector_attach_property(&intel_connector->base,
948 dev->mode_config.scaling_mode_property,
949 DRM_MODE_SCALE_ASPECT);
950 intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT;
951 /*
952 * LVDS discovery:
953 * 1) check for EDID on DDC
954 * 2) check for VBT data
955 * 3) check to see if LVDS is already on
956 * if none of the above, no panel
957 * 4) make sure lid is open
958 * if closed, act like it's not there for now
959 */
960
961 /*
962 * Attempt to get the fixed panel mode from DDC. Assume that the
963 * preferred mode is the right one.
964 */
965 intel_lvds->edid = drm_get_edid(connector,
966 &dev_priv->gmbus[pin].adapter);
967 if (intel_lvds->edid) {
968 if (drm_add_edid_modes(connector,
969 intel_lvds->edid)) {
970 drm_mode_connector_update_edid_property(connector,
971 intel_lvds->edid);
972 } else {
973 kfree(intel_lvds->edid);
974 intel_lvds->edid = NULL;
975 }
976 }
977 if (!intel_lvds->edid) {
978 /* Didn't get an EDID, so
979 * Set wide sync ranges so we get all modes
980 * handed to valid_mode for checking
981 */
982 connector->display_info.min_vfreq = 0;
983 connector->display_info.max_vfreq = 200;
984 connector->display_info.min_hfreq = 0;
985 connector->display_info.max_hfreq = 200;
986 }
987
988 list_for_each_entry(scan, &connector->probed_modes, head) {
989 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
990 intel_lvds->fixed_mode =
991 drm_mode_duplicate(dev, scan);
992 intel_find_lvds_downclock(dev,
993 intel_lvds->fixed_mode,
994 connector);
995 goto out;
996 }
997 }
998
999 /* Failed to get EDID, what about VBT? */
1000 if (dev_priv->lfp_lvds_vbt_mode) {
1001 intel_lvds->fixed_mode =
1002 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1003 if (intel_lvds->fixed_mode) {
1004 intel_lvds->fixed_mode->type |=
1005 DRM_MODE_TYPE_PREFERRED;
1006 goto out;
1007 }
1008 }
1009
1010 /*
1011 * If we didn't get EDID, try checking if the panel is already turned
1012 * on. If so, assume that whatever is currently programmed is the
1013 * correct mode.
1014 */
1015
1016 /* Ironlake: FIXME if still fail, not try pipe mode now */
1017 if (HAS_PCH_SPLIT(dev))
1018 goto failed;
1019
1020 lvds = I915_READ(LVDS);
1021 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1022 crtc = intel_get_crtc_for_pipe(dev, pipe);
1023
1024 if (crtc && (lvds & LVDS_PORT_EN)) {
1025 intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc);
1026 if (intel_lvds->fixed_mode) {
1027 intel_lvds->fixed_mode->type |=
1028 DRM_MODE_TYPE_PREFERRED;
1029 goto out;
1030 }
1031 }
1032
1033 /* If we still don't have a mode after all that, give up. */
1034 if (!intel_lvds->fixed_mode)
1035 goto failed;
1036
1037 out:
1038 if (HAS_PCH_SPLIT(dev)) {
1039 u32 pwm;
1040
1041 pipe = (I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) ? 1 : 0;
1042
1043 /* make sure PWM is enabled and locked to the LVDS pipe */
1044 pwm = I915_READ(BLC_PWM_CPU_CTL2);
1045 if (pipe == 0 && (pwm & PWM_PIPE_B))
1046 I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE);
1047 if (pipe)
1048 pwm |= PWM_PIPE_B;
1049 else
1050 pwm &= ~PWM_PIPE_B;
1051 I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE);
1052
1053 pwm = I915_READ(BLC_PWM_PCH_CTL1);
1054 pwm |= PWM_PCH_ENABLE;
1055 I915_WRITE(BLC_PWM_PCH_CTL1, pwm);
1056 }
1057 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1058 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
1059 DRM_DEBUG_KMS("lid notifier registration failed\n");
1060 dev_priv->lid_notifier.notifier_call = NULL;
1061 }
1062 /* keep the LVDS connector */
1063 dev_priv->int_lvds_connector = connector;
1064 drm_sysfs_connector_add(connector);
1065 return true;
1066
1067 failed:
1068 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1069 drm_connector_cleanup(connector);
1070 drm_encoder_cleanup(encoder);
1071 kfree(intel_lvds);
1072 kfree(intel_connector);
1073 return false;
1074 }
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