2 * Copyright (c) 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions: *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "intel_mocs.h"
24 #include "intel_lrc.h"
25 #include "intel_ringbuffer.h"
27 /* structures required */
28 struct drm_i915_mocs_entry
{
33 struct drm_i915_mocs_table
{
35 const struct drm_i915_mocs_entry
*table
;
38 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
39 #define LE_CACHEABILITY(value) ((value) << 0)
40 #define LE_TGT_CACHE(value) ((value) << 2)
41 #define LE_LRUM(value) ((value) << 4)
42 #define LE_AOM(value) ((value) << 6)
43 #define LE_RSC(value) ((value) << 7)
44 #define LE_SCC(value) ((value) << 8)
45 #define LE_PFM(value) ((value) << 11)
46 #define LE_SCF(value) ((value) << 14)
48 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
49 #define L3_ESC(value) ((value) << 0)
50 #define L3_SCC(value) ((value) << 1)
51 #define L3_CACHEABILITY(value) ((value) << 4)
54 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
56 /* (e)LLC caching options */
57 #define LE_PAGETABLE 0
62 /* L3 caching options */
69 #define LE_TC_PAGETABLE 0
71 #define LE_TC_LLC_ELLC 2
72 #define LE_TC_LLC_ELLC_ALT 3
77 * These are the MOCS tables that are programmed across all the rings.
78 * The control value is programmed to all the rings that support the
79 * MOCS registers. While the l3cc_values are only programmed to the
80 * LNCFCMOCS0 - LNCFCMOCS32 registers.
82 * These tables are intended to be kept reasonably consistent across
83 * platforms. However some of the fields are not applicable to all of
86 * Entries not part of the following tables are undefined as far as
87 * userspace is concerned and shouldn't be relied upon. For the time
88 * being they will be implicitly initialized to the strictest caching
89 * configuration (uncached) to guarantee forwards compatibility with
90 * userspace programs written against more recent kernels providing
91 * additional MOCS entries.
93 * NOTE: These tables MUST start with being uncached and the length
94 * MUST be less than 63 as the last two registers are reserved
95 * by the hardware. These tables are part of the kernel ABI and
96 * may only be updated incrementally by adding entries at the
99 static const struct drm_i915_mocs_entry skylake_mocs_table
[] = {
101 .control_value
= LE_CACHEABILITY(LE_UC
) |
102 LE_TGT_CACHE(LE_TC_LLC_ELLC
) |
103 LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
104 LE_PFM(0) | LE_SCF(0),
107 .l3cc_value
= L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC
),
111 .control_value
= LE_CACHEABILITY(LE_PAGETABLE
) |
112 LE_TGT_CACHE(LE_TC_LLC_ELLC
) |
113 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
114 LE_PFM(0) | LE_SCF(0),
116 .l3cc_value
= L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
),
120 .control_value
= LE_CACHEABILITY(LE_WB
) |
121 LE_TGT_CACHE(LE_TC_LLC_ELLC
) |
122 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
123 LE_PFM(0) | LE_SCF(0),
125 .l3cc_value
= L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
),
129 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
130 static const struct drm_i915_mocs_entry broxton_mocs_table
[] = {
133 .control_value
= LE_CACHEABILITY(LE_UC
) |
134 LE_TGT_CACHE(LE_TC_LLC_ELLC
) |
135 LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
136 LE_PFM(0) | LE_SCF(0),
139 .l3cc_value
= L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC
),
143 .control_value
= LE_CACHEABILITY(LE_PAGETABLE
) |
144 LE_TGT_CACHE(LE_TC_LLC_ELLC
) |
145 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
146 LE_PFM(0) | LE_SCF(0),
149 .l3cc_value
= L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
),
153 .control_value
= LE_CACHEABILITY(LE_UC
) |
154 LE_TGT_CACHE(LE_TC_LLC_ELLC
) |
155 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
156 LE_PFM(0) | LE_SCF(0),
159 .l3cc_value
= L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
),
164 * get_mocs_settings()
165 * @dev_priv: i915 device.
166 * @table: Output table that will be made to point at appropriate
167 * MOCS values for the device.
169 * This function will return the values of the MOCS table that needs to
170 * be programmed for the platform. It will return the values that need
171 * to be programmed and if they need to be programmed.
173 * Return: true if there are applicable MOCS settings for the device.
175 static bool get_mocs_settings(struct drm_i915_private
*dev_priv
,
176 struct drm_i915_mocs_table
*table
)
180 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
181 table
->size
= ARRAY_SIZE(skylake_mocs_table
);
182 table
->table
= skylake_mocs_table
;
184 } else if (IS_BROXTON(dev_priv
)) {
185 table
->size
= ARRAY_SIZE(broxton_mocs_table
);
186 table
->table
= broxton_mocs_table
;
189 WARN_ONCE(INTEL_INFO(dev_priv
)->gen
>= 9,
190 "Platform that should have a MOCS table does not.\n");
193 /* WaDisableSkipCaching:skl,bxt,kbl */
194 if (IS_GEN9(dev_priv
)) {
197 for (i
= 0; i
< table
->size
; i
++)
198 if (WARN_ON(table
->table
[i
].l3cc_value
&
199 (L3_ESC(1) | L3_SCC(0x7))))
206 static i915_reg_t
mocs_register(enum intel_engine_id ring
, int index
)
210 return GEN9_GFX_MOCS(index
);
212 return GEN9_MFX0_MOCS(index
);
214 return GEN9_BLT_MOCS(index
);
216 return GEN9_VEBOX_MOCS(index
);
218 return GEN9_MFX1_MOCS(index
);
221 return INVALID_MMIO_REG
;
226 * intel_mocs_init_engine() - emit the mocs control table
227 * @engine: The engine for whom to emit the registers.
229 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
230 * given table starting at the given address.
232 * Return: 0 on success, otherwise the error status.
234 int intel_mocs_init_engine(struct intel_engine_cs
*engine
)
236 struct drm_i915_private
*dev_priv
= engine
->i915
;
237 struct drm_i915_mocs_table table
;
240 if (!get_mocs_settings(dev_priv
, &table
))
243 if (WARN_ON(table
.size
> GEN9_NUM_MOCS_ENTRIES
))
246 for (index
= 0; index
< table
.size
; index
++)
247 I915_WRITE(mocs_register(engine
->id
, index
),
248 table
.table
[index
].control_value
);
251 * Ok, now set the unused entries to uncached. These entries
252 * are officially undefined and no contract for the contents
253 * and settings is given for these entries.
255 * Entry 0 in the table is uncached - so we are just writing
256 * that value to all the used entries.
258 for (; index
< GEN9_NUM_MOCS_ENTRIES
; index
++)
259 I915_WRITE(mocs_register(engine
->id
, index
),
260 table
.table
[0].control_value
);
266 * emit_mocs_control_table() - emit the mocs control table
267 * @req: Request to set up the MOCS table for.
268 * @table: The values to program into the control regs.
270 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
271 * given table starting at the given address.
273 * Return: 0 on success, otherwise the error status.
275 static int emit_mocs_control_table(struct drm_i915_gem_request
*req
,
276 const struct drm_i915_mocs_table
*table
)
278 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
279 enum intel_engine_id engine
= req
->engine
->id
;
283 if (WARN_ON(table
->size
> GEN9_NUM_MOCS_ENTRIES
))
286 ret
= intel_ring_begin(req
, 2 + 2 * GEN9_NUM_MOCS_ENTRIES
);
290 intel_logical_ring_emit(ringbuf
,
291 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES
));
293 for (index
= 0; index
< table
->size
; index
++) {
294 intel_logical_ring_emit_reg(ringbuf
,
295 mocs_register(engine
, index
));
296 intel_logical_ring_emit(ringbuf
,
297 table
->table
[index
].control_value
);
301 * Ok, now set the unused entries to uncached. These entries
302 * are officially undefined and no contract for the contents
303 * and settings is given for these entries.
305 * Entry 0 in the table is uncached - so we are just writing
306 * that value to all the used entries.
308 for (; index
< GEN9_NUM_MOCS_ENTRIES
; index
++) {
309 intel_logical_ring_emit_reg(ringbuf
,
310 mocs_register(engine
, index
));
311 intel_logical_ring_emit(ringbuf
,
312 table
->table
[0].control_value
);
315 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
316 intel_logical_ring_advance(ringbuf
);
321 static inline u32
l3cc_combine(const struct drm_i915_mocs_table
*table
,
325 return table
->table
[low
].l3cc_value
|
326 table
->table
[high
].l3cc_value
<< 16;
330 * emit_mocs_l3cc_table() - emit the mocs control table
331 * @req: Request to set up the MOCS table for.
332 * @table: The values to program into the control regs.
334 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
335 * given table starting at the given address. This register set is
336 * programmed in pairs.
338 * Return: 0 on success, otherwise the error status.
340 static int emit_mocs_l3cc_table(struct drm_i915_gem_request
*req
,
341 const struct drm_i915_mocs_table
*table
)
343 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
347 if (WARN_ON(table
->size
> GEN9_NUM_MOCS_ENTRIES
))
350 ret
= intel_ring_begin(req
, 2 + GEN9_NUM_MOCS_ENTRIES
);
354 intel_logical_ring_emit(ringbuf
,
355 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES
/ 2));
357 for (i
= 0; i
< table
->size
/2; i
++) {
358 intel_logical_ring_emit_reg(ringbuf
, GEN9_LNCFCMOCS(i
));
359 intel_logical_ring_emit(ringbuf
,
360 l3cc_combine(table
, 2*i
, 2*i
+1));
363 if (table
->size
& 0x01) {
364 /* Odd table size - 1 left over */
365 intel_logical_ring_emit_reg(ringbuf
, GEN9_LNCFCMOCS(i
));
366 intel_logical_ring_emit(ringbuf
, l3cc_combine(table
, 2*i
, 0));
371 * Now set the rest of the table to uncached - use entry 0 as
372 * this will be uncached. Leave the last pair uninitialised as
373 * they are reserved by the hardware.
375 for (; i
< GEN9_NUM_MOCS_ENTRIES
/ 2; i
++) {
376 intel_logical_ring_emit_reg(ringbuf
, GEN9_LNCFCMOCS(i
));
377 intel_logical_ring_emit(ringbuf
, l3cc_combine(table
, 0, 0));
380 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
381 intel_logical_ring_advance(ringbuf
);
387 * intel_mocs_init_l3cc_table() - program the mocs control table
388 * @dev: The the device to be programmed.
390 * This function simply programs the mocs registers for the given table
391 * starting at the given address. This register set is programmed in pairs.
393 * These registers may get programmed more than once, it is simpler to
394 * re-program 32 registers than maintain the state of when they were programmed.
395 * We are always reprogramming with the same values and this only on context
400 void intel_mocs_init_l3cc_table(struct drm_device
*dev
)
402 struct drm_i915_private
*dev_priv
= to_i915(dev
);
403 struct drm_i915_mocs_table table
;
406 if (!get_mocs_settings(dev_priv
, &table
))
409 for (i
= 0; i
< table
.size
/2; i
++)
410 I915_WRITE(GEN9_LNCFCMOCS(i
), l3cc_combine(&table
, 2*i
, 2*i
+1));
412 /* Odd table size - 1 left over */
413 if (table
.size
& 0x01) {
414 I915_WRITE(GEN9_LNCFCMOCS(i
), l3cc_combine(&table
, 2*i
, 0));
419 * Now set the rest of the table to uncached - use entry 0 as
420 * this will be uncached. Leave the last pair as initialised as
421 * they are reserved by the hardware.
423 for (; i
< (GEN9_NUM_MOCS_ENTRIES
/ 2); i
++)
424 I915_WRITE(GEN9_LNCFCMOCS(i
), l3cc_combine(&table
, 0, 0));
428 * intel_rcs_context_init_mocs() - program the MOCS register.
429 * @req: Request to set up the MOCS tables for.
431 * This function will emit a batch buffer with the values required for
432 * programming the MOCS register values for all the currently supported
435 * These registers are partially stored in the RCS context, so they are
436 * emitted at the same time so that when a context is created these registers
437 * are set up. These registers have to be emitted into the start of the
438 * context as setting the ELSP will re-init some of these registers back
441 * Return: 0 on success, otherwise the error status.
443 int intel_rcs_context_init_mocs(struct drm_i915_gem_request
*req
)
445 struct drm_i915_mocs_table t
;
448 if (get_mocs_settings(req
->i915
, &t
)) {
449 /* Program the RCS control registers */
450 ret
= emit_mocs_control_table(req
, &t
);
454 /* Now program the l3cc registers */
455 ret
= emit_mocs_l3cc_table(req
, &t
);