4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
34 /* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38 #define IMAGE_MAX_WIDTH 2048
39 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40 /* on 830 and 845 these large limits result in the card hanging */
41 #define IMAGE_MAX_WIDTH_LEGACY 1024
42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44 /* overlay register definitions */
46 #define OCMD_TILED_SURFACE (0x1<<19)
47 #define OCMD_MIRROR_MASK (0x3<<17)
48 #define OCMD_MIRROR_MODE (0x3<<17)
49 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50 #define OCMD_MIRROR_VERTICAL (0x2<<17)
51 #define OCMD_MIRROR_BOTH (0x3<<17)
52 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60 #define OCMD_YUV_422_PACKED (0x8<<10)
61 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62 #define OCMD_YUV_420_PLANAR (0xc<<10)
63 #define OCMD_YUV_422_PLANAR (0xd<<10)
64 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
67 #define OCMD_BUF_TYPE_MASK (0x1<<5)
68 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
69 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
70 #define OCMD_TEST_MODE (0x1<<4)
71 #define OCMD_BUFFER_SELECT (0x3<<2)
72 #define OCMD_BUFFER0 (0x0<<2)
73 #define OCMD_BUFFER1 (0x1<<2)
74 #define OCMD_FIELD_SELECT (0x1<<2)
75 #define OCMD_FIELD0 (0x0<<1)
76 #define OCMD_FIELD1 (0x1<<1)
77 #define OCMD_ENABLE (0x1<<0)
79 /* OCONFIG register */
80 #define OCONF_PIPE_MASK (0x1<<18)
81 #define OCONF_PIPE_A (0x0<<18)
82 #define OCONF_PIPE_B (0x1<<18)
83 #define OCONF_GAMMA2_ENABLE (0x1<<16)
84 #define OCONF_CSC_MODE_BT601 (0x0<<5)
85 #define OCONF_CSC_MODE_BT709 (0x1<<5)
86 #define OCONF_CSC_BYPASS (0x1<<4)
87 #define OCONF_CC_OUT_8BIT (0x1<<3)
88 #define OCONF_TEST_MODE (0x1<<2)
89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
90 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92 /* DCLRKM (dst-key) register */
93 #define DST_KEY_ENABLE (0x1<<31)
94 #define CLK_RGB24_MASK 0x0
95 #define CLK_RGB16_MASK 0x070307
96 #define CLK_RGB15_MASK 0x070707
97 #define CLK_RGB8I_MASK 0xffffff
99 #define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101 #define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104 /* overlay flip addr flag */
105 #define OFC_UPDATE 0x1
107 /* polyphase filter coefficients */
108 #define N_HORIZ_Y_TAPS 5
109 #define N_VERT_Y_TAPS 3
110 #define N_HORIZ_UV_TAPS 3
111 #define N_VERT_UV_TAPS 3
115 /* memory bufferd overlay registers */
116 struct overlay_registers
{
144 u32 RESERVED1
; /* 0x6C */
157 u32 FASTHSCALE
; /* 0xA0 */
158 u32 UVSCALEV
; /* 0xA4 */
159 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
161 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
162 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
163 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
164 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
165 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
166 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
167 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
170 struct intel_overlay
{
171 struct drm_device
*dev
;
172 struct intel_crtc
*crtc
;
173 struct drm_i915_gem_object
*vid_bo
;
174 struct drm_i915_gem_object
*old_vid_bo
;
177 u32 pfit_vscale_ratio
; /* shifted-point number, (1<<12) == 1.0 */
179 u32 brightness
, contrast
, saturation
;
180 u32 old_xscale
, old_yscale
;
181 /* register access */
183 struct drm_i915_gem_object
*reg_bo
;
185 uint32_t last_flip_req
;
186 void (*flip_tail
)(struct intel_overlay
*);
189 static struct overlay_registers __iomem
*
190 intel_overlay_map_regs(struct intel_overlay
*overlay
)
192 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
193 struct overlay_registers __iomem
*regs
;
195 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
196 regs
= (struct overlay_registers __iomem
*)overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
198 regs
= io_mapping_map_wc(dev_priv
->mm
.gtt_mapping
,
199 overlay
->reg_bo
->gtt_offset
);
204 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
,
205 struct overlay_registers __iomem
*regs
)
207 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
208 io_mapping_unmap(regs
);
211 static int intel_overlay_do_wait_request(struct intel_overlay
*overlay
,
212 void (*tail
)(struct intel_overlay
*))
214 struct drm_device
*dev
= overlay
->dev
;
215 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
216 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
219 BUG_ON(overlay
->last_flip_req
);
220 ret
= i915_add_request(ring
, NULL
, &overlay
->last_flip_req
);
224 overlay
->flip_tail
= tail
;
225 ret
= i915_wait_seqno(ring
, overlay
->last_flip_req
);
228 i915_gem_retire_requests(dev
);
230 overlay
->last_flip_req
= 0;
234 /* overlay needs to be disable in OCMD reg */
235 static int intel_overlay_on(struct intel_overlay
*overlay
)
237 struct drm_device
*dev
= overlay
->dev
;
238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
239 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
242 BUG_ON(overlay
->active
);
245 WARN_ON(IS_I830(dev
) && !(dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
247 ret
= intel_ring_begin(ring
, 4);
251 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
252 intel_ring_emit(ring
, overlay
->flip_addr
| OFC_UPDATE
);
253 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
254 intel_ring_emit(ring
, MI_NOOP
);
255 intel_ring_advance(ring
);
257 return intel_overlay_do_wait_request(overlay
, NULL
);
260 /* overlay needs to be enabled in OCMD reg */
261 static int intel_overlay_continue(struct intel_overlay
*overlay
,
262 bool load_polyphase_filter
)
264 struct drm_device
*dev
= overlay
->dev
;
265 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
266 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
267 u32 flip_addr
= overlay
->flip_addr
;
271 BUG_ON(!overlay
->active
);
273 if (load_polyphase_filter
)
274 flip_addr
|= OFC_UPDATE
;
276 /* check for underruns */
277 tmp
= I915_READ(DOVSTA
);
279 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
281 ret
= intel_ring_begin(ring
, 2);
285 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
286 intel_ring_emit(ring
, flip_addr
);
287 intel_ring_advance(ring
);
289 return i915_add_request(ring
, NULL
, &overlay
->last_flip_req
);
292 static void intel_overlay_release_old_vid_tail(struct intel_overlay
*overlay
)
294 struct drm_i915_gem_object
*obj
= overlay
->old_vid_bo
;
296 i915_gem_object_unpin(obj
);
297 drm_gem_object_unreference(&obj
->base
);
299 overlay
->old_vid_bo
= NULL
;
302 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
304 struct drm_i915_gem_object
*obj
= overlay
->vid_bo
;
306 /* never have the overlay hw on without showing a frame */
307 BUG_ON(!overlay
->vid_bo
);
309 i915_gem_object_unpin(obj
);
310 drm_gem_object_unreference(&obj
->base
);
311 overlay
->vid_bo
= NULL
;
313 overlay
->crtc
->overlay
= NULL
;
314 overlay
->crtc
= NULL
;
318 /* overlay needs to be disabled in OCMD reg */
319 static int intel_overlay_off(struct intel_overlay
*overlay
)
321 struct drm_device
*dev
= overlay
->dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
323 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
324 u32 flip_addr
= overlay
->flip_addr
;
327 BUG_ON(!overlay
->active
);
329 /* According to intel docs the overlay hw may hang (when switching
330 * off) without loading the filter coeffs. It is however unclear whether
331 * this applies to the disabling of the overlay or to the switching off
332 * of the hw. Do it in both cases */
333 flip_addr
|= OFC_UPDATE
;
335 ret
= intel_ring_begin(ring
, 6);
339 /* wait for overlay to go idle */
340 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
341 intel_ring_emit(ring
, flip_addr
);
342 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
343 /* turn overlay off */
344 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
345 intel_ring_emit(ring
, flip_addr
);
346 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
347 intel_ring_advance(ring
);
349 return intel_overlay_do_wait_request(overlay
, intel_overlay_off_tail
);
352 /* recover from an interruption due to a signal
353 * We have to be careful not to repeat work forever an make forward progess. */
354 static int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
)
356 struct drm_device
*dev
= overlay
->dev
;
357 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
358 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
361 if (overlay
->last_flip_req
== 0)
364 ret
= i915_wait_seqno(ring
, overlay
->last_flip_req
);
367 i915_gem_retire_requests(dev
);
369 if (overlay
->flip_tail
)
370 overlay
->flip_tail(overlay
);
372 overlay
->last_flip_req
= 0;
376 /* Wait for pending overlay flip and release old frame.
377 * Needs to be called before the overlay register are changed
378 * via intel_overlay_(un)map_regs
380 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
382 struct drm_device
*dev
= overlay
->dev
;
383 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
384 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
387 /* Only wait if there is actually an old frame to release to
388 * guarantee forward progress.
390 if (!overlay
->old_vid_bo
)
393 if (I915_READ(ISR
) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
) {
394 /* synchronous slowpath */
395 ret
= intel_ring_begin(ring
, 2);
399 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
400 intel_ring_emit(ring
, MI_NOOP
);
401 intel_ring_advance(ring
);
403 ret
= intel_overlay_do_wait_request(overlay
,
404 intel_overlay_release_old_vid_tail
);
409 intel_overlay_release_old_vid_tail(overlay
);
413 struct put_image_params
{
430 static int packed_depth_bytes(u32 format
)
432 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
433 case I915_OVERLAY_YUV422
:
435 case I915_OVERLAY_YUV411
:
436 /* return 6; not implemented */
442 static int packed_width_bytes(u32 format
, short width
)
444 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
445 case I915_OVERLAY_YUV422
:
452 static int uv_hsubsampling(u32 format
)
454 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
455 case I915_OVERLAY_YUV422
:
456 case I915_OVERLAY_YUV420
:
458 case I915_OVERLAY_YUV411
:
459 case I915_OVERLAY_YUV410
:
466 static int uv_vsubsampling(u32 format
)
468 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
469 case I915_OVERLAY_YUV420
:
470 case I915_OVERLAY_YUV410
:
472 case I915_OVERLAY_YUV422
:
473 case I915_OVERLAY_YUV411
:
480 static u32
calc_swidthsw(struct drm_device
*dev
, u32 offset
, u32 width
)
482 u32 mask
, shift
, ret
;
490 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
497 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
498 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
499 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
500 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
501 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
502 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
503 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
504 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
505 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
506 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
507 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
508 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
509 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
510 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
511 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
512 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
513 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
514 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
517 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
518 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
519 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
520 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
521 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
522 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
523 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
524 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
525 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
526 0x3000, 0x0800, 0x3000
529 static void update_polyphase_filter(struct overlay_registers __iomem
*regs
)
531 memcpy_toio(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
532 memcpy_toio(regs
->UV_HCOEFS
, uv_static_hcoeffs
,
533 sizeof(uv_static_hcoeffs
));
536 static bool update_scaling_factors(struct intel_overlay
*overlay
,
537 struct overlay_registers __iomem
*regs
,
538 struct put_image_params
*params
)
540 /* fixed point with a 12 bit shift */
541 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
543 #define FRACT_MASK 0xfff
544 bool scale_changed
= false;
545 int uv_hscale
= uv_hsubsampling(params
->format
);
546 int uv_vscale
= uv_vsubsampling(params
->format
);
548 if (params
->dst_w
> 1)
549 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
552 xscale
= 1 << FP_SHIFT
;
554 if (params
->dst_h
> 1)
555 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
558 yscale
= 1 << FP_SHIFT
;
560 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
561 xscale_UV
= xscale
/uv_hscale
;
562 yscale_UV
= yscale
/uv_vscale
;
563 /* make the Y scale to UV scale ratio an exact multiply */
564 xscale
= xscale_UV
* uv_hscale
;
565 yscale
= yscale_UV
* uv_vscale
;
571 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
572 scale_changed
= true;
573 overlay
->old_xscale
= xscale
;
574 overlay
->old_yscale
= yscale
;
576 iowrite32(((yscale
& FRACT_MASK
) << 20) |
577 ((xscale
>> FP_SHIFT
) << 16) |
578 ((xscale
& FRACT_MASK
) << 3),
581 iowrite32(((yscale_UV
& FRACT_MASK
) << 20) |
582 ((xscale_UV
>> FP_SHIFT
) << 16) |
583 ((xscale_UV
& FRACT_MASK
) << 3),
586 iowrite32((((yscale
>> FP_SHIFT
) << 16) |
587 ((yscale_UV
>> FP_SHIFT
) << 0)),
591 update_polyphase_filter(regs
);
593 return scale_changed
;
596 static void update_colorkey(struct intel_overlay
*overlay
,
597 struct overlay_registers __iomem
*regs
)
599 u32 key
= overlay
->color_key
;
601 switch (overlay
->crtc
->base
.fb
->bits_per_pixel
) {
603 iowrite32(0, ®s
->DCLRKV
);
604 iowrite32(CLK_RGB8I_MASK
| DST_KEY_ENABLE
, ®s
->DCLRKM
);
608 if (overlay
->crtc
->base
.fb
->depth
== 15) {
609 iowrite32(RGB15_TO_COLORKEY(key
), ®s
->DCLRKV
);
610 iowrite32(CLK_RGB15_MASK
| DST_KEY_ENABLE
,
613 iowrite32(RGB16_TO_COLORKEY(key
), ®s
->DCLRKV
);
614 iowrite32(CLK_RGB16_MASK
| DST_KEY_ENABLE
,
621 iowrite32(key
, ®s
->DCLRKV
);
622 iowrite32(CLK_RGB24_MASK
| DST_KEY_ENABLE
, ®s
->DCLRKM
);
627 static u32
overlay_cmd_reg(struct put_image_params
*params
)
629 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
631 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
632 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
633 case I915_OVERLAY_YUV422
:
634 cmd
|= OCMD_YUV_422_PLANAR
;
636 case I915_OVERLAY_YUV420
:
637 cmd
|= OCMD_YUV_420_PLANAR
;
639 case I915_OVERLAY_YUV411
:
640 case I915_OVERLAY_YUV410
:
641 cmd
|= OCMD_YUV_410_PLANAR
;
644 } else { /* YUV packed */
645 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
646 case I915_OVERLAY_YUV422
:
647 cmd
|= OCMD_YUV_422_PACKED
;
649 case I915_OVERLAY_YUV411
:
650 cmd
|= OCMD_YUV_411_PACKED
;
654 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
655 case I915_OVERLAY_NO_SWAP
:
657 case I915_OVERLAY_UV_SWAP
:
660 case I915_OVERLAY_Y_SWAP
:
663 case I915_OVERLAY_Y_AND_UV_SWAP
:
664 cmd
|= OCMD_Y_AND_UV_SWAP
;
672 static int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
673 struct drm_i915_gem_object
*new_bo
,
674 struct put_image_params
*params
)
677 struct overlay_registers __iomem
*regs
;
678 bool scale_changed
= false;
679 struct drm_device
*dev
= overlay
->dev
;
680 u32 swidth
, swidthsw
, sheight
, ostride
;
682 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
683 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
686 ret
= intel_overlay_release_old_vid(overlay
);
690 ret
= i915_gem_object_pin_to_display_plane(new_bo
, 0, NULL
);
694 ret
= i915_gem_object_put_fence(new_bo
);
698 if (!overlay
->active
) {
700 regs
= intel_overlay_map_regs(overlay
);
705 oconfig
= OCONF_CC_OUT_8BIT
;
706 if (IS_GEN4(overlay
->dev
))
707 oconfig
|= OCONF_CSC_MODE_BT709
;
708 oconfig
|= overlay
->crtc
->pipe
== 0 ?
709 OCONF_PIPE_A
: OCONF_PIPE_B
;
710 iowrite32(oconfig
, ®s
->OCONFIG
);
711 intel_overlay_unmap_regs(overlay
, regs
);
713 ret
= intel_overlay_on(overlay
);
718 regs
= intel_overlay_map_regs(overlay
);
724 iowrite32((params
->dst_y
<< 16) | params
->dst_x
, ®s
->DWINPOS
);
725 iowrite32((params
->dst_h
<< 16) | params
->dst_w
, ®s
->DWINSZ
);
727 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
728 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
730 tmp_width
= params
->src_w
;
732 swidth
= params
->src_w
;
733 swidthsw
= calc_swidthsw(overlay
->dev
, params
->offset_Y
, tmp_width
);
734 sheight
= params
->src_h
;
735 iowrite32(new_bo
->gtt_offset
+ params
->offset_Y
, ®s
->OBUF_0Y
);
736 ostride
= params
->stride_Y
;
738 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
739 int uv_hscale
= uv_hsubsampling(params
->format
);
740 int uv_vscale
= uv_vsubsampling(params
->format
);
742 swidth
|= (params
->src_w
/uv_hscale
) << 16;
743 tmp_U
= calc_swidthsw(overlay
->dev
, params
->offset_U
,
744 params
->src_w
/uv_hscale
);
745 tmp_V
= calc_swidthsw(overlay
->dev
, params
->offset_V
,
746 params
->src_w
/uv_hscale
);
747 swidthsw
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
748 sheight
|= (params
->src_h
/uv_vscale
) << 16;
749 iowrite32(new_bo
->gtt_offset
+ params
->offset_U
, ®s
->OBUF_0U
);
750 iowrite32(new_bo
->gtt_offset
+ params
->offset_V
, ®s
->OBUF_0V
);
751 ostride
|= params
->stride_UV
<< 16;
754 iowrite32(swidth
, ®s
->SWIDTH
);
755 iowrite32(swidthsw
, ®s
->SWIDTHSW
);
756 iowrite32(sheight
, ®s
->SHEIGHT
);
757 iowrite32(ostride
, ®s
->OSTRIDE
);
759 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
761 update_colorkey(overlay
, regs
);
763 iowrite32(overlay_cmd_reg(params
), ®s
->OCMD
);
765 intel_overlay_unmap_regs(overlay
, regs
);
767 ret
= intel_overlay_continue(overlay
, scale_changed
);
771 overlay
->old_vid_bo
= overlay
->vid_bo
;
772 overlay
->vid_bo
= new_bo
;
777 i915_gem_object_unpin(new_bo
);
781 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
783 struct overlay_registers __iomem
*regs
;
784 struct drm_device
*dev
= overlay
->dev
;
787 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
788 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
790 ret
= intel_overlay_recover_from_interrupt(overlay
);
794 if (!overlay
->active
)
797 ret
= intel_overlay_release_old_vid(overlay
);
801 regs
= intel_overlay_map_regs(overlay
);
802 iowrite32(0, ®s
->OCMD
);
803 intel_overlay_unmap_regs(overlay
, regs
);
805 ret
= intel_overlay_off(overlay
);
809 intel_overlay_off_tail(overlay
);
813 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
814 struct intel_crtc
*crtc
)
816 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
821 /* can't use the overlay with double wide pipe */
822 if (INTEL_INFO(overlay
->dev
)->gen
< 4 &&
823 (I915_READ(PIPECONF(crtc
->pipe
)) & (PIPECONF_DOUBLE_WIDE
| PIPECONF_ENABLE
)) != PIPECONF_ENABLE
)
829 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
831 struct drm_device
*dev
= overlay
->dev
;
832 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
833 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
836 /* XXX: This is not the same logic as in the xorg driver, but more in
837 * line with the intel documentation for the i965
839 if (INTEL_INFO(dev
)->gen
>= 4) {
840 /* on i965 use the PGM reg to read out the autoscaler values */
841 ratio
= I915_READ(PFIT_PGM_RATIOS
) >> PFIT_VERT_SCALE_SHIFT_965
;
843 if (pfit_control
& VERT_AUTO_SCALE
)
844 ratio
= I915_READ(PFIT_AUTO_RATIOS
);
846 ratio
= I915_READ(PFIT_PGM_RATIOS
);
847 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
850 overlay
->pfit_vscale_ratio
= ratio
;
853 static int check_overlay_dst(struct intel_overlay
*overlay
,
854 struct drm_intel_overlay_put_image
*rec
)
856 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
858 if (rec
->dst_x
< mode
->hdisplay
&&
859 rec
->dst_x
+ rec
->dst_width
<= mode
->hdisplay
&&
860 rec
->dst_y
< mode
->vdisplay
&&
861 rec
->dst_y
+ rec
->dst_height
<= mode
->vdisplay
)
867 static int check_overlay_scaling(struct put_image_params
*rec
)
871 /* downscaling limit is 8.0 */
872 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
875 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
882 static int check_overlay_src(struct drm_device
*dev
,
883 struct drm_intel_overlay_put_image
*rec
,
884 struct drm_i915_gem_object
*new_bo
)
886 int uv_hscale
= uv_hsubsampling(rec
->flags
);
887 int uv_vscale
= uv_vsubsampling(rec
->flags
);
892 /* check src dimensions */
893 if (IS_845G(dev
) || IS_I830(dev
)) {
894 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
895 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
898 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
899 rec
->src_width
> IMAGE_MAX_WIDTH
)
903 /* better safe than sorry, use 4 as the maximal subsampling ratio */
904 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
905 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
908 /* check alignment constraints */
909 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
910 case I915_OVERLAY_RGB
:
911 /* not implemented */
914 case I915_OVERLAY_YUV_PACKED
:
918 depth
= packed_depth_bytes(rec
->flags
);
922 /* ignore UV planes */
926 /* check pixel alignment */
927 if (rec
->offset_Y
% depth
)
931 case I915_OVERLAY_YUV_PLANAR
:
932 if (uv_vscale
< 0 || uv_hscale
< 0)
934 /* no offset restrictions for planar formats */
941 if (rec
->src_width
% uv_hscale
)
944 /* stride checking */
945 if (IS_I830(dev
) || IS_845G(dev
))
950 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
952 if (IS_GEN4(dev
) && rec
->stride_Y
< 512)
955 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
957 if (rec
->stride_Y
> tmp
|| rec
->stride_UV
> 2*1024)
960 /* check buffer dimensions */
961 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
962 case I915_OVERLAY_RGB
:
963 case I915_OVERLAY_YUV_PACKED
:
964 /* always 4 Y values per depth pixels */
965 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
968 tmp
= rec
->stride_Y
*rec
->src_height
;
969 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
973 case I915_OVERLAY_YUV_PLANAR
:
974 if (rec
->src_width
> rec
->stride_Y
)
976 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
979 tmp
= rec
->stride_Y
* rec
->src_height
;
980 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
983 tmp
= rec
->stride_UV
* (rec
->src_height
/ uv_vscale
);
984 if (rec
->offset_U
+ tmp
> new_bo
->base
.size
||
985 rec
->offset_V
+ tmp
> new_bo
->base
.size
)
994 * Return the pipe currently connected to the panel fitter,
995 * or -1 if the panel fitter is not present or not in use
997 static int intel_panel_fitter_pipe(struct drm_device
*dev
)
999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1002 /* i830 doesn't have a panel fitter */
1006 pfit_control
= I915_READ(PFIT_CONTROL
);
1008 /* See if the panel fitter is in use */
1009 if ((pfit_control
& PFIT_ENABLE
) == 0)
1012 /* 965 can place panel fitter on either pipe */
1014 return (pfit_control
>> 29) & 0x3;
1016 /* older chips can only use pipe 1 */
1020 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1021 struct drm_file
*file_priv
)
1023 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1024 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1025 struct intel_overlay
*overlay
;
1026 struct drm_mode_object
*drmmode_obj
;
1027 struct intel_crtc
*crtc
;
1028 struct drm_i915_gem_object
*new_bo
;
1029 struct put_image_params
*params
;
1032 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1033 overlay
= dev_priv
->overlay
;
1035 DRM_DEBUG("userspace bug: no overlay\n");
1039 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1040 mutex_lock(&dev
->mode_config
.mutex
);
1041 mutex_lock(&dev
->struct_mutex
);
1043 ret
= intel_overlay_switch_off(overlay
);
1045 mutex_unlock(&dev
->struct_mutex
);
1046 mutex_unlock(&dev
->mode_config
.mutex
);
1051 params
= kmalloc(sizeof(struct put_image_params
), GFP_KERNEL
);
1055 drmmode_obj
= drm_mode_object_find(dev
, put_image_rec
->crtc_id
,
1056 DRM_MODE_OBJECT_CRTC
);
1061 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
1063 new_bo
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
,
1064 put_image_rec
->bo_handle
));
1065 if (&new_bo
->base
== NULL
) {
1070 mutex_lock(&dev
->mode_config
.mutex
);
1071 mutex_lock(&dev
->struct_mutex
);
1073 if (new_bo
->tiling_mode
) {
1074 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1079 ret
= intel_overlay_recover_from_interrupt(overlay
);
1083 if (overlay
->crtc
!= crtc
) {
1084 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1085 ret
= intel_overlay_switch_off(overlay
);
1089 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1093 overlay
->crtc
= crtc
;
1094 crtc
->overlay
= overlay
;
1096 /* line too wide, i.e. one-line-mode */
1097 if (mode
->hdisplay
> 1024 &&
1098 intel_panel_fitter_pipe(dev
) == crtc
->pipe
) {
1099 overlay
->pfit_active
= 1;
1100 update_pfit_vscale_ratio(overlay
);
1102 overlay
->pfit_active
= 0;
1105 ret
= check_overlay_dst(overlay
, put_image_rec
);
1109 if (overlay
->pfit_active
) {
1110 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1111 overlay
->pfit_vscale_ratio
);
1112 /* shifting right rounds downwards, so add 1 */
1113 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1114 overlay
->pfit_vscale_ratio
) + 1;
1116 params
->dst_y
= put_image_rec
->dst_y
;
1117 params
->dst_h
= put_image_rec
->dst_height
;
1119 params
->dst_x
= put_image_rec
->dst_x
;
1120 params
->dst_w
= put_image_rec
->dst_width
;
1122 params
->src_w
= put_image_rec
->src_width
;
1123 params
->src_h
= put_image_rec
->src_height
;
1124 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1125 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1126 if (params
->src_scan_h
> params
->src_h
||
1127 params
->src_scan_w
> params
->src_w
) {
1132 ret
= check_overlay_src(dev
, put_image_rec
, new_bo
);
1135 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1136 params
->stride_Y
= put_image_rec
->stride_Y
;
1137 params
->stride_UV
= put_image_rec
->stride_UV
;
1138 params
->offset_Y
= put_image_rec
->offset_Y
;
1139 params
->offset_U
= put_image_rec
->offset_U
;
1140 params
->offset_V
= put_image_rec
->offset_V
;
1142 /* Check scaling after src size to prevent a divide-by-zero. */
1143 ret
= check_overlay_scaling(params
);
1147 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1151 mutex_unlock(&dev
->struct_mutex
);
1152 mutex_unlock(&dev
->mode_config
.mutex
);
1159 mutex_unlock(&dev
->struct_mutex
);
1160 mutex_unlock(&dev
->mode_config
.mutex
);
1161 drm_gem_object_unreference_unlocked(&new_bo
->base
);
1168 static void update_reg_attrs(struct intel_overlay
*overlay
,
1169 struct overlay_registers __iomem
*regs
)
1171 iowrite32((overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff),
1173 iowrite32(overlay
->saturation
, ®s
->OCLRC1
);
1176 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1180 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1183 for (i
= 0; i
< 3; i
++) {
1184 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1191 static bool check_gamma5_errata(u32 gamma5
)
1195 for (i
= 0; i
< 3; i
++) {
1196 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1203 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1205 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1206 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1207 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1208 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1209 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1210 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1211 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1214 if (!check_gamma5_errata(attrs
->gamma5
))
1220 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1221 struct drm_file
*file_priv
)
1223 struct drm_intel_overlay_attrs
*attrs
= data
;
1224 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1225 struct intel_overlay
*overlay
;
1226 struct overlay_registers __iomem
*regs
;
1229 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1230 overlay
= dev_priv
->overlay
;
1232 DRM_DEBUG("userspace bug: no overlay\n");
1236 mutex_lock(&dev
->mode_config
.mutex
);
1237 mutex_lock(&dev
->struct_mutex
);
1240 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1241 attrs
->color_key
= overlay
->color_key
;
1242 attrs
->brightness
= overlay
->brightness
;
1243 attrs
->contrast
= overlay
->contrast
;
1244 attrs
->saturation
= overlay
->saturation
;
1246 if (!IS_GEN2(dev
)) {
1247 attrs
->gamma0
= I915_READ(OGAMC0
);
1248 attrs
->gamma1
= I915_READ(OGAMC1
);
1249 attrs
->gamma2
= I915_READ(OGAMC2
);
1250 attrs
->gamma3
= I915_READ(OGAMC3
);
1251 attrs
->gamma4
= I915_READ(OGAMC4
);
1252 attrs
->gamma5
= I915_READ(OGAMC5
);
1255 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1257 if (attrs
->contrast
> 255)
1259 if (attrs
->saturation
> 1023)
1262 overlay
->color_key
= attrs
->color_key
;
1263 overlay
->brightness
= attrs
->brightness
;
1264 overlay
->contrast
= attrs
->contrast
;
1265 overlay
->saturation
= attrs
->saturation
;
1267 regs
= intel_overlay_map_regs(overlay
);
1273 update_reg_attrs(overlay
, regs
);
1275 intel_overlay_unmap_regs(overlay
, regs
);
1277 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1281 if (overlay
->active
) {
1286 ret
= check_gamma(attrs
);
1290 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1291 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1292 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1293 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1294 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1295 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1301 mutex_unlock(&dev
->struct_mutex
);
1302 mutex_unlock(&dev
->mode_config
.mutex
);
1307 void intel_setup_overlay(struct drm_device
*dev
)
1309 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1310 struct intel_overlay
*overlay
;
1311 struct drm_i915_gem_object
*reg_bo
;
1312 struct overlay_registers __iomem
*regs
;
1315 if (!HAS_OVERLAY(dev
))
1318 overlay
= kzalloc(sizeof(struct intel_overlay
), GFP_KERNEL
);
1322 mutex_lock(&dev
->struct_mutex
);
1323 if (WARN_ON(dev_priv
->overlay
))
1328 reg_bo
= i915_gem_alloc_object(dev
, PAGE_SIZE
);
1331 overlay
->reg_bo
= reg_bo
;
1333 if (OVERLAY_NEEDS_PHYSICAL(dev
)) {
1334 ret
= i915_gem_attach_phys_object(dev
, reg_bo
,
1335 I915_GEM_PHYS_OVERLAY_REGS
,
1338 DRM_ERROR("failed to attach phys overlay regs\n");
1341 overlay
->flip_addr
= reg_bo
->phys_obj
->handle
->busaddr
;
1343 ret
= i915_gem_object_pin(reg_bo
, PAGE_SIZE
, true, false);
1345 DRM_ERROR("failed to pin overlay register bo\n");
1348 overlay
->flip_addr
= reg_bo
->gtt_offset
;
1350 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1352 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1357 /* init all values */
1358 overlay
->color_key
= 0x0101fe;
1359 overlay
->brightness
= -19;
1360 overlay
->contrast
= 75;
1361 overlay
->saturation
= 146;
1363 regs
= intel_overlay_map_regs(overlay
);
1367 memset_io(regs
, 0, sizeof(struct overlay_registers
));
1368 update_polyphase_filter(regs
);
1369 update_reg_attrs(overlay
, regs
);
1371 intel_overlay_unmap_regs(overlay
, regs
);
1373 dev_priv
->overlay
= overlay
;
1374 mutex_unlock(&dev
->struct_mutex
);
1375 DRM_INFO("initialized overlay support\n");
1379 if (!OVERLAY_NEEDS_PHYSICAL(dev
))
1380 i915_gem_object_unpin(reg_bo
);
1382 drm_gem_object_unreference(®_bo
->base
);
1384 mutex_unlock(&dev
->struct_mutex
);
1389 void intel_cleanup_overlay(struct drm_device
*dev
)
1391 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1393 if (!dev_priv
->overlay
)
1396 /* The bo's should be free'd by the generic code already.
1397 * Furthermore modesetting teardown happens beforehand so the
1398 * hardware should be off already */
1399 BUG_ON(dev_priv
->overlay
->active
);
1401 drm_gem_object_unreference_unlocked(&dev_priv
->overlay
->reg_bo
->base
);
1402 kfree(dev_priv
->overlay
);
1405 #ifdef CONFIG_DEBUG_FS
1406 #include <linux/seq_file.h>
1408 struct intel_overlay_error_state
{
1409 struct overlay_registers regs
;
1415 static struct overlay_registers __iomem
*
1416 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
)
1418 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
1419 struct overlay_registers __iomem
*regs
;
1421 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1422 /* Cast to make sparse happy, but it's wc memory anyway, so
1423 * equivalent to the wc io mapping on X86. */
1424 regs
= (struct overlay_registers __iomem
*)
1425 overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1427 regs
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
1428 overlay
->reg_bo
->gtt_offset
);
1433 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
1434 struct overlay_registers __iomem
*regs
)
1436 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1437 io_mapping_unmap_atomic(regs
);
1441 struct intel_overlay_error_state
*
1442 intel_overlay_capture_error_state(struct drm_device
*dev
)
1444 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1445 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1446 struct intel_overlay_error_state
*error
;
1447 struct overlay_registers __iomem
*regs
;
1449 if (!overlay
|| !overlay
->active
)
1452 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1456 error
->dovsta
= I915_READ(DOVSTA
);
1457 error
->isr
= I915_READ(ISR
);
1458 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1459 error
->base
= (__force
long)overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1461 error
->base
= overlay
->reg_bo
->gtt_offset
;
1463 regs
= intel_overlay_map_regs_atomic(overlay
);
1467 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1468 intel_overlay_unmap_regs_atomic(overlay
, regs
);
1478 intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
)
1480 seq_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1481 error
->dovsta
, error
->isr
);
1482 seq_printf(m
, " Register file at 0x%08lx:\n",
1485 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)